EE276 – Digital Electronic Circuits

Arithmetic Circuits

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 Topics

• Binary Adders
• Binary Ripple Carry Adder
• BCD Airthmetic
• Binary Subtraction
• Binary Adder-Subtractors
• Binary Multipliers
• Comparator
Binary Arithmetic Circuits
Recall: Arithmetic -- addition

Binary addition is similar to decimal arithmetic

No carries 1 0 1 1 0 0 Carries

0 1 1 0 0 1 0 1 1 0
+ 1 0 0 0 1 + 1 0 1 1 1

1 1 1 0 1 1 0 1 1 0 1
Remember:
1+1 is 2 (or (10)2), which results in a carry
1+1+1 is 3 (or (11)2) which also results in a carry
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Half Adder (One bit Adder)

▪ S = XY’ + X’Y
=XY
▪ C = X.Y

Capable of adding only two

Bits but no Carry in

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Full Adder

x y

Full Adder
Cout Z

▪ Three inputs:
❑X
❑Y
❑Third input is Cin → Z
▪ Two outputs:
❑Sum
❑ Cout

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FA: Straight Forward Implementation

K Map for S

S
Z

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FA: Straight Forward Implementation

K Map for C

X
Y

C
X
Z

C = XY +XZ+YZ
Y
Z

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 Implementation Issues

C = XY +XZ+YZ

o Implementation need
Nine Gates: Seven AND gates and two OR Gates!!

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Other Alternatives

o Use of hierarchy to design a 1-bit full adder from

two half adders.
o Also, share logic between the Sum output and Carry
output.

▪ Half Adder ▪ Full Adder

S=XY S=XYZ
C = XY C = XY + XZ + YZ

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A Different Way to Represent C

XYZ
YZ
00 01 11 10
X
0 1
1 1 1 1
XY

XYZ

C = XY + XYZ + XYZ

C = XY + Z (XY + XY)

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Two Half Adders (and an OR)

x y

Full Adder
C Z

S
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Binary Ripple Carry Adder
 Binary Ripple-Carry Adder

A Parallel binary adder is a digital circuit that produces the

arithmetic sum of two binary numbers using only combinational
logic.
The parallel adder uses “n” full adders in parallel, with all input
bits applied simultaneously to produce the sum.
The full adders are connected in cascade, with the carry output
from one full adder connected to the carry input of the next full
adder.

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Binary Ripple-Carry Adder

Straightforward – connect full adders

Carry-out to carry-in chain
C0 in case this is part of larger chain, maybe just set to zero

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 Problems with this Design

Delay
Approx how much?

A3 A2 A1 A0
B3 B2 B1 B0

C3 C2 C1 The "long path" is from A0 or

C0
B0 through the circuit to S3

C4
S3 S2 S1 S0
The gate-level propagation path for a 4-bit 16
ripple carry adder
Carry Propagation

C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1(G0 + P0C) = G1 + P1G0 + P1P0C0

C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 +P2P1P0C0

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Carry lookahead carry generator

C3 = G2 + P2G1 + P2P1G0
+P2P1P0C0

C2 = G1 + P1G0 + P1P0C0

C 1 = G 0 + P0 C 0

C0 = input carry

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Four-bit adder with carry lookahead

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Binary Coded Decimal (BCD)
 Recall: Binary Coded Decimal

Decimal BCD
0 0000
Binary Coded Decimal (BCD) 1 0001
Each Decimal Digit is represented 2 0010
by 4 bits 3 0011
(0 – 9)  Valid combinations 4 0100
(10 – 15)  Invalid combinations 5 0101
6 0110
7 0111
8 1000
9 1001

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BCD Addition
One decimal digit + one decimal digit
If the result is 1 decimal digit ( ≤ 9 ), then it is a simple binary addition
Example:

5 0101
+ 2 + 0010
7 0111

If the result is two decimal digits ( ≥ 10 ), then binary addition gives invalid
combinations
Example:
6 0110
+ 5 + 0101
0001 0001 11 1011 22
BCD Addition

If the binary result

is greater than 9, 6 0110
correct the result by
adding a “6” + 5 + 0101
11 1011
+ 0110
0001 0001
Multiple Decimal Digits

Two Decimal Digits

241

0010 0100 0001

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 BCD Addition

Four binary digits count up to 15 (1111) but in BCD we only use the representations
up to 9 (1001).
The difference between 15 and 9 is 6. If you want 9+1 to produce 10, which is 1 0000,
you have to add 6 to make 1010 wrap to 1 0000.
It is done to skip the six invalid states of binary coded decimal i.e from 10 to 15 and
again return to the BCD codes.

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BCD Arithmetic

8 1000 Eight
+5 +0101 Plus Five
13 1101 is 13 (> 9)
▪ Note that the result is MORE THAN 9, so must be
represented by two digits!
▪ To correct the digit, add 6
8 1000 Eight
+5 +0101 Plus 5
13 1101 is 13 (> 9)
+0110 so add 6
carry = 1 0011 leaving 3 + cy
0001 | 0011 Final answer (two digits)

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BCD Addition Circuit

Design a BCD Adder that adds two BCD digits.

Constraints:
Use 4-bit Binary Adders
Hints:
A detection circuit that detects invalid BCD digits will need to be
designed.

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 Contd..

BCD # 1 BCD # 2
Addend Augend

Input
4-bit binary adder
Carry

Detection
Circuit for
Output Invalid BCD
Carry 0 or 6 Add 0 if result is valid
Add 6 if result is invalid

4-bit binary adder

BCD Sum
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Contd…
Z3 Z2 Z1 Z 0
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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Example: Seven-Segment Decoder

yz
wx

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Binary Subtractor
Binary Subtraction: Subtraction via Complements
the concept of Complements.
X = Y – Z ➔ X = Y + complement(Z)

There are two types of complements for each base-r system

The radix complement, the (r’s) complement.
The diminished radix complement, (r-1)’s comp.
For Decimal System
10’s complement
9’s complement
For Binary Systems
2’s complement
1’s complement

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Binary Subtraction
1’s Complement
1’s Complement (Diminished Radix Complement)
All ‘0’s become ‘1’s
All ‘1’s become ‘0’s
Example (10110000)2
 (01001111)2

10110000
+ 01001111
11111111
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 1’s Complement: Example

1 0 1 0 1 0 1 0

0 1 0 1 0 1 0 1

Notice that the 1’s complement of the number 10101010 can be

obtained by complementing each bit

2n - 1 1 1 1 1 1 1 1

-N 0 1 0 1 0 1 0
1’s Compl. 1 0 1 0 1 0 1
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2’s Complement

2’s Complement (Radix Complement)

Take 1’s complement then add 1
Toggle all bits to the left of the first ‘1’ from the right
Example:

Number: 10110000 10110000

1’s Comp.: 01001111
+ 1
01010000 01010000

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 Example

2n 1 0 0 0 0 0 0

-N 0 1 1 0 0 1
1’s Comp 1 0 0 1 1 0
2’s Compl. 1 0 0 1 1 1

2’s complement of the number 011001 can be obtained by complementing

each bit and adding 1.

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Example: Incorrect Result

Minuend is smaller than Subtrahend

Borrow 1 1 1 0 0

(M) Minuend 1 0 0 1 1
(N) Subtrahend - 1 1 1 1 0
Difference 1 0 1 0 1

Incorrect Result!!

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 Example

If no borrow, then result is

non-negative (minuend >=
subtrahend).
Borrow 1 1 1 0 0

(M) Minuend 1 0 0 1 1 Since there is borrow, result

must be negative.
(N) Subtrahend - 1 1 1 1 0
Difference 1 0 1 0 1 The result must be corrected
to a negative number.
Correct Diff - 0 1 0 1 1
19 – 30 = -11

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Subtraction: Algorithm #1
Algorithm: Subtraction of two n-digit Numbers M-N

1. Subtract N from M
✓ If no borrow, then M  N and result is OK
! Else, N > M so result must be subtracted from 2n and a minus sign should
be appended
2. NOTE: Subtraction of a binary number from 2n to obtain an n-digit result is
called 2’s complement

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Adder/Subtractor Circuit!!

Binary Adder Binary Subtractor

EXPENSIVE!!

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Subtraction: Algorithm #2
Subtraction of Unsigned Numbers Using Complements

1. M – N Equivalent to M + (2’s complement of N)

2. Add (2’s complement of N) to M
This is M + (2n – N) = M – N + 2n
Notice we are using addition to achieve subtraction.
3. If M  N, will generate carry!
• Result is correct → Simply discard carry
• Result is positive M - N
4. If M < N, no end carry will be generated!
• Make Correction → Take 2’s complement of result
• Place minus sign in front

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 Example
Example-1
❑ X = 1010100 minus Y = 1000011
❑ Notice that X > Y
❑ The 2’s complement of Y=1000011 is obtained first by getting the 1’s
complement → 0111100 and then adding 1 → (0111101)

X 1 0 1 0 1 0 0
+ 2’s comp Y 0 1 1 1 1 0 1
Sum 1 0 0 1 0 0 0 1
Example-2
Y = 1000011 minus X = 1010100
Notice Y < X

Y 1 0 0 0 0 1 1
+ 2’s comp X 0 1 0 1 1 0 0
Sum 1 1 0 1 1 1 1
No end carry
Answer: - (2’s complement of Sum)
- 0010001
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Adder/Subtractor Circuit
Adder-Subtractor
I. By using 2’s complement approach we were able to get rid of the design of
a subtractor.
II. Need only adder and complementer for input to subtract
III. Need selective complementer to make negative output back from 2’s
complement

B1 B1 B0 B0

01
MUX S0 MUX S0 S

A1 A0

C2 C1
FA FA C0

S1 S0 45
Selective 1’s Complementer

Control

01

When X = 0 we transfer
Y to output Control
When X = 1 we
complement Y

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S B In Design
0 0 0
0 1 1 Subtraction of Unsigned Numbers Using Complements
1 0 1
1 1 0
S low for add,
01 high for subtract

Inverts each bit

of B if S is 1

Adds 1 to make
2’s complement

Selective 2’s Complementer

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Signed Numbers
 Negative Numbers
Computers Represent Information in ‘0’s and ‘1’s
‘+’ and ‘−’ signs have to be represented in ‘0’s and ‘1’s
3 Systems
Signed Magnitude
1’s Complement
2’s Complement
All three use the left-most bit to represent the sign:
‘0’  positive
‘1’  negative

Represent +9 in different ways

Signed magnitude 00001001
1’s Complement 00001001
2’s Complement 00001001

Represent -9 in different ways

Signed magnitude 10001001
1’s Complement 11110110
2’s Complement 11110111

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Advantages/Disadvantages

Signed magnitude has problem that we need to correct after

subtraction
One’s complement has a positive and negative zero
✓ Two’s complement is most popular
i.e., arithmetic operations are easy
No correction is required.

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Binary Subtraction Using 2’s Comp. Addition

Change “Subtraction” to “Addition”

If “Carry” = 1
ignore it, and the
result is positive (5)10 – (1)10 (5)10 – (6)10
(in Binary)
If “Carry” = 0 (+5)10 + (-1)10 (+5)10 + (-6)10
then the result
is negative
(in 2’s Comp.)
0101 0101
+ 1111 + 1010

1 0100 0 1111

+4 −1

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Operation in 2s complement
Addition of Two Positive Numbers
Addition
(+6) + 13 = +19
00000110 → +6
+00001101 → +13
--------------
00010011 → +19
If a carry out appears it should be discarded.
Addition of a Positive and Negative Numbers
Addition
(-6) + 13 = +7
11111010 (this is 2’s comp of +6)
+00001101
--------------
1 00000111 +7
The carry out is discarded

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Contd…
Subtraction
(+6) – (+13) = -7
00000110 00000110
- 00001101 → + 11110011 (2’s comp)
-------------- -----------
11111001
What is 11111001?
Take its 2’s complement=> 00000111
The magnitude is 7
So it must be -7

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Circuit for 2’s complement Numbers

No Correction is needed if the signed numbers are in 2’s

complement representation

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Overflow
 Overflow
In order to obtain a correct answer when adding and subtracting, we must ensure
that the result has a sufficient number of bits to accommodate the sum.
If we start with two n-bit numbers and we end up with a number that is n+1 bits,
we say an overflow has occurred.

Two cases of overflow for addition of signed numbers

Two large positive numbers overflow into sign bit
Not enough room for result
Two large negative numbers added
Same – not enough bits
Carry out can be OK

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 Examples

Two signed numbers +70 and +80 are stored in 8-bit registers.
The range of binary numbers, expressed in decimal, that each
register can accommodate is from +127 to -128.
Since the sum of the two stored numbers is 150, it exceeds the
capacity of an 8-bit register.
The same applies for -70 and -80.
Adding -70 + (-80) = -150

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 Overflow Detection

Carries: 0 1 Carries: 1 0
+70 0 1000110 -70 1 0111010
+80 0 1010000 -80 1 0110000
------ ------------- ---- -------------
+150 1 0010110 -150 0 1101010
1. The addition of +70 and +80 resulted in a negative number!
2. The addition of -70 and -80 also resulted in an incorrect value which is
positive number!
3. An overflow condition can be detected by observing the carry into the
sign bit position and the carry out of the sign bit position.
4. If the the carry in and carry out of the sign bit are not equal an overflow
has occurred.

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Circuit for Overflow Detection

Condition is that either Cn-1 or Cn is high, but not both

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Binary Multiplication
Binary Multiplication

Bit by bit

1 0 1 1 1
x 1 0 1 0
0 0 0 0 0
1 0 1 1 1
0 0 0 0 0
1 0 1 1 1

1 1 1 0 0 1 1 0

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Binary Multiplication: Example II

1 0 1 1
X 1 0 1

1 0 1 1
0 0 0 0
1 0 1 1
1 1 0 1 1 1

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Multiplier

Multiply by doing single-bit multiplies and shifts

Combinational circuit to accomplish this?

The value of A0B0

Will either be 0 or 1

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Combinational Multiplier

AND
computes
A0 B0

Half adder
computes sum.
Will need FA for
larger multiplier.

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Larger Multiplier: Resources

For J multiplier bits and K multiplicand bits we need

oJ x K → AND gates
o(J-1) K-bit → adders to produce a product of J+K bits.

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Larger Multiplier
Multiplier
Multiplicand

A k=4-bit by j=3-bit
Binary Multiplier.

J = 3-bit (Multiplier)
K = 4-bit (Multiplicand)

Resources:
Jxk = 12 AND Gates
(J-1) Adders
Of k bits each

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Comparator

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Comparators

➢ Compare the magnitude of two binary numbers for the

purpose of establishing whether one is greater than, equal to,
or less than the other.
➢ A comparator makes use of a cascade connection of identical
subnetworks similar to the case of the parallel adder.
4 bit comparator
Consider two 4-bit binary numbers:
𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0

𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0
• For equality
A3 = B3, A2 = B2, A1 = B1, and A0 = B0
The digits are either 1 or 0, and the equality of each pair of bits
can be expressed
xi = Ai Bi + Ai‘B’i for i = 0, 1, 2, 3

For equality to exist, all xi variables must be equal to 1

(A = B) = x3x2x1x0 1
Four-bit magnitude comparator
1 Bit comparator

Consider two n-bit binary numbers:

𝐴 = 𝐴𝑛−1 ⋯ 𝐴𝑖 𝐴𝑖−1 ⋯ 𝐴1 𝐴0
𝐵 = 𝐵𝑛−1 ⋯ 𝐵𝑖 𝐵𝑖−1 ⋯ 𝐵1 𝐵0
Assume 𝐴𝑖 , 𝐵𝑖 are entering the subnetwork and that the binary
numbers are analyzed from right to left.
Subnetwork is called a 1-bit comparator.
Contd..
3 conditions describing the relative magnitudes of 𝐴𝑖−1 ⋯ 𝐴1 𝐴0 , 𝐵𝑖−1 ⋯ 𝐵1 𝐵0
𝐺𝑖 = 1 denotes 𝐴𝑖−1 ⋯ 𝐴1 𝐴0 > 𝐵𝑖−1 ⋯ 𝐵1 𝐵0
𝐸𝑖 = 1 denotes 𝐴𝑖−1 ⋯ 𝐴1 𝐴0 = 𝐵𝑖−1 ⋯ 𝐵1 𝐵0
𝐿𝑖 = 1 denotes 𝐴𝑖−1 ⋯ 𝐴1 𝐴0 < 𝐵𝑖−1 ⋯ 𝐵1 𝐵0
1-bit comparator is a 5-input 3-output network

Rules:
If 𝐴𝑖 = 0, 𝐵𝑖 = 1 then 𝐿𝑖 = 1
If 𝐴𝑖 = 1, 𝐵𝑖 = 0 then 𝐺𝑖 = 1
If 𝐴𝑖 = 𝐵𝑖 and 𝐿𝑖−1 = 1 then 𝐿𝑖 = 1
If 𝐴𝑖 = 𝐵𝑖 and 𝐺𝑖−1 = 1 then 𝐺𝑖 = 1
If 𝐴𝑖 = 𝐵𝑖 and 𝐸𝑖−1 = 1 then 𝐸𝑖 = 1
Can use this to construct a truth table.

Minimal Sum Boolean Expressions:

𝐺𝑖+1 = 𝐴𝑖 𝐵𝑖 + 𝐴𝑖 𝐺𝑖 + 𝐵𝑖 𝐺𝑖
𝐸𝑖+1 = 𝐴𝑖 𝐵𝑖 𝐸𝑖 + 𝐴𝑖 𝐵𝑖 𝐸𝑖
𝐿𝑖+1 = 𝐴𝑖 𝐵𝑖 + 𝐵𝑖 𝐿𝑖 + 𝐴𝑖 𝐿𝑖
Comparators Circuit
Comparators