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1 Bit ALU Design

The document outlines the design of a 1-bit Arithmetic Logic Unit (ALU) utilizing 2-to-4 decoders to perform addition, subtraction, logical AND, and logical OR operations based on 2-bit control inputs. It details the methodology, including the use of decoders for control signal selection and operation execution, as well as the expected outputs for each operation. The design demonstrates effective modularity and scalability for digital systems while ensuring accurate operation performance.

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aryan090920
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32 views4 pages

1 Bit ALU Design

The document outlines the design of a 1-bit Arithmetic Logic Unit (ALU) utilizing 2-to-4 decoders to perform addition, subtraction, logical AND, and logical OR operations based on 2-bit control inputs. It details the methodology, including the use of decoders for control signal selection and operation execution, as well as the expected outputs for each operation. The design demonstrates effective modularity and scalability for digital systems while ensuring accurate operation performance.

Uploaded by

aryan090920
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Design of a 1-Bit ALU Using 2-to-4 Decoders

1. Introduction
An Arithmetic Logic Unit (ALU) is a fundamental component of a digital system that performs

arithmetic and logical operations. This report focuses on designing a 1-bit ALU capable of

performing addition, subtraction, logical AND, and logical OR operations. The design incorporates

control inputs to select the desired operation and utilizes 2-to-4 decoders to implement the logic.

2. Problem Statement
The objective is to design a 1-bit ALU that:

- Takes two 1-bit inputs, A and B.

- Performs one of four operations based on a 2-bit control input:

- 00: Addition

- 01: Subtraction

- 10: Logical AND

- 11: Logical OR

- Produces a 2-bit output (O1 O0):

- O1: Carry for addition, borrow for subtraction, or 0 for logical operations.

- O0: Result of the selected operation.

- Implements the design using five 2-to-4-line decoders:

- One decoder for control signal selection.

- Four decoders for generating the outputs corresponding to each operation.

3. Methodology
3.1 Design Approach

1. Input Components:

- Two 1-bit inputs (A, B).

- Two 1-bit control signals (C1, C0).


2. Control Decoder:

- A 2-to-4-line decoder is used to decode the control signals (C1, C0) and generate four enable

signals for the operations:

- Enable0: For addition (00).

- Enable1: For subtraction (01).

- Enable2: For AND (10).

- Enable3: For OR (11).

3. Operation Decoders:

- Four 2-to-4-line decoders are used, one for each operation.

- Outputs of the operation decoders (O1, O0) depend on the enable signal and the inputs (A, B).

4. Logic for Operations:

- Addition: Uses XOR for sum (O0) and AND for carry (O1).

- Subtraction: Uses XOR for difference (O0) and AND with NOT B for borrow (O1).

- AND: Logical AND operation for O0 and O1 = 0.

- OR: Logical OR operation for O0 and O1 = 0.

5. Output Selection:

- Use the enable signals from the control decoder to activate the appropriate operation decoder.

4. Implementation
4.1 Circuit Components

1. 2-to-4-line Decoder:

- Input: Two control bits (C1, C0).

- Output: Four enable signals.

2. Logical Gates:

- XOR, AND, OR, NOT gates for operation logic.

3. Output Decoders:

- One decoder per operation to map the inputs and enable signals to the outputs (O1, O0).
4.2 Circuit Diagram

(Diagram Placeholder for Implementation.)

5. Results and Interpretation


5.1 Expected Outputs

| Control (C1C0) | Operation | Inputs (A, B) | Output (O1 O0) |

|----------------|----------------|---------------|----------------|

| 00 | Addition | 0, 0 | 0, 0 |

| | | 0, 1 | 0, 1 |

| | | 1, 0 | 0, 1 |

| | | 1, 1 | 1, 0 |

| 01 | Subtraction | 0, 0 | 0, 0 |

| | | 0, 1 | 1, 1 |

| | | 1, 0 | 0, 1 |

| | | 1, 1 | 0, 0 |

| 10 | Logical AND | 0, 0 | 0, 0 |

| | | 0, 1 | 0, 0 |

| | | 1, 0 | 0, 0 |

| | | 1, 1 | 0, 1 |

| 11 | Logical OR | 0, 0 | 0, 0 |

| | | 0, 1 | 0, 1 |

| | | 1, 0 | 0, 1 |

| | | 1, 1 | 0, 1 |

5.2 Interpretation

The circuit performs the desired operation based on the control inputs. Outputs are verified to match
the truth tables for addition, subtraction, AND, and OR operations.

6. Conclusion
This design effectively demonstrates a 1-bit ALU using five 2-to-4 decoders. The modular design

ensures clarity and scalability for larger systems. The methodology confirms that the ALU performs

arithmetic and logical operations accurately, meeting the requirements specified.

7. References
1. M. Morris Mano, Digital Logic and Computer Design.

2. John F. Wakerly, Digital Design: Principles and Practices.

8. Appendices
A. Truth Tables for Operations

(Included in the Results section.)

B. Circuit Diagram

(Diagram Placeholder for Implementation.)

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