UNIT I

Digital Logic Families

 Syllabus
• Classification and Characteristics of digital Logic Families: Speed, power
dissipation, figure of merit, fan in, fan out, current, voltage, noise
immunity, operating temperatures and power supply requirements. TTL
logic. Operation of TTL NAND gate, active pull up, wired AND, open
collector output, unconnected inputs. Tri-State logic. CMOS logic: CMOS
inverter, NAND, NOR gates, unconnected inputs, wired logic, open drain
output. Interfacing CMOS and TTL, Data sheet specifications.
 Example Logic Families
• General comparison or three commonly available logic
families.

the most important to understand

 Digital IC
• There are many IC packages, differing in
physical size, environmental & power consumption conditions, and
circuit board mounting

The DIP (dual-in-line package)

has pins (leads) down the
two long sides of the
rectangular package.

The notch on one end,

is used to locate pin 1.
Some DIPs use a small
dot to locate pin 1.
 SSI Devices

• Each package contains a code identifying the

package
N74LS00

Manufacturers Code
Family
L Member
N = National Semiconductors 00 = Quad 2 input NAND
SN = Signetics LS
H 02 = Quad 2 input Nor
04 = Hex Invertors
Specification 20 = Dual 4 Input NAND
 INTRODUCTION
• Logic Family: It is a group of compatible
ICs with the same logic levels and the
supply voltages for performing various
logic functions
• They have been fabricated using a specific
circuit configuration.
• They are the building block of logic
circuits.
• It is set of techniques used to implement
logic within large scale ICs (LSI).
 ICs are integrated using following
integration techniques
• SSI (upto 12)
• MSI (12 to 99)
• LSI (100 to 9999)
• VLSI (10,000 to 99999)
• ULSI (> 100,000)
 Types of logic families
RTL
Saturated
DCTL

Bipolar Logic
Family DTL

TTL IIL
Logic
Families
HTL

Schottkey
Non- TTL
Saturated
Unipolar
Logic Family
ECL

MOSFET
 Basic Characteristics of ICs
• Propagation delay
• Power dissipation
• Fan in and fan out
• Noise immunity
• Power supply requirement
• Figure of merits i.e. speed power product
• Operating temperature
• Current and voltage parameters
 Fan out

• Also known as loading factor

• Defined as the maximum number of logic inputs that
an output can drive reliably
• A logic circuit that specify to have 10 fan out can
drive 10 logic inputs.The maximum number of
standard logic inputs that an output can drive reliably.
• Related to the current parameters (both in high and
low states.)
• For TTL (10),CMOS(50)
 Fan-Out
• A measure of the ability of the output of
one gate to drive the input(s) of
subsequent gates
• Usually specified as standard loads within
a single family
– e.g., an input to an inverter in the same family
• May have to compute based on current
drive requirements when mixing families
– Although mixing families is not usually
recommended
 Electrical Characteristics
• TTL • CMOS
– faster (some versions) – lower power consumption
– strong drive capability – simpler to make
– larger power consumption – greater packing density
– better noise immunity
– slower

• Complex IC’s contain many millions of transistors

• If constructed entirely from TTL type gates would melt
• A combination of technologies (families) may be used
• CMOS has become most popular and has had greatest development
 Fan-In
• Number of input signals to a gate
– Not an electrical property
– Function of the manufacturing process

NAND gate with a Fan-in

of 8
 Voltage & Current
• For a High-state gate driving a second gate, we define:
– VOH (min), high-level output voltage, the minimum voltage level that a
logic gate will produce as a logic 1 output.
– VIH (min), high-level input voltage, the minimum voltage level that a
logic gate will recognize as a logic 1 input. Voltage below this level
will not be accepted as high.
– IOH, high-level output current, current that flows from an output in the
logic 1 state under specified load conditions.
– IIH, high-level input current, current that flows into an input when a
logic 1 voltage is applied to that input.

I OH I IH
Test setup for
measuring
values VOH VIH
Ground
 Voltage & Current
• For a Low-state gate driving a second
gate, we define:
– VOL (max), low-level output voltage, the maximum voltage
level that a logic gate will produce as a logic 0 output.
– VIL (max), low-level input voltage, the maximum voltage
level that a logic gate will recognize as a logic 0 input.
Voltage above this value will not be accepted as low.
– IOL , low-level output current, current that flows from an
output in the logic 0 state under specified load conditions.
– IIL , low-level input current, current that flows into an input
when a logic 0 voltage is applied to that input.
I OL I IL
Inputs are
connected to Vcc
instead of V OL V IL
Ground
Ground
 Electrical Characteristics

logic 1
• Important characteristics are:

– VOHmin min value of output recognized as a ‘1’

– VIHmin min value input recognized as a ‘1’
indeterminate
input voltage
– VILmax max value of input recognized as a ‘0’
– VOLmax max value of output recognized as a ‘0’

logic 0 – Values outside the given range are not allowed.

 Logic Level & Voltage Range

Typical acceptable voltage ranges for positive logic 1

and logic 0 are shown below
• A logic gate with an input at a voltage level within the
‘indeterminate’ range will produce an unpredictable
output level.
5.0V
5.0V Logic 1
Logic 1 3.5V
2.5V Indeterminate
Indeterminate 1.5V
0.8V Logic 0
Logic 0
0V 0V
TTL CMOS
 Logic Level & Voltage Range

Typical acceptable voltage ranges for positive logic 1

and logic 0 are shown below
• A logic gate with an input at a voltage level within the
‘indeterminate’ range will produce an unpredictable
output level.
5.0V
5.0V Logic 1
Logic 1 3.5V
2.5V Indeterminate
Indeterminate 1.5V
0.8V Logic 0
Logic 0
0V 0V
TTL CMOS
 Noise Margin
• If noise in the circuit is high
enough it can push a logic 0 VOHmin
up or drop a logic 1 down logic 1
VIHmin
into the indeterminate or
“illegal” region
indeterminate
• The magnitude of the input voltage

voltage required to reach

this level is the noise margin VILmax
• Noise margin for logic high logic 0
VOLmax
is:
– NMH = VOHmin – VIHmin
 Noise
• Noise immunity refers to the circuit’s ability to tolerate
noise without changes in output voltage.
– A quantitative measure is called noise margin.

High-state noise margin: Low-state noise margin:

 Digital IC Terminology – Power Requirements
• The amount of power an IC requires is determined by the current, ICC
(or IDD) it draws from the supply.

– Actual power is the product ICC x VCC (IDD x VDD ).

In some logic circuits, average

current is computed based
on the assumption that gate
outputs are LOW half the
time and HIGH half the time.
 Current Sourcing/Sinking

• Current-sourcing action.
– When the output of gate 1 is HIGH, it supplies
current IIH to the input of gate 2.
• Which acts essentially as a resistance to ground.
– The output of gate 1 is acting as a source of
current for the gate 2 input.
 Current Sourcing/Sinking

• Current-sinking action.
– Input circuitry of gate 2 is represented as a resistance tied to +VCC
—the positive terminal of a power supply.
– When gate 1 output goes LOW, current will flow from the input
circuit of gate 2 back through the output resistance of gate 1, to
ground.
• Circuit output that drives the input of gate 2 must be able to sink
a current, IIL , coming from that input.
 Logic Family
The basic TTL logic circuit is the NAND gate.

Diode equivalent
for Q1 .

Basic TTL
NAND gate.
TTL NAND gate LOW output
• A TTL output acts as a current sink in the
LOW state because it receives current from
the input of the gate that it is driving.
Transistor Q4 of the driving
gate is on and essentially
“shorts” point X to ground.

LOW voltage at X forward-

biases the emitter–base
junction of Q1 & current
flows back through Q4.
• A TTL output acts as a current sink in the
LOW state because it receives current from
the input of the gate that it is driving.
Q4 is performing a current-
sinking action—deriving its
current from the input
current (IIL) of the load gate.

Q4 is often called the current-

sinking transistor or pull-
down transistor because
it brings the output voltage
down to its LOW state.
TTL NAND gate HIGH output
• A TTL output acts as a current source in the
HIGH state—a small reverse-bias leakage
current.
Transistor Q3 is supplying the
input current (IIH) required
by Q1 of the load gate.

Q3 is often called the current-

sourcing or pull-up transistor.

In more modern TTL series,

the pull-up circuit is made
up of two transistors.
Typical TTL series characteristics.
 Open Collector/Open Drain Outputs

• One solution to the problem of sharing a

common wire among gates is to remove the
active pull-up transistor from each gate’s
output circuit.
– In this way, none of the gates will ever try to
assert
a logic HIGH.
 Open Collector/Open Drain Outputs
TTL outputs modified this way
are called open-collector outputs.

CMOS outputs modified this way

are called open-drain outputs.
 IC Interfacing
• Interfacing means connecting output(s) of one
circuit/system to input(s) of another circuit/system.
• The simplest and most desirable interface circuit
between a driver and a load is a direct connection.
– Often a direct connection cannot be made due
to
a difference in electrical characteristics.
• An interface circuit is connected between the driver
and the load, to condition the driver output signal
so it is compatible with requirements of the load.
IC Interfacing
IC Interfacing
• Logic devices will be voltage-compatible,
and no interface will be necessary under the
following circumstances:

Nominal values for different families/series of digital devices.

 External pull-up resistor
is used when TTL drives CMOS.
 Equivalent CMOS output
circuits for both logic states.
• A substantial shift in voltage because driver
& load operate on different supply voltages
requires a voltage-level translator interface
circuit.

The simplest way to

accomplish this is with
a buffer that has an
open drain—with
a pull-up resistor.
• A substantial shift in voltage because driver
& load operate on different supply voltages
requires a voltage-level translator interface
circuit.
Another solution is
a dual-supply-level
translator circuit using
two different supply
voltages, one each
for inputs & outputs,
translating between
the two levels.
• A substantial shift in voltage because driver
& load operate on different supply voltages
requires a voltage-level translator interface
circuit.Another common solution is an interface using a
buffer from a series that can withstand higher input.

A low-voltage series
with 5-V tolerant
inputs
as an interface.
 Power Dissipation
• Static
– I2R losses due to passive components, no
input signal
• Dynamic
– I2R losses due to charging and discharging
capacitances through resistances, due to
input signal
 Speed-Power Product
• Speed (propagation delay) and power consumption are
the two most important performance parameters of a
digital IC.
• A simple means for measuring and comparing the
overall performance of an IC family is the speed-power
product (the smaller, the better).
• For example, an IC has
– an average propagation delay of 10 ns
– an average power dissipation of 5 mW
– the speed-power product = (10 ns) x (5 mW)
= 50 picoJoules (pJ)
Comparison of Logic Families
 7400 Series Evolution
• BJT storage time reduction by using a BC Schottky diode.
• Schottky diode has a Vfw=0.25V. When BC junction becomes forward
biased Schottky diode will bypass base current.
C

B
 Characteristics: TTL and
MOS
Remember:
• TTL stands for Transistor-Transistor Logic
– uses BJTs
• MOS stands for Metal Oxide Semiconductor
– uses FETs
• MOS can be classified into three sub-families:
– PMOS (P-channel)
– NMOS (N-channel)
– CMOS (Complementary MOS, most common)
 Transistor-Transistor Logic
Families
• Transistor-Transistor Logic Families:
– 74L Low power
– 74H High speed
– 74S Schottky
– 74LS Low power Schottky
– 74AS Advanced Schottky
– 74ALS Advance Low power
Schottky
 CMOS Logic Families

• CMOS Logic Families

– 40xx/45xx Metal-gate CMOS
– 74C TTL-compatible CMOS
– 74HC High speed CMOS
– 74ACT Advanced CMOS -TTL compatible