Digital ASIC Design

EELE 5331

Lecturer: Yushi Zhou

Department of Electrical Engineering

Email: yzhou30@lakeheadu.ca
 Manufacturing Process
• Introduction
• Fabrication processes
– Wafer preparation
– Photolithography
– Ion implantation
– Deposition, etching, etc.
• CMOS fabrication

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 1

 Introduction – 1
– Fabrication is a set of optical masks forms the central
interface between manufacturing process and the
desired circuits.
– Masks define the patterns that when transcribed
onto the different layers, form the elements of the
electronic devices and interconnecting wires.
– A successful fabrication requires the designer
adheres to design rule set defined by the foundry.
– Don’t forget packaging, the interface between the
silicon die and the real world, which has large
impacts on the performance, reliability, and the cost.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 2

 Introduction - 2
• A p-typ substrate (wafer)
serves as the foundation
upon which n-wells,
1959 source/drain regions,
gate dielectric,
polysilicon, n-well,
substrate ties, and metal
1980’s interconnects are built.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 3

 A Modern CMOS Process – 1

Dual well trench isolated CMOS

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 4

 A Modern CMOS Process - 2
GF130 nm process: 8 layers with 3 thick layers, 3 thin layers and 2
special layers for inductors.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 5

 CMOS Process
• How are various regions defined so accurately?
• How are then-wells and S/D regions built?
• How are the gate oxide and polysilicon fabricated?
• How are the gate oxide and polysilicon aligned with
the S/D regions?
• How are the contact windows created?
• How are the metal interconnect layers deposited?

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 6

 CMOS Process Flow
Modern CMOS technologies involve more than 200 processing
steps, but we simplify it to four steps:
1. wafer processing to produce the proper type of substrate.
2. photolithography to precisely define each region.
3. oxidation, deposition, and ion implantation to add materials to
the wafer.
4. etching to remove materials from the wafer.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 7

 Wafer Processing
• Formation of high quality wafer
• The size of the wafer is 4-12 in

From Wiki
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 8
 Photolithography
• Photolithography,
or simply
lithography, is the
first step in
transferring the
circuit layout
information to the
wafer.

• n-wells, S/D regions, contacts, polysilicon and metal interconnects.

• For fabrication purposes, we decompose the layout into these layers.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 9

 Photolithography Sequences-1

• The sequence associated with the lithography of each layer involves

one mask and three processing steps:
1. cover wafer with photoresist
2. align mask on top and expose to light
2023-10-023. etch exposed photoresist.
Yushi Zhou yzhou30@lakeheadu.ca 10
 Photolithography Sequences-2
• Two types of photoresists are used in processing.
1. A “negative” photoresist hardens in the areas exposed to
light and
2. A “positive” photoresist hardens in the areas not exposed to
light.

• The number of masks in a process heavily impacts the

overall cost of fabrication, eventually influencing the unit
price of the chip.

• In modern CMOS processes this number is around 30.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 11

 Oxidation-1
• Silicon can produce a very thin uniform-oxide layer on the
surface
• In areas between the devices, a thick layer of SiO2, called the
“field oxide” (FOX) is grown, providing the foundation for
interconnect lines that are formed in subsequent steps

SiO2-isolate adjacent devices

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 12

 Oxidation-2
• Silicon dioxide is “grown” by placing the exposed silicon in an
oxidizing atmosphere such as oxygen at a temperature around
1000⁰C.

• Since the oxide thickness, tox, determines both the current handling
and reliability of the transistors, it must be controlled to within a
few percent.

• The “cleanness” of the silicon surface under the oxide affects the
mobility of the charge carriers and thus the current drive,
transconductance, and noise of the transistors.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 13

 Ion Implantation
• In many steps of fabrication, dopants must be selectively introduced
into the wafer.
• The most common method of introducing dopants is “ion
implantation,” whereby the doping atoms are accelerated as a high-
energy focused beam, hitting the surface of the wafer and
penetrating the exposed areas

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 14

 Channel Stop Implantation

NMOS
Avoid turn-on

• Another important application of implantation is to create

“channel-stop” regions between transistors.
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 15
 Channeling

• An interesting phenomenon in ion implantation is “channeling.” As shown

in Figure, if the implant beam is aligned with the crystal axis, the ions
penetrate the wafer to a great depth.

• For this reason, the implant (or the wafer) is tilted by 7–9⁰, avoiding such
an alignment and ensuring a predictable profile.
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 16
 Deposition and Etching
• As suggested by the structures in the layers, device fabrication
requires the deposition of various materials.
1. Examples include polysilicon, dielectric materials separating
interconnect layers, and metal layers serving as interconnects.

• A common method of forming polysilicon on thick dielectric layers is

“chemical vapor deposition” (CVD), whereby wafers are placed in a
furnace filled with a gas that creates the desired material through a
chemical reaction.

• The etching of the materials is also a crucial step. Structures with

very small dimensions must be etched with high precision.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 17

 CMOS Fabrication Sequence-1

(a) The fabrication begins with a p-type silicon wafer approximately 1

mm thick. Following cleaning and polishing steps, a thin layer of silicon
dioxide is grown as a protective coating on top of the wafer.

(b) Next, to create n-wells, a photolithography sequence consisting of

photoresist deposition, exposure to UV light using the n-well mask, and
selective etching is carried out and n-wells are implanted.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 18

 CMOS Fabrication Sequence-2

(c) The remaining photoresist and oxide layers are then removed in this
step.

(d) At this point in the sequence, a stack consisting of a silicon oxide

layer, a silicon nitride (Si3N4), and a positive photoresist layer is created.
Subsequently, the channel-stop implant is performed, the photoresist is
removed, and a thick oxide layer is grown in the exposed silicon areas,
producing the field oxide.
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 19
 CMOS Fabrication Sequence-3

(e) The protective nitride and oxide layers are then removed thereby
exposing all areas where transistors are to be formed.

(f) The next step involves the growth of the gate oxide, a critical
operation requiring slow, low-pressure CVD

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 20

 CMOS Fabrication Sequence-4

(g) With the gate oxide in place, the polysilicon layer is deposited and
the “poly mask” lithography is carried out, resulting in the structure
shown in figure(g).
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 21
 CMOS Fabrication Sequence-5
(h) and (i) In the next step, the source/drain junctions of the
transistors and the substrate and n-well ties are formed by ion
implantation.
This step requires a “source/drain mask” and two lithography
sequences.
• The first sequence incorporates a negative photoresist,
exposing the areas to receive an n+ implant (the S/D junctions
of NMOS transistors and the n-well ties).

• In the second sequence [Figure(i)], the same mask and a

positive photoresist are used, exposing the areas to receive a
p+ implant (the S/D junctions of PMOS transistors and the
substrate ties)
• CMOS transistor is done !!!
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 22
 Back-end Processing-1
• With the basic transistors fabricated, the wafers must next
undergo “back-end” processing, a sequence primarily
providing various electrical connections on the chip through
contacts and wires.

• The first step in this sequence is “silicidation”.

• Since the sheet resistance of doped polysilicon and S/D

regions is typically several tens of ohms per square, it is
desirable to reduce their resistance by about an order of
magnitude.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 23

 Back-end Processing-2

• Silicidation: covering the polysilicon layer and active areas (S/D

regions and substrate and n-well ties) with a thin layer of a highly
conductive material, e.g., titanium silicide or tungsten.
1. Adding oxide spacer to avoid short between polysilicon and
active regions.
2. Adding silicide to reduce resistance.
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 24
 Back-End Processing-3
Thick layer oxide contact
• Produce contact
window on top of the
wafer.
• Produce via between
layers.

via

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 25

 Interconnects-1
• The performance of today’s complex integrated circuits heavily depends
on the quality of the available interconnects, requiring more metal layers
in new generations of the technology.

• Two properties of interconnects, namely, series resistance and parallel

capacitance, impact the performance, often calling for iteration between
layout and circuit design.

• The series resistance becomes especially problematic in supply and

ground lines, creating dc and transient voltage drops. In particular, for
ESD protection, large series resistance should be avoided.

• Also, for long signal lines, the distributed resistance and capacitance of
the wire may result in a significant delay.
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 26
 Interconnects-2
• Sheet resistance denotes the resistivity of the layer.
ρ ρ
• The total resistance of a rectangular bar is R= L/(Wt), where is
resistivity of the material, and L, W and t denote the length, width
and thickness of the bar.
ρ
• R = /t is used to calculate the resistance as these two
parameters are set by the fabrication material and processing
steps.
• Total resistance of a rectangular bar now becomes L/W* R, where
L and W are dependent of layout and design rules.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 27

 Interconnects-3
A single layer
on top of the
substrate

Parallel-plate cap

• The problem of interconnect capacitance is much more complicated. A

single wire on top of a substrate (as in the figure), identifying a
“parallel-plate” capacitance and a “fringe” capacitance.

• For narrow lines, the two are comparable.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 28

 Interconnects-4
• A simple empirical relationship for calculating the total wire
capacitance per unit length on top of a conducting substrate is:

Where W, h and t denote the dimensions

• For typical dimensions, this equation predicts the capacitance
with a few percent of error.
• While upper levels of metal in a process exhibit less
capacitance per unit width and length, their minimum allowable
width is usually greater than that of the lower layers.
• Thus, the minimum capacitance for a given length may be only
slightly smaller for the top-most layer(s).

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 29

 Interconnects-5

• Table depicts typical values of minimum widths and parallel-plate and

fringe capacitances (to the substrate) in a four-metal 0.25-𝞵m process

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 30

 Interconnects-6
• Very important factor “Electromigration (EM)”:
• At high current densities, the atoms in a wire tend to “migrate”,
leaving a void that eventually (after some years of operation) grows
to a discontinuity.
• Due to combined effects of current and temperature.
• Should consider Idc and Irms in certain circumstances.
• For this reason, long-term reliability considerations restrict the
maximum current density of interconnects.

• As a rule of thumb, a current-density of 2 mA per micron of width is

acceptable, but the actual value varies according to the thickness of the
metal.
2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 31
 Interconnects-7
EM failure example:

Copper connection

Source: Wiki

EM failure can be detected by EDA tools during the post-layout simulation.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 32
 Most of slides and figures are from Dr. B. Razavi’s book. We
thank to be allowed to share these resources.

2023-10-02 Yushi Zhou yzhou30@lakeheadu.ca 33