Section 1

By: Mohamed El Eraky

Integrated Circuits Lab.
ECE Department
Ain Shams University
 Content
• Different technologies
• CMOS fabrication steps
• Sheet 1
-Q5
-Q6
-Q7
• Sheet 2
– Q3
3/21/2024 CMOS Fabrication steps 2
 Triple Well CMOS

https://www.researchgate.net/figure/Cross-section-view-of-CMOS-gates-a-without-triple-well-and-b-with-triple-
3/21/2024 well_fig2_281371533 3
 Strained Si (Si –Ge)

3/21/2024 https://www.realworldtech.com/iedm-2003-day-2/4/ 4
 Silicon on insulator (SOI)

3/21/2024 Dr.Hani Fikry (VLSI Course ) ECE 482 (SOI Slides) 5

 Trigate

3/21/2024 Dr.Hani Fikry (VLSI Course ) ECE 482 (FinFet Slides) 6

 FinFet

3/21/2024 Dr.Hani Fikry (VLSI Course ) ECE 482 (FinFet Slides) 7

 IC Die (building)

3/21/2024 CMOS Fabrication steps 8

 IC Die

3/21/2024 CMOS Fabrication steps 9

 CMOS Fabrication Step: 1
Form N-Well regions NWELL mask
• Grow oxide
• Deposit photoresist

oxide photoresist

p-type substrate

Cross section view

NWELL mask

Layout view

3/21/2024 CMOS Fabrication steps 10

 CMOS Fabrication Step: 1
Form N-Well regions NWELL mask
• Grow oxide
• Deposit photoresist
• Pattern photoresist photoresist
oxide
– NWELL Mask
– expose only n-well p-type substrate
areas
Cross section view

NWELL mask

Layout view

3/21/2024 CMOS Fabrication steps 11

 CMOS Fabrication Step: 1
Form N-Well regions
• Grow oxide
• Deposit photoresist
• Pattern photoresist
oxide
– NWELL Mask
– expose only n-well p-type substrate
areas
• Etch oxide Cross section view
• Remove photresist

Layout view

3/21/2024 CMOS Fabrication steps 12

 CMOS Fabrication Step: 1
Form N-Well regions
• Grow oxide
• Deposit photoresist
• Pattern photoresist n-well
– NWELL Mask
– expose only n-well p-type substrate
areas
• Etch oxide Cross section view
• Remove photoresist
• Diffuse n-type dopants
through oxide mask
layer

Layout view

3/21/2024 CMOS Fabrication steps 13

 CMOS Fabrication Step: 2
Form Active Regions ACTIVE mask
• Deposit SiN over wafer
• Deposit photoresist over
SiN layer n-well
SiN photoresist

p-type substrate

ACTIVE mask

3/21/2024 CMOS Fabrication steps 14

 CMOS Fabrication Step: 2
Form Active Regions ACTIVE mask
• Deposit SiN over wafer
• Deposit photoresist over
SiN layer n-well
SiN photoresist
• Pattern photoresist
– *ACTIVE MASK p-type substrate

ACTIVE mask

3/21/2024 CMOS Fabrication steps 15

 CMOS Fabrication Step: 2
Form Active Regions
• Deposit SiN over wafer
• Deposit photoresist over
SiN layer n-well
SiN photoresist
• Pattern photoresist
– *ACTIVE MASK p-type substrate
• Etch SiN in exposed
areas
– leaves SiN mask
which blocks oxide
growth

ACTIVE mask

3/21/2024 CMOS Fabrication steps 16

 CMOS Fabrication Step: 2
Form Active Regions
• Deposit SiN over wafer
• Deposit photoresist over
SiN layer n-well
• Pattern photoresist FOX
– *ACTIVE MASK p-type substrate
• Etch SiN in exposed
areas
– leaves SiN mask
which blocks oxide
growth
• Remove photoresist
• Grow Field Oxide (FOX)
– thermal oxidation ACTIVE mask

3/21/2024 CMOS Fabrication steps 17

 CMOS Fabrication Step: 2
Form Active Regions
• Deposit SiN over wafer
• Deposit photoresist over
SiN layer n-well
• Pattern photoresist FOX
– *ACTIVE MASK p-type substrate
• Etch SiN in exposed
areas
– leaves SiN mask
which blocks oxide
growth
• Remove photoresist
• Grow Field Oxide (FOX)
– thermal oxidation ACTIVE mask
• Remove SiN

3/21/2024 CMOS Fabrication steps 18

 CMOS Fabrication Step: 2

n-well

FOX
p-type substrate

ACTIVE mask

3/21/2024 CMOS Fabrication steps 19

 CMOS Fabrication Step: 3
Form Gate (Poly layer)
• Grow thin Gate Oxide
– over entire wafer
– negligible effect on
FOX regions gate oxide

3/21/2024 CMOS Fabrication steps 20

 CMOS Fabrication Step: 3
Form Gate (Poly layer) POLY mask

• Grow thin Gate Oxide

– over entire wafer
– negligible effect on polysilicon
FOX regions gate oxide

• Deposit Polysilicon
• Deposit Photoresist

POLY mask

3/21/2024 CMOS Fabrication steps 21

 CMOS Fabrication Step: 3
Form Gate (Poly layer) POLY mask

• Grow thin Gate Oxide

– over entire wafer
– negligible effect on
FOX regions gate oxide

• Deposit Polysilicon
• Deposit Photoresist
• Pattern Photoresist
– *POLY MASK
• Etch Poly in exposed
areas
• Etch/remove Oxide
– gate protected by
poly
POLY mask

3/21/2024 CMOS Fabrication steps 22

 CMOS Fabrication Step: 3
Form Gate (Poly layer)
• Grow thin Gate Oxide
– over entire wafer
– negligible effect on
FOX regions gate oxide

• Deposit Polysilicon
• Deposit Photoresist
• Pattern Photoresist
– *POLY MASK
• Etch Poly in exposed
areas
• Etch/remove Oxide
– gate protected by
poly

3/21/2024 CMOS Fabrication steps 23

 CMOS Fabrication Step: 4
Form pmos S/D PSELECT mask

• Cover with photoresist

PSELECT mask

3/21/2024 CMOS Fabrication steps 24

 CMOS Fabrication Step: 4
Form pmos S/D PSELECT mask

• Cover with photoresist

• Pattern photoresist
– *PSELECT MASK

POLY mask

3/21/2024 CMOS Fabrication steps 25

 CMOS Fabrication Step: 4
Form pmos S/D
• Cover with photoresist
• Pattern photoresist
– *PSELECT MASK
• Implant p-type dopants
p+ dopant p+ dopant
• Remove photoresist

POLY mask

3/21/2024 CMOS Fabrication steps 26

 CMOS Fabrication Step: 5
Form nmos S/D NSELECT mask

• Cover with photoresist

p+ p+ p+

POLY mask

3/21/2024 CMOS Fabrication steps 27

 CMOS Fabrication Step: 5
Form nmos S/D NSELECT mask

• Cover with photoresist

• Pattern photoresist p+ p+ p+
– *NSELECT MASK
n

POLY mask

3/21/2024 CMOS Fabrication steps 28

 CMOS Fabrication Step: 5
Form nmos S/D
• Cover with photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *NSELECT MASK
n
• Implant n-type dopants
n+ dopant n+ dopant
• Remove photoresist

POLY mask

3/21/2024 CMOS Fabrication steps 29

 CMOS Fabrication Step: 6
CONTACT mask
Form Contacts
• Deposit oxide
• Deposit photoresist n+
p+ p+
n+ n+
p+

CONTACT mask CONTACT mask

3/21/2024 CMOS Fabrication steps 30

 CMOS Fabrication Step: 6
CONTACT mask
Form Contacts
• Deposit oxide
• Deposit photoresist n+
p+ p+
n+ n+
p+
• Pattern photoresist n
– *CONTACT Mask
– One mask for both
active and poly
contact shown

CONTACT mask CONTACT mask

3/21/2024 CMOS Fabrication steps 31

 CMOS Fabrication Step: 6
Form Contacts
• Deposit oxide
• Deposit photoresist n+
p+ p+
n+ n+
p+
• Pattern photoresist n
– *CONTACT Mask
– One mask for both
active and poly
contact shown
• Etch oxide

3/21/2024 CMOS Fabrication steps 32

 CMOS Fabrication Step: 6
Form Contacts
• Deposit oxide
• Deposit photoresist n+
p+ p+
n+ n+
p+
• Pattern photoresist n
– *CONTACT Mask
– One mask for both
active and poly
contact shown
• Etch oxide
• Remove photoresist
• Deposit metal1
– immediately after
opening contacts so
no native oxide
grows in contacts
• Planerize
– make top level

3/21/2024 CMOS Fabrication steps 33

 CMOS Fabrication Step: 7
METAL1 mask
Form Metal 1 Traces
• Deposit photoresist
n+ n+ n+
p+ p+ p+

METAL1 mask

3/21/2024 CMOS Fabrication steps 34

 CMOS Fabrication Step: 7
METAL1 mask
Form Metal 1 Traces
• Deposit photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *METAL1 Mask
n

METAL1 mask

3/21/2024 CMOS Fabrication steps 35

 CMOS Fabrication Step: 7
Form Metal 1 Traces
• Deposit photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *METAL1 Mask
n
• Etch metal

metal over poly outside of cross section

3/21/2024 CMOS Fabrication steps 36

 CMOS Fabrication Step: 7
Form Metal 1 Traces
• Deposit photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *METAL1 Mask
n
• Etch metal
• Remove photoresist

3/21/2024 CMOS Fabrication steps 37

 CMOS Fabrication Step: 8
VIA mask
Form Vias to Metal1
• Deposit oxide
• Planerize oxide n+
p+ p+
n+ n+
p+
• Deposit photoresist n

VIA mask

3/21/2024 CMOS Fabrication steps 38

 CMOS Fabrication Step: 8
VIA mask
Form Vias to Metal1
• Deposit oxide
• Planerize n+
p+ p+
n+ n+
p+
• Deposit photoresist n
• Pattern photoresist
– *VIA Mask

VIA mask

3/21/2024 CMOS Fabrication steps 39

 CMOS Fabrication Step: 8
Form Vias to Metal1
• Deposit oxide
• Planerize n+
p+ p+
n+ n+
p+
• Deposit photoresist n
• Pattern photoresist
– *VIA Mask
• Etch oxide
• Remove photoresist

3/21/2024 CMOS Fabrication steps 40

 CMOS Fabrication Step: 8
Form Vias to Metal1
• Deposit oxide
• Planerize n+
p+ p+
n+ n+
p+
• Deposit photoresist n
• Pattern photoresist
– *VIA Mask
• Etch oxide
• Remove photoresist
• Deposit Metal2

3/21/2024 CMOS Fabrication steps 41

 CMOS Fabrication Step: 9
METAL2 mask
Form Metal2 Traces
• Deposit photoresist
n+ n+ n+
p+ p+ p+

METAL2 mask

3/21/2024 CMOS Fabrication steps 42

 CMOS Fabrication Step: 9
METAL2 mask
Form Metal2 Traces
• Deposit photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *METAL2 Mask
n

METAL2 mask

3/21/2024 CMOS Fabrication steps 43

 CMOS Fabrication Step: 9
Form Metal2 Traces
• Deposit photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *METAL2 Mask
n
• Etch metal

3/21/2024 CMOS Fabrication steps 44

 CMOS Fabrication Step: 9
Form Metal2 Traces
• Deposit photoresist
• Pattern photoresist n+
p+ p+
n+ n+
p+
– *METAL2 Mask
n
• Etch metal
• Remove photoresist

3/21/2024 CMOS Fabrication steps 45

 CMOS Fabrication Step: 10+
Form Additional Traces
• Deposit oxide
• Deposit photoresist n+
p+ p+
n+ n+
p+
• Pattern photoresist n
• Etch oxide
• Deposit metal p-type substrate
• Deposit photresist
• Pattern photoresist
• Etch metal
• Repeat for each
additional metal

3/21/2024 CMOS Fabrication steps 46

 Q5 ) Inverter Layout

3/21/2024 47
 Rules
• Poly + active region → Transistor
– Poly → gate
– Active Region (diffusion) → source, drain
• Any Transistor in NWELL → Pmos
• active Region + n-select → n+
• active Region + p-select → p+

3/21/2024 CMOS Fabrication steps 48

 CMOS Process Layers
Layer Representation
Well (n)
Active area
Select (p+)
Select (n+)
Polysilicon
Metal1
via

3/21/2024 CMOS Fabrication steps 49

 Layer Representation

Q6: 1- Well (n)

Active
area

Select
(p+)

Select
(n+)

Polysilico
n
NWELL Metal1

via
p+ p+
n+

in

gnd out vcc

p+ n+ n+
P substrate

3/21/2024 CMOS Fabrication steps 50

 Layer Representation

Q6: 1- Well (n)

Active
area

Select
(p+)

Select
(n+)

Polysilico
n
NWELL Metal1

via

in

gnd out vcc

P substrate

3/21/2024 CMOS Fabrication steps 51

 Layer Representation

Q6: 3- Well (n)

Active
area

Select
(p+)

Select
(n+)

Polysilico
n

Metal1

via

3/21/2024 CMOS Fabrication steps 52

 Q6: 4-

X
Z
Y

3/21/2024 CMOS Fabrication steps 53

 Q7: State and explain briefly the two main types of constraints on layout imposed
by the fabrication process
• Resolution constraints • Overlap constraint
– Smallest width and spacing to − Smallest extension and spacing to
margin for variations margin for alignment mismatch
– Minimum values are imposed by the
processing capabilities of the target
technology.

3/21/2024 CMOS Fabrication steps 54

 Scaling

𝑡𝑜𝑥
L

3/21/2024 CMOS Fabrication steps 55

 Sheet 2

3/21/2024 CMOS Fabrication steps 56

 Sheet 2

3/21/2024 CMOS Fabrication steps 57

 References
• “Simplified Example of a LOCOS Fabrication Process” by Prof. A. Mason.

• “M1: Introduction to ICs Lecture 1” by Prof. DiaaEldin Khalil.

3/21/2024 CMOS Fabrication steps 58