VLSI Design & Testing

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 VLSI DESIGN AND TESTING
BY VTU Academy (on YouTube)

Module-3 : CMOS Process Technology

3.1 Silicon Semiconductor Technology: An Overview

• Silicon as a Semiconductor:

o Pure (intrinsic) silicon has electrical conductivity between that of a conductor and an insulator.

o Doping introduces impurities to control conductivity:

▪ Donors (n-type): Add free electrons.

▪ Acceptors (p-type): Create holes by accepting electrons.

o The junction between n-type and p-type is essential for creating semiconductor devices.

3.1.1 Wafer Processing

• Starting Material:

o Wafers are sliced from single-crystal silicon ingots

using the Czochralski method.

o Wafer sizes: 75–150 mm diameter, <1 mm thick.

• Czochralski Method (Crystal Growth):

o A seed crystal is dipped into molten polycrystalline

silicon.

o The seed is slowly pulled and rotated to grow a

single-crystal ingot.

o Controlled impurity doping is done during this

stage.

• Wafer Slicing & Polishing:

o Diamond blades are used to slice the ingot into thin

wafers.

o At least one side is polished to a mirror-like finish.

3.1.2 Oxidation
• Importance of SiO₂ (Silicon Dioxide):

o SiO₂ is widely used in IC fabrication as an insulator and barrier.

• Types of Oxidation:
 o Wet Oxidation: Uses water vapor (H₂O) at 900–1000°C. Fast process.

o Dry Oxidation: Uses pure oxygen (O₂) at ~1200°C. Slower but results in better-quality oxide.

• Oxide Growth:

o SiO₂ grows both into and above the silicon surface.

o Since SiO₂ takes up more space than the original silicon, the oxide layer bulges out.

3.1.3 Selective Diffusion

• Why it’s needed:

o To form regions with specific electrical

properties (n-type or p-type) in exact
locations.

• Role of SiO₂:

o Acts as a mask or barrier against

unwanted doping.

• Process Steps:

1. Grow SiO₂ layer over the wafer.

2. Apply photoresist (PR)—a UV-sensitive

material.

3. Use UV light through a mask to define pattern

areas.

4. Etch SiO₂ in exposed areas.

5. Introduce dopants in exposed silicon (via

diffusion or ion implantation).

• Advanced Lithography - Electron Beam Lithography (EBL):

o Enables high-precision patterns (~0.5 µm or smaller).

o Direct digital-to-pattern process (no physical mask needed).

o Not widely used in mass production due to high cost and slow speed.
CMOS Process Technology – Fabrication Steps

Step 1: Substrate Preparation

• Material Used: High-purity single crystal silicon.

• Doping: Phosphorus (P) impurities are added during crystal growth for desired electrical properties.

• Wafer Specifications:

o Diameter: 75 mm to 150 mm

o Thickness: ~0.4 mm

o Doping Concentration: Between 10¹⁵/cm³ and 10¹⁶/cm³

Step 2: Thick Oxide Growth

• A thick layer of SiO₂ (~1 µm) is grown over the entire wafer surface.

• Purpose: Acts as a protective layer for the underlying silicon during further processing.

Step 3: Photoresist Application

• A photosensitive material (photoresist) is uniformly spun onto the wafer.

• Purpose: Helps define the areas to be modified in the next steps.

Step 4: UV Exposure Through a Mask

• The wafer is exposed to ultraviolet (UV) light through a mask.

• The mask defines the pattern (transistor channels, diffusion areas, etc.).

• Only the exposed regions of the photoresist are altered (polymerized).

Step 5: Etching the Oxide Layer

• The wafer undergoes etching to remove the exposed photoresist and SiO₂ underneath.

• This process opens windows in the oxide, exposing selected silicon regions

Step 6: Thin Oxide Growth

• A thin SiO₂ layer is grown in the exposed silicon regions.

• Purpose: This oxide layer will act as the gate oxide in the MOSFET structure

Step 7: Polysilicon Deposition (Gate Patterning)

• Polysilicon (heavily doped for conductivity) is deposited over the entire wafer using Chemical Vapor
Deposition (CVD).

• Typical thickness: 1–2 µm

• This polysilicon layer is later patterned to form MOSFET gates.

Step 8: N-Type Diffusion

• The wafer is exposed to n-type dopant gases (e.g., phosphorus or arsenic) at high temperatures.

• Purpose: Forms n-type source and drain regions.

• Depth: ~1 µm

• This process is self-aligning because the polysilicon gate and surrounding oxides act as masks

Step 9: Contact Cuts

• A new thick oxide layer is grown again.

• This oxide is selectively etched (with the help of photoresist) to open contact holes.

• These holes expose polysilicon gates and source/drain regions for electrical connection.\

Step 10: Metallization

• A layer of metal (usually aluminum) is deposited over the wafer (~1 µm thick).

• This metal is patterned and etched to form the required interconnections between components.
3.2 CMOS Technologies
CMOS (Complementary Metal Oxide Semiconductor) technology is widely used in VLSI (Very Large Scale
Integration) systems due to its low power consumption and high performance. CMOS circuits consume power
only during switching, making them ideal for battery-powered devices.

Advantages of CMOS:

• Very low static power consumption

• Low power-delay product

• Ideal for high-density logic circuits

CMOS is preferred over earlier technologies like nMOS
and pMOS due to these benefits.

3.2.1 The p-well CMOS Process

In the p-well process, we use an n-type substrate, and
we create a p-type well (called p-well) within it. Here's
where n-channel transistors (NMOS) are built, while p-
channel transistors (PMOS) are built directly in the n-
type substrate.

Basic Steps in the p-well CMOS Process:

1. Start with an n-type substrate:

o This is the base silicon wafer.

o It is lightly doped with donor impurities.

2. Create the p-well:

o Use a mask to define where the p-well

should go.

o Perform deep diffusion or ion

implantation of acceptor impurities (like
boron) to form the p-well.

3. Field Oxide Formation:

o Grow a thick silicon dioxide (SiO₂) layer

called Field Oxide (FOX) in unwanted
areas to isolate devices.

4. Thin Oxide Growth (Thinox Masking):

o Etch windows in FOX to expose active

regions.

o Grow a thin oxide layer (~10–50 nm) in

these regions for the gate oxide.

o These areas are called active regions or

islands.

5. Polysilicon Gate Formation:

o Deposit polysilicon over the wafer.

o Pattern and etch it to form gate electrodes.

o The gates are “self-aligned” with source

and drain due to the use of poly during
implantation.

6. Doping of Source and Drain:

o Use p⁺ mask to implant p-type dopants into

PMOS source/drain areas.
 o Use n⁺ (complement of p⁺) to implant n-type dopants into NMOS source/drain areas.

o The gate poly itself is usually n⁺ doped to reduce resistance.

7. Contact Cuts:

o Open holes in the oxide layer to allow contact between metal and underlying regions (poly,
source, drain).

8. Metallization:

o Deposit a layer of aluminum over the wafer.

o Etch the aluminum to form interconnect lines.

9. Passivation and Bond Pad Openings:

o A final protective layer is applied over the wafer.

o Openings are made for wire bonding.

Understanding Layouts and Cross-
Sections
• NMOS is built inside the p-well, and
PMOS is built in the n-type
substrate.

• A cross-section diagram shows the

physical layers and junctions.
layout diagram shows the top
view, useful for chip design.
Limitations of p-well Process

• NMOS performance in p-well is slightly inferior due to:

o High p-well capacitance

o Higher body effect

• Requires careful substrate grounding to prevent latch-up

3.2.3 The Twin-Tub Process – Simplified Notes

Definition

• Twin-tub CMOS technology allows separate optimization of n-type and p-type transistors.

• It enables independent control over:

o Threshold voltage (Vth)

o Body effect

o Gain of both nMOS and pMOS devices.

Starting Material
 • Substrate: Usually an n-type or p-type silicon wafer.

• On top of it, a lightly doped epitaxial (epi) layer is grown.

Epitaxy means "arranged upon" – a process to grow a high-purity silicon layer with controlled thickness
and uniform doping.

• Purpose of the epi layer:

o Prevents latch-up

o Provides better control over electrical properties

Process Flow Overview

The process is similar to the p-well process, with one key difference:

Both p-well and n-well (called “tubs”) are formed.

Key Steps in Twin-Tub Process

1. Tub Formation

o Both n-well and p-well regions are formed using selective doping.

2. Thin Oxide Etching

o Removes a thin oxide layer where further steps (like gate oxide formation) will happen.

3. Source and Drain Implantation

o Dopants (like boron or phosphorus) are implanted to form the source and drain terminals.

4. Contact Cut Definition

o Openings are made in the oxide layer for metal contacts.

5. Metallization

o Metal (usually aluminum) is deposited and patterned to connect all components.

Advantages of Twin-Tub Process

• Better performance nMOS and pMOS transistors:

o nMOS: Lower capacitance and less body effect.

o pMOS: Improved performance via separate optimization.

• Includes threshold voltage adjustment using additional doping steps.

o These use thinox and n-plus masks.

 3.2.4 Silicon on Insulator (SOI)

What is SOI?

SOI (Silicon-On-Insulator) is an advanced CMOS fabrication technology where the silicon transistors
are built on top of an insulating layer, instead of a regular bulk silicon substrate.

Advantages of SOI over Traditional CMOS

• Higher transistor density (no wells needed)

• No latch-up problems (due to isolation)

• Lower parasitic capacitance → faster circuits

• No field inversion

• No body effect

• High radiation tolerance → ideal for aerospace or space applications

Fabrication Process (Step-by-Step)

The entire SOI CMOS process is illustrated in Fig. 3.15 (a to i) on page 90.

1. Start with Insulator Substrate

• A very thin layer (7–8 µm) of lightly doped

n-type silicon is grown on top of an
insulator.

• Common insulator: sapphire

(see Fig. 3.15a)

2. Etching Silicon Islands

• An anisotropic etch removes most of the

silicon except where transistors will be
built.

• Etching must be vertical (anisotropic)

because silicon is thicker than the space
between "islands".
(see Figs. 3.15b and 3.15c)

3. Forming p-Islands (nMOS regions)

• Photoresist masks the n-regions.

• A p-type dopant (like boron) is implanted

into exposed islands to form p-islands,
which will become n-channel MOSFETs.
(see Fig. 3.15d)

4. Forming n-Islands (pMOS regions)

• Now the p-islands are masked.

• An n-type dopant (like phosphorus) is

implanted to form n-islands, which will
become p-channel MOSFETs.
(see Fig. 3.15e)

5. Gate Oxide Growth

• A thin gate oxide (about 500–600 Å) is grown over all silicon areas by thermal oxidation.
6. Polysilicon Deposition

• A polysilicon layer is deposited over the

oxide.

• Usually doped with phosphorus to lower its

resistance.
(see Fig. 3.15f)

7. Polysilicon Patterning

• The polysilicon is patterned using

photolithography and etched to form gate
electrodes.
(see Fig. 3.15g)

8. nMOS Source/Drain Implantation

• Mask the n-islands.

• Phosphorus is implanted to form n+ source

and drain in p-islands (nMOS).

o The photoresist and polysilicon

protect the gate and n-islands.
(see Fig. 3.15h)

9. pMOS Source/Drain Implantation

• Mask the p-islands.

• Boron is implanted to form p+ source and

drain in n-islands (pMOS).
(see Fig. 3.15i)

10. Interconnect and Final Steps

• Deposit phosphosilicate glass (PSG) or SiO₂ for insulation.

• Etch contact holes, deposit and pattern aluminum metal to form interconnects.

• Add a final passivation layer and open bonding pads.

(see Fig. 3.15i)

Etching Techniques Comparison (Fig. 3.16)

 Fig. 3.16 shows three types of etching:

Type of Etch Description Impact

Fully Anisotropic Straight vertical etching

Sharp, precise features
Etch with no undercut

Etches uniformly in all

Isotropic Etch Causes undercutting, rounded edges
directions

Controlled tapering of Smoother step heights for metal/polysilicon

Preferential Etch
island edges runners to enter and exit islands

Advantages of SOI Technology

1. High Packing Density: No wells → more compact design

2. Fast Circuits: Low junction capacitance due to sidewall-only diffusion

3. No Field-Inversion or Latch-Up: Fully isolated devices

4. No Body Effect: No bulk substrate = no threshold voltage shifts

 5. Radiation Tolerant: Excellent for harsh environments

Disadvantages of SOI Technology

• More expensive: Sapphire or spinel substrates are costly

• Lower device gains: I/O structures need to be larger

• Difficult input protection: No substrate diode means fewer natural ESD protections

• Less mature: Processing technology is less developed compared to bulk silicon

3.2.5 CMOS Process Enhancements

CMOS processes can be enhanced in various ways to:

• Increase routing flexibility

• Provide high-quality capacitors for analog/memory applications

• Include resistors with specific characteristics

Key Enhancements:

• Double or triple level metal

• Double or triple level polysilicon

• Combinations of the above

Polysilicon Resistance Reduction Techniques
To reduce polysilicon resistance without adding extra mask layers, refractory metals are used with polysilicon.
These techniques are illustrated in Fig. 3.17 and include:

(a) Silicide Gate Approach (Fig. 3.17a)

• A silicide (e.g., tantalum silicide) replaces

polysilicon as the gate material.

• Advantages:

o Very low resistance (~1–2 Ω/□)

o Mechanically strong, stable in processing

o Easily integrated into existing process

flows

(b) Polycide Approach (Fig. 3.17b)

• A silicide layer is deposited on top of polysilicon.

• Called polycide, widely used in standard CMOS.

(c) Metal/Silicide Sandwich (Heart of Moly) – Fig. 3.17c

• A molybdenum gate with a silicide cap forms a

metal-silicide sandwich.

• Useful for faster switching and reduced delay.

(d) Salicide Process (Fig. 3.17d)

• Extends silicide to source and drain regions as

well.

• Reduces interconnect resistance significantly.

Second Metal Layer (Interconnect)

• Used to reduce interconnect
resistance further.

• Typically has a coarser pitch

due to surface topography.

• Contact between metal 1 and

metal 2 is made using vias (Fig.
3.18).

Important Considerations:

• Vias require:

o Sufficient overlap with metal layers

o Thicker metal-2 to handle current

 • In many processes, metal 1 must connect to underlying diffusion/poly—metal 2 alone cannot (except in
advanced processes).

Contact Geometries (Fig. 3.19)

• Metal borders around vias may be:

o Required on both metal levels

o Required only on metal 2

o Not required at all (aggressive scaling)

• Fig. 3.19b: Shows metal-2-only border case.

• Fig. 3.19c: Shows stacked via on contact, used in

advanced nodes.

Double Poly Process

• Involves two polysilicon layers separated by oxide.

• Used to create capacitors or vertical structures.

• Isolation oxide is grown between poly layers.

Recent Innovations:
(a) 3D CMOS Structures (Fig. 3.20a & 3.20b)

• Use vertical stacking in silicon to reduce area and

increase performance.

• Fig. 3.20a: Cross-section of a 3D SOI CMOS

structure.

• Fig. 3.20b: Layout example of a CMOS inverter in

3D.
(b) Trench Isolation (Fig. 3.21a)

• Deep oxide-filled trenches isolate n- and p-

transistors.

• Prevents latch-up and reduces spacing

requirements.

(c) Advanced Twin-Tub Process (Fig. 3.21b)

• Developed by Tektronix.

• Features:

o Silicide gates

o Trench isolation

o Second metal layer

Summary of Enhancements:

Enhancement Purpose

Silicide/Polycide Reduce gate resistance

Salicide Reduce source/drain resistance

Double/Triple Metal Better routing

Double/Triple Poly Custom resistors, capacitors

Trench Isolation Prevent latch-up

3D CMOS Save area, improve speed

3.3 Layout Design Rules

What Are Layout (Design) Rules?

• Layout rules (also called design rules) are guidelines used to prepare photomasks for IC fabrication.

• They serve as a bridge between the circuit designer and the process engineer to ensure
manufacturable and functional circuits.
Purpose of Design Rules

• To maximize yield (number of working chips per wafer).

• To minimize layout area (compact design).

• To maintain circuit reliability.

Design rules aim to find a balance between performance and manufacturability:

• Conservative rules → Better yield, lower risk of failure.

• Aggressive rules → Smaller size, better performance, but higher risk of manufacturing defects.

What Do Design Rules Specify?

They impose geometric constraints on layout features, such as:

• Minimum widths of lines, diffusion, poly, etc.

• Minimum spacing between different structures.

• Overlap and enclosure rules (e.g., how much metal must cover a contact).

• Layer-to-layer alignment tolerance (registration rules).

Important: Violating rules doesn’t guarantee failure, but frequent violations increase the chances of failure
significantly.

Key Issues Addressed by Design Rules

1. Reproducibility of Features
→ Ensures layout patterns can be fabricated accurately using lithography.

2. Layer Interactions
→ Ensures correct electrical and physical interaction between different layers (e.g., diffusion, poly,
metal).

Problems Without Rules

• Too thin lines → May break/disconnect.

• Too close lines → May short-circuit.

• Misalignment of layers → Functional errors or open/shorts.

Types of Design Rule Systems

1. Micron-Based Rules

• Uses absolute dimensions, e.g., 4 µm poly width.

• Commonly used in industry.

• Each rule is listed in microns for different layers.

2. Alpha (α) and Beta (β) Rules

• Use relative units:

o α = Minimum feature size

o β = Minimum grid size

• Typically, α and β are scaled by a constant factor.

3. Lambda (λ)-Based Rules

• Popularized by Mead and Conway.

• All dimensions are defined as multiples of λ (a scalable unit).

• Good for teaching and academic prototyping.

Advantages of Lambda Rules:

• Scalable across processes.

• Simple to understand—can fit on one page.

• First-order scaling: Can be easily adapted to new technologies by changing λ.

Note: Don’t confuse β and λ here with transistor parameters β (gain) and λ (channel length modulation)
from Chapter 2.

Table 3.1 (Referenced)

• Shows how λ rules are derived from a typical micron rule set.

• Illustrates how one can move from absolute to scalable rules.

Final Notes

• Although lambda rules are useful, they may not be suitable for:
 o High-performance commercial chips

o Area-optimized designs

• This text promotes symbolic layout and tools that hide design rules from the user for ease of design
(especially useful in education).

3.3.1 Layer Representations

Why Layer Representation Matters

• Modern CMOS fabrication uses many complex layers (masks), making it hard to visualize the full
manufacturing process.

• To simplify design, we use conceptual layout levels that abstract away the complexity and focus on
what’s physically seen on the final chip.

Key Physical Features in All CMOS Layouts

Despite differences in process types (n-well, p-well, SOI), all CMOS processes generally consist of the
following:

1. Two types of substrate materials (p-type and n-type)

2. Doped regions (to form nMOS and pMOS transistors)

3. Gate electrodes (typically polysilicon)

4. Interconnections (metal layers for wiring)

5. Interlayer contacts (vias and contacts to connect layers)

Layer Abstraction in Design

• Designers don’t deal directly with all the fabrication masks.

• Instead, layout tools and symbolic representations let designers work at a high level using:

o nMOS and pMOS transistors

o Wiring and contacts

o Only key conceptual layers

The design is later translated into actual mask layers used for fabrication.

Mask Layer Naming: CIF Format

• CIF (Caltech Intermediate Form) is a format used to represent layout mask data.

• CIF 2.0 uses up to 4 alphanumeric characters to name each mask layer.

o First character = Process class

Example: 'C' → bulk CMOS

o Second character = Layer type

 • CIF naming helps group and identify masks for related processes (shown in Table 3.4 in the text).

Different CMOS Processes & Mask Variants

1. n-Well CMOS

• Most common bulk CMOS process.

• n-well is formed in a p-type substrate.

• Transistor regions are defined within the well or substrate.

2. Twin-Tub Process

• Uses both n-well and p-well, giving designers more control over transistor characteristics.

• More complex than single-well processes.

3. SOI (Silicon on Insulator)

• No wells are used.

• Simpler from a layout perspective.

• Geometry directly corresponds to conceptual features: n-regions, p-regions, gates, and interconnects.

Importance of Understanding Mask Usage

• Each fabrication line may use a different combination of masks.

• Understanding the actual mask set is critical if you're:

o Generating CIF or GDS formats

o Transferring designs to fabrication

• Example:

o A layer labeled "n-thinox" may be used to define nMOS transistors.

o A "p-thinox" layer may define pMOS devices.

Symbolic Layout: Making Design Easier

• Goal: Make design as simple and process-independent as possible.

 • Instead of dealing with layers, the designer uses symbols:

o nMOS / pMOS

o Wires

o Contacts

These symbolic elements are automatically converted to proper mask layers.

Advantages of Symbolic Layout

• Hides design rules from the designer.

• Simplifies the learning curve.

• Enables automatic layout optimization (size, speed, power).

• Bridges the simplicity of SOI with the practicality of bulk CMOS.

3.3.2 Lambda-based p-well Rules

In CMOS design, lambda-based rules provide scalable design rules that adapt to different process
technologies. These rules are expressed in terms of λ (lambda), which is a unit equal to half the minimum
feature size of a particular technology (e.g., in a 0.6 µm process, λ = 0.3 µm). These rules guide layout
designers in placing and sizing features to ensure reliable circuit fabrication.

Key Design Considerations (Based on Fig. 3.22)

1. Feature Sizes, Separations, and Overlaps

Design rules are categorized based on:

• Minimum sizes (like width of diffusion, polysilicon, etc.)

• Clearances between different regions

• Overlap requirements for proper operation and connectivity

Major Issues :
1. Well Spacing and Separation

• P-well is a deep diffusion region, so spacing rules are critical.

• Outer clearance (5λ): Prevents p-well from shorting to nearby p-diffusion in the n-substrate.

• Inner clearance (3λ): Accounts for the transition region of the field oxide, avoiding “bird’s beak”
effects (tapered oxide growth).

• Thinox restriction: Thin oxide must not cross well boundaries, to avoid shorts.

• P-well grounding: Due to its high resistance, p-well must be grounded using substrate contacts
wherever space allows.

2. Transistor Formation Rules

• Transistor is formed where polysilicon crosses thin oxide (thinox).

o This defines the gate; diffusion under thinox becomes source/drain.

• Gate Extension: Poly must extend 1.5λ–2λ beyond diffusion to avoid shorts.

• Thinox Extension: Must extend 2λ beyond gate poly for proper source/drain diffusion.

• Spacing Rules:

o Unintended transistor formation is avoided by keeping poly and thinox at least 0.5λ–1λ apart
when not forming a gate.

o Minimum poly over thinox overlap: 2λ.

Device Type Identification

• N-channel transistor: Formed in a p-well (p-substrate)

• P-channel transistor: Formed in an n-region (n-well)

• Diffusion formation:

o p+ diffusion = thinox ∩ p-mask

 o n+ diffusion = thinox ∩ (NOT p-mask)

3. Contacts

Common Contact Types:

• Metal to:

o p-diffusion (p-thinox)

o n-diffusion (n-thinox)

o Polysilicon

• Substrate contacts: For tying wells to power supplies:

o Vss contact for p-well (ground)

o VDD contact for n-well (power)

Special Contact Considerations

• Split or merged contacts are used to connect transistor sources to substrate or p-well.

• Contact size: For elongated contacts, a 4λ–6λ length rule ensures doping boundary alignment.

• Uniform contact cuts are preferred to simplify manufacturing.

4. Poly Doping

• Polysilicon is usually doped n+, even inside p-wells.

• In p-well regions, doping can reduce conductivity, increasing poly sheet resistance.

• Design Tip: Place poly wires outside p-well if high conductivity is critical.

5. Gate Edge Spacing (2λ Rule)

• 2λ separation from gate edge to p+ region is maintained.

• This allows for controlled doping transitions, useful for forming lateral diodes.

• Junction gradients and breakdown voltages vary across processes due to doping transitions.

6. Guard Rings

Guard rings collect minority carriers and help prevent latch-up:

• p+ guard rings in n-substrate → tie to Vss

• n+ guard rings in p-well → tie to VDD

• Purpose: To isolate devices and reduce noise/interference.

Example Layout
• Fig. 3.26 and Plate 4 show a 2-input NAND gate using these lambda-based rules.

• It demonstrates the practical application of the above spacing and layout guidelines.
3.3.3 Lambda-based SOI (Silicon-On-Insulator) Rules
What is SOI?
SOI technology places a layer of insulating material (like silicon dioxide) beneath the active silicon layer, which
improves performance and reduces power consumption.

Design Rule Summary for SOI:

• Key Point: In SOI CMOS design, most design rules are

simplified.

• Common rule value: 2λ is the default for almost all

spacing rules.

o This includes spacing between features like metal

lines, polysilicon, and island edges.

• Exceptions to the 2λ rule:

o n-device to n-device spacing

o Implant spacing rules

o Metal-to-metal spacing

o Contact rules

Why 2λ spacing?

• Prevents short circuits caused by:

o Thin oxide layers

o Manufacturing defects

o Incomplete coverage between poly and island

edges

3.3.4 Double Metal Design Rules

In some fabrication processes, two layers of metal are used to
route signals and power.

Why two metal layers?

• Helps manage complex interconnections

• Reduces congestion and delays in wiring

Key Design Rules:

• Wider metal traces for Metal 2:

The second metal layer (Metal 2) usually has larger width
and separation requirements than Metal 1.
 o This reduces the risk of:

▪ Broken wires

▪ Shorts between wires

o It accounts for vertical topography (the height difference between metal layers).

Design Tables:

• Table 3.7 and 3.8 provide specific width, separation, and overlap rules for Metal 1 and Metal 2 in double
metal processes.

3.3.5 Design Rules — Summary and Practical Notes

While lambda-based design rules are a good approximation, they are not enough for commercial high-
performance circuits.

Some advanced rules in real-world processes:

1. Polysilicon extensions:

o Required when metal wires exit a contact to avoid shorts or connection issues.

2. Different gate lengths for pMOS and nMOS transistors:

o Due to performance differences between p- and n-type devices.

3. Variable poly extensions based on transistor length or construction:

o Helps improve transistor behavior or meet electrical specs.

Issue with strict lambda rules:

• Worst-case values lead to inefficient layouts (large, slow, or power-hungry circuits).

Better alternative:
 • Use symbolic design or intermediate representations:

o Designers create circuits using abstract symbols or schematic-level tools.

o The system automatically generates the physical layout with process-specific rules.

This idea is explored further in Chapter 7.

Summary

Section Key Concepts

3.3.3 SOI rules are simplified; most features follow the 2λ spacing rule except for a few specific ones.

3.3.4 Double metal processes require wider spacing and widths in the second metal layer to avoid defects.

Lambda rules are not enough for high-performance designs; symbolic design methods are more
3.3.5
scalable and adaptable.