ELEC0004 Coursework 1
ELEC0004 Coursework 1
student ID number:21003456
1. A JK flip-flop receives a clock and two inputs, J and K. On the rising edge of the
clock, it updates the output, Q. If J and K are both 0, Q retains its old value. If only J
is 1, Q becomes 1. If only K is 1, Q becomes 0. If both J and K are 1, Q becomes the
opposite of its present state.
(i) Sketch the state transition diagram for the JK flip-flop. [10 marks]
(ii) Write out the state transition table for the JK flip flop. [10 marks]
Inputs Present state Next state
J K Q Q’
0 0 1 1
0 0 0 0
1 0 1 1
1 0 0 1
0 1 1 0
0 1 0 0
1 1 1 0
1 1 0 1
(iii) Construct a JK flip-flop based on a D flip-flop and some combinational logic. Your
design should be in the form of a Moore-type finite state machine. [30 marks]
st
According to the state transition table of the JK flip flop, we can use 1 canonical form
function to build the logic gate:
𝑄 ′ (𝑜𝑢𝑡𝑝𝑢𝑡) = 𝐽. 𝐾. 𝑄 + 𝐽. 𝐾. 𝑄 + 𝐽. 𝐾. 𝑄 + 𝐽. 𝐾. 𝑄
𝑄′ (𝑜𝑢𝑡𝑝𝑢𝑡) = 𝐽. 𝐾. (𝑄 + 𝑄) + 𝐽. 𝐾. 𝑄 + 𝐽. 𝐾. 𝑄
𝑄 ′ (𝑜𝑢𝑡𝑝𝑢𝑡) = 𝐽. 𝐾 + 𝐽. 𝐾. 𝑄 + 𝐽. 𝐾. 𝑄
And since we need to base on the D flip-flop in form of Moore-type finite state
machine in our design, this is what I have built:
When the CLK is 0, the value at propagates to N1, and when CLK is 1, the value at D
is copied to Q’ immediately before the clock rise from 0 to 1.
2. A toggle (T) flip-flop receives a clock and one input, T. On the rising edge of the
clock, it updates the output, Q. If T is 0, Q retains its old value. If T is 1, Q toggles to
the complement of its present state (i.e., Q becomes the opposite of its present
state).
(i) Sketch the state transition diagram for the T flip-flop. [10 marks]
(ii) Write out the state transition table for the T flip flop. [10 marks]
Input Present state Next state
T Q Q’
0 0 0
1 0 1
0 1 1
1 1 0
(iv) Construct a T flip-flop based on a D flip-flop and some combinational logic. Your
design should be in the form of a Moore-type finite state machine. [30 marks]
st
According to the state transition table of the T flip flop, we can use 1 canonical form
function to build the logic gate:
𝑄 ′ (𝑜𝑢𝑡𝑝𝑢𝑡) = 𝑇. 𝑄 + 𝑇. 𝑄
And since we need to base on the D flip-flop in form of Moore-type finite state
machine in our design, this is what I have built:
When the CLK is 0, the value at propagates to N1, and when CLK is 1, the value at D
is copied to Q’ immediately before the clock rise from 0 to 1.