LOGIC FAMILIES

 Digital logic is concerned with the interconnection among digital components and modules
 Most of the digital circuits are constructed on a single chip, which are referred to as
integrated circuits (IC).
 Integrated circuits contain a large number of interconnected digital circuits within a
single small package.
 Small scale integration (SSI) and medium scale integration (MSI) devices provide digital
functions and large-scale integration (LSI) or Very-large-scale integration (VLSI) devices provide
complete computer modules by combining thousands or millions of transistors into a single chip
 The set of compatible ICs with the same logic levels and same supply voltages have been
fabricated to perform the various logic functions known as logic family.
 Based on the fabrication technology, logic families are classified into two types:
a) Unipolar logic family
o In unipolar logic families, a current flow because of only one type of charge carriers
(that is, either electrons or holes) for example in a MOSFET.
b) Bipolar logic family
 Transistors and diodes are bipolar devices, in which the current flows because
of both the charge carriers (electrons and holes)
 On the basis of operations of transistors in ICs, bipolar logic families are
further classified as: either saturated bipolar logic families or Unsaturated
bipolar logic families
 In saturated bipolar logic families, transistors operate in saturation region
 The transistor is one of the key elements used in logic families. One of the
important applications of the transistor is the switch

Transistor as a switch;
 Transistor is one of the basic elements of logic families. It operates as a switch.
 In switching circuits, transistors operate in cut-off or saturation region. The cut-
off condition is referred to as switch OFF and saturation is referred to as switch
ON
 In the cut-off region, both emitter and collector junctions are in reverse-bias
condition and only reverse current flows in the transistor, which is negligible.
 In the saturation region, both emitter and collector junctions are in forward bias
condition.
 When transistor is operated in the saturation region, voltage across the emitter
junction is VBEsat (0.8 V for silicon and 0.3 V for germanium) and voltage across
emitter and collector terminals is VCEsat. (0.2 V for silicon and 0.1 V for
germanium)

 The condition to operate the transistor in saturation is that the base current
should be greater than the collector current; [IB > IC/]
 When input Vin applied to the transistor is LOW (0 V), the emitter junction is
reverse biased, there is no current flowing through the base terminal and the
current flowing through the collector terminal is reverse saturation current,
which is negligible.
 By applying KVL to the output loop

 When the transistor is operating in cut-off, the output is equal to VCC and it is
referred to as HIGH (logic 1).
 When input Vin that is applied to the transistor is HIGH (+5 V), the emitter
junction is forward biased, current flowing through the base terminal is sufficient
and the transistor operates in saturation region.
 Current flows through the collector terminal and there is a considerable voltage
drop across the collector resistor. And output voltage is
 When the transistor is operating in saturation, the output is equal to VCEsat and it
is referred to as LOW (logic 0). Transistor is either ON or OFF and it is controlled
by the input voltage.

Characteristics of digital ICs

There are various logic families and the selection of a family for a particular
application is based on its characteristics. Real time applications demand high
speed logic families and hence it is necessary to study the characteristics of digital
ICs. Following are the parameters used to compare the performance of digital ICs:

1. Speed of operation-The speed of operation of digital ICs should be high. It is

specified in terms of propagation delay time.
2. Power dissipation-Every electronic circuit requires a certain amount of electric
power for its operation.
 When the power is supplied by an external source, some of it is dissipated in
electronic circuits. It is wastage of power across the circuit components and
devices.
 Requirement of power is less, if the dissipation of power is less. Hence power
dissipation should be as minimum as possible.
3. Figure of merit-The power dissipation of logic families should be minimum to
reduce power requirements. But it is important to note that in logic families, if
the power dissipation is reduced, the speed of operation gets reduced. Hence
the figure of merit is a parameter considered for comparison instead of using the
speed of operation and power dissipation. Figure of merit is a product of
propagation delay and power dissipation. It is measured in terms of Pico-Joules
(ns mW = pJ)
4. Current and voltage parameters- Current and voltage parameters define the minimum
and maximum limit of current and voltage for input and output of a logic family.
5. Fan-out - Fan-out is the capability of a logic gate to drive the maximum number of
similar gates. High fan-out is advantageous, because it reduces the need of
additional gates to drive more gates
6. Fan-in- Fan-in is the number of inputs to a gate. For a two-inputs gate, fan-in is
two; and for a four-inputs gate, fan-in is four.
7. Noise immunity- Unwanted signals are known as noise. The stray electric and
magnetic fields may
induce some noise at an input of digital circuit. Because of noise, the input
voltage may drop or raise which results in undesired operations. The circuit
should have the ability to tolerate the noise signal.
 The noise immunity of digital circuit is defined as the ability of a digital circuit
to tolerate the noise signal. A quantitative measure of noise immunity is
known as noise margin.
8. Power supply requirement- Every electronic circuit requires supply voltage to
operate. The required supply voltage and power by the IC should be as less as
possible.
9. Operating temperature- The operating temperature is the range of temperature in
which an IC
 functions properly. The accepted temperature range of an IC is 0 to +70°C for
commercial and industrial applications.

A) Resistor Transistor Logic

 RTL consists of resistors and transistors. In RTL, transistors operate in cut-off
region or saturation region as per the input voltage applied.
 The figure below shows the circuit of a two-inputs resistor-transistor logic
NOR gate. Here A and B are the inputs of the gate and Y is the output

 When the transistor operates in saturation region, maximum current flows

through resistor RC. The output voltage VY = VCEsat (VCEsat = 0.2 V for
silicon and 0.1 V for germanium); it is logic 0 level voltage.
 When the transistor operates in cut-off, no current flows through resistor
RC and the output voltage VY = VCC = +5 V; it is logic 1 level voltage.
When both the inputs are in logic 0, transistors T1 and T2 operate in cut-
off, and the output is +VCC, i.e. +5 V (logic 1).

 When any one of the inputs is at logic 1 level, the corresponding transistor
operates in saturation, and the output is VY = 0.2 V (logic 0).
 When both the inputs are at logic 1 level, both the transistors operate in
saturation and the output is VY = 0.2 V (logic 0). The operation of circuit is
summarized in the table below;

The truth table; RTL NOR GATE

 The RTL suffers from a few drawbacks as listed below:
1. Low noise margin (Typically 0.1 V)
2. Fan-out is poor (Typically 5)
3. Propagation delay is high and the speed of operation is low (Typically
12 ns)
4. High power dissipation (Typically 12 mW)

B) Transistor-transistor logic
Transistor-transistor logic is one of the popular saturated logic families.
Transistor is the basic element of this logic family, which operates either in
cut-off or saturation region. The first version of TTL is known as the standard
TTL.
Standard TTLs are available in various forms:
1. TTL with passive pull-up
2. TTL with totem-pole output
3. TTL with open collector output
4. Tristate TTL

1. TTL with passive pull-up

 Figure below shows a two-input TTL NAND gate with passive pull-up.
Transistor T1 has two emitter terminals.
 These terminals act as the inputs of the gate, that is, input A and input B. The
input voltages are logic 0 or logic 1, where logic 0 corresponds to 0.2 V and
logic 1 corresponds to +5 V.
  When both the inputs (A and B) are in logic 0, V(0) = VCEsat = 0.2 V, the
emitter junctions of transistor T1 are forward biased and the voltage at the
base of transistor T1 is VB1 = V(0) + VBE = 0.2 + 0.7 = 0.9 V.
 The minimum voltage required at the base of T1, so that T2 and T3 start to
conduct, greater than
the voltage available at the base of T1 and hence T2 and T3 are in cut-off and
the output voltage is equal to the supply voltage VCC (logic 1 level), output is
in logic 1 state.
 When any one of the inputs is at logic 0 level, the corresponding emitter
junction of T1 is forward biased and the voltage at the base of T1 is VB1 = V(0)
+ VBE = 0.2 + 0.7 = 0.9 V. The minimum voltage required at the base of T1,
so that T2 and T3 start to conduct, is VBEcut (in) + VBEcut (in) + 0.7 = 0.5 + 0.5 +
0.7 = 1.7 V. The required voltage is greater than the voltage available at the
base of T1 and hence T2 and T3 are in cut-off and the output voltage is equal
to the supply voltage VCC, output is in logic 1 state.
 When all the inputs are in logic 1 state, the emitter junctions of T1 are reverse
biased and the current supply by the source is sufficient to operate T2 and T3
in saturation and the output is in logic 0 state.

Assignment; research and make short notes on;

 TTL with totem-pole output

 TTL with open collector output

2. Wired AND connection

A wired-AND connection has two or more than two gates connected together.
Using a wired-AND connection, the fan-in of the circuit is increased.
3. Unused inputs
The input circuit of a TTL is shown below;

 When the input is in logic 0 state, the emitter junction is forward biased and
the current flows through the junction.
 When the input is in logic 1 state, the emitter junction is reversed biased and
the current cannot flow through the junction.
 If any one of the inputs of the TTL gate is open, then the corresponding
junction cannot be forward biased, and the current cannot flow. The input
acts exactly in the same way, as in case when logic 1 is applied to that input.
 Therefore, in TTL ICs, all unconnected inputs are treated as logical 1s

4. Tri-state TTL
 A normal digital circuit has two output states: Low and High. The output is
either in high state or low state.
 If the output is not in the low state, it is definitely in the high state. The tri-
state TTL has three output states: High, Low, and High impedance.
 In TTL with totem-pole output, T3 is ON when the output is low and T4 is ON
when the output is high. In high-impedance state, both T3 and T4 in totem-
pole arrangement are turned OFF and as a result, the output is open or
floating.
 When the output is low, the driver gate sinks the load current as shown in
Fig. (a).
 When the output is high, the driver gate supplies the current to the load as
shown in Fig. (b).
 When the output is in high-impedance state, it acts as open or floating and
there is no sink and source current as shown in Fig. (c).
Tri-state TTL inverter
The circuit of a tri-state TTL inverter is shown below

 The tri-state TTL inverter has two inputs—normal input A and enable input E.
When the enable input E is High, the corresponding emitter junction of T1 is
reverse biased and the circuit operates as a normal inverter as explained
below.
 When A is high, the second emitter junction ofT1 is reverse biased. Current
supplied by the source flows through the collector terminal of T1, which forces
T2 and T3 to be in saturation and the output is low. T4 operates in cut-off.
 When A is low, the corresponding emitter junction of T1 is forward biased,
current supplied by the source flows through the emitter terminal of T1,
transistors T2 and T3 operate in cut-off and the output is high. T4 operates in
ON state.
 When the enable input E is low, the corresponding emitter junction of T1 is
forward biased. Current supplied by the source flows through the emitter
terminal of T1, transistors T2 and T3 operate in cut-off.
 Because of low enable input, the diode D2 is forward biased and the current
supplied by the source flows through the diode D2, transistor T4 is operated in
cut-off and thus the output is in high-impedance state