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IEEE P1500, Boundary Scan for SoCs

Kim Petersén
Department of Microelectronics and Information technology
Royal Institute of Technology
164 40 Kista Sweden
Email: kim.petersen@hdc.se

key words: IP, DFT , SoC, NoC.

Development Manufacturing
ABSTRACT IP suppliers IP integrator Silicon vendor
This document briefly describes the upcoming IC
standard IEEE 1500 [1], titled "Standard Testability IP
method for Embedded Core-based Integrated
Circuits".
IEEE P1500 defines a mechanism for the test of Insert at IP- Connect at Use
digital aspects of core designs within a System-on- level IC-level
Chip (SoC). This mechanism is a scaleable standard IEEE P1500 (HW structure)
architecture for enabling test reuse and integration Create Use Create Use
for embedded cores and associated circuitry.

1. INTRODUCTION
IEEE P1450.6 (Information transfer)
The rapid decrease of state of the art silicon process line
width creates the possibility to design SoCs with tens of Fig. 1. How to use IEEE P1500
million of gates, and in a near future 100 million of gates
IEEE P1500 defines a serial and a parallel test access
and above. Such huge designs requires a change of
mechanism a rich instruction set for testing cores, i.e.
development strategy to be able to handle Time to Market
reusable megacells, and SoC interconnect and features
(TTM) demands. One part of this change is visible as a
for core isolation and protection.
change from the traditional transistor level development
to IP level based development of SoCs. IP-level based The description of the IEEE P1500 in this document is
design makes IC development become more similar to focused on the serial access mechanism.
PCB development. One important difference to keep in
mind is that IPs are pre-developed, but not manufactured,
3. OVERVIEW OF HOW TO CONNECT AT THE
blocks of logic.
IC-LEVEL
Increased usage of IP blocks force a change of how DFT The standard does not define how to connect IEEE
(Design for Test) must be carried out at IC-level. P1500 wrapped cores to primary terminals at the IC
Traditionally DFT has been carried out as a more or less level.
a flat activity at IC level. Such strategy could be used in
the absence of IP blocks, since more or less all logic was One possible way of connecting wrapped cores to
developed from scratch in each project. But, with primary terminals at the IC level is shown in figure 2.
increased usage of IP blocks the DFT work must change A 1149.1 wrapped SoC
to a hierarchical activity.
The IEEE P1500 specification does not describe how to P1500
8-10
test individual cores, this is the responsibility of the core Wrapped
WSP
provider. core
T
4-5 P1500
A 8-10
Wrapped
2. OVERVIEW OF HOW TO USE P
P1500 core
IEEE P1500 shall be used in conjunction with the 8-10
Wrapped
standard Core Test Language (CTL) IEEE 1450.6, as core
shown in figure 1. IEEE 1450.6 is part of the
standardisation activity called STIL (Standard Test Interface logic between 1149.1 and P1500
Interface Language), se ref. [3] for further information.
Fig. 2. Example of how connect WSPs at IC-level
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The interface logic needed to connect IEEE P1500 • by the rising edge of WRCK for Capture, Shift and
wrapped cores, as shown in figure 2, into the IEEE Transfer,
1149.1 architecture can be as small as four two-input • and falling edge of WRCK for Update.
OR-gates up to as complex structures as for example an
embedded test processors. The final choice is the WSO only change state at the falling edge of WRCK.
responsibility of the core integrator.
4.1. The Wrapper Serial Port (WSP)
The WSP comprise ten terminals, eight mandatory and
4. THE DIFFERENT PORTS AND REGISTERS
two optional, as shown in figure 4. In reality, one of the
The standard defines a number of ports and registers. optional terminals, AUXCK can exist in any number of
Two different ports are defined, the mandatory Wrapper times. But with the purpose to make the text easier to
Serial Port (WSP) and the optional Wrapper Parallel Port read, it is treated as one single terminal only in this
(WPP). The wrapper terminals in the WSP provide serial paper.
access to the IEEE P1500 wrapper. The WSP terminals facilitate standard “plug and play”
Three different mandatory registers are defined, the operation of the IEEE P1500 architecture. The
Wrapper Instruction Register (WIR), the Wrapper Bypass mandatory part of the WSC part in the WSP is exactly
Register (WBY) and the Wrapper Boundary Register the same outputs achieved from the 16 state TAP
(WBR). They are all more or less similar to the controller defined in the IEEE 1149.1 standard [2]. This
corresponding registers defined in the standard IEEE is by purpose to make it easy to directly connect IEEE
1149.1 [2]. Any number of user specific registers can be P1500 wrapped cores to the IEEE 1149.1 architecture.
added into the IEEE P1500 architecture, indicated by n
"WDR" (Wrapper Data Registers) in figure 3. Also, any AUXCK
TransferDR Optional
number of user specific registers embedded in the core
logic can be connected into the IEEE P1500 architecture, Wrapper WRCK
indicated by "CDR" (Core Data Registers) in figure 3. Serial WRSTN
Shared or control UpdateWR Wrapped
WBR dedicated (WSC) ShiftWR Core
test IOs CaptureWR
WPP SelectWIR
Core WSI Serial data &
WPO
WPI logic WSO Instructions

Fig. 4. Wrapper Serial Port

CDR Functional
IOs AUXCK, any number of user defined auxiliary clock(s)
WDR may be part of the serial port.
WSI WBY WSO
WIR TransferDR is required when the WBR include cells with
WSP
a transfer capability (see section 6 for more information).
WSC 6-8
WRCK is the IEEE P1500 wrapper clock.
Fig. 3. Example of a IEEE P1500 wrapped core WRSTN is the active-low wrapper reset dedicated for
The WBY provides a bypass path for the WSI-WSO IEEE P1500. When asserted, it unconditionally resets the
terminals of the WSP. WIR and puts the wrapper into its normal operation
mode, i.e the wrapper is transparent and the WBY is
The WIR enables all wrapper operations. The WIR can connected between WSI and WSO. WRSTN may be used
optionally be interfaced to the core logic for establishing to reset other wrapper registers or wrapper circuitry as
test mode or functional operation. The WIR can also needed. WRSTN may be either synchronous or
optionally be extended to generate controls for selection asynchronous. It is recommended that WRSTN only is
and operation of other data registers, for example CDRs. de-asserted at the falling edge of WRCK, this sequence
The WBR is the register through which test data stimuli can be used for any implementation of reset. WRSTN is
are applied and pattern responses are captured. This the only terminal at WSP that may be asynchronous to
register allows internal testing of the core logic, as well WRCK.
as testing of external connectivity to other cores and SoC CaptureDR, ShiftDR and UpdateDR: These terminals
integration circuitry, in response to an instruction loaded control and enable wrapper register operations. A
into the WIR. terminal is asserted when it is logic 1and de-asserted
Wrapper register events are enabled when it is logical 0.
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SelectWIR determines type of wrapper register selected. The WBY is the default data register between WSI and
SelectWIR is asserted to logic 1, the WIR is WSO, after WRSTN is asserted, and should be selected
unconditionally selected and connected between WSI and by the current wrapper instruction when no other data
WSO, and enabled to shift, update of capture using the register is selected.
WSP terminals. SelectWIR must be de-asserted to logic 0
in order for any data register (i.e. WBY, WBR, WDR or 4.4. The Wrapper Boundary register (WBR)
CDR) to be selected and connected between WSI and
The WBR can either consists of dedicated (i.e. for test
WSO.
operation only) wrapper boundary cells or shared (i.e.
The WSI and WSI terminals are used for serial scan-in shared between normal functional and test operation)
and scan-out of wrapper serial data and instructions. wrapper boundary cells, or a mixture of dedicated and
shared cells.
4.2. The Wrapper Instruction register (WIR)
IEEE P1500 specifies a total 26 different WBR-cells,
The WIR (see figure 5) is an instruction register in which ranging from lower complexity compared to the
IEEE P1500 wrapper instructions are serially loaded boundary scan cells defined by the standard IEEE 1149.1
through the standard WSP. The WIR contains a shift [2] up to much more complex cells.
stage, instruction decode, and update stage. Only a single
The shift path in each WBR-cell can contain any number
WIR is allowed in each IEEE P1500 wrapper.
of storage elements, from one and upward.
SelectWIR WRSTN may optionally be used to reset the WBR cells to
WBR a known state.
WDRn
Core_Modes 4.5. The Wrapper Parallel Port (WPP)
CDR_Controls CDRn WSO
W WDR_Controls WPP is an optional user defined parallel interface. Its
WSC I WBY terminals are divided into the groups called Wrapper
DR_Select[n:0]
R parallel Input (WPI), Wrapper parallel Output (WPO)
WBR_Control_Modes
DR_WSO and Wrapper parallel Control (WPC). These groups are
WBY_Controls
used when the wrapper is configured into parallel mode.
WSI
The WPP can be used to enable test of the core logic by
Fig. 5. Example of a WIR interface to wrapper and core
using for example Scan or any type of BIST (Built-In
The WIR circuitry shall retain its current state Self Test), when the BIST logic is placed outside the
indefinitely while the WRCK is stopped, provided that wrapped core.
the WRSTN terminal is logical 1.
The WIR will reset to the WS_BYPASS wrapper 5. WIR INSTRUCTIONS
instruction whenever the WRSTN terminal transition to a The instruction loaded into the WIR , together with the
logic 0. The minimum length of the WIR is two storage IEEE P1500 wrapper signals, determine the mode of
elements. operation of the wrapper and possibly the core itself. A
particular instruction may result in one or more wrapper
4.3. The Wrapper Bypass register (WBY) or core data registers being serially connected between
The WBY provides a minimum-length serial path WSI and WSO or WPI and WPO. Further, the active
between the wrapper's WSI and WSO. This allows more instruction may select one or more other registers,
rapid movement of test data to and from other core separate from the register(s) between WSI and WSO or
wrappers, provided the wrappers are connected serially. WPI and WPO.

Each WBY can be configured as an n-bit bypass shift- A total of 11 instructions are defined, three of them are
register, as shown in figure 6, where n ≥1. A one-bit unconditionally mandatory:
WBY is the preferred length. But, the possibility to make • WS_BYPASS
a WBY longer than one bit makes it possible to connect • WS_EXTEST.
IEEE P1500 wrapped cores together hierarchically, this • Wx_INTEST.
without violating the IEEE P1500 compliance.
One of the 11 instructions are conditionally mandatory,
Serial shift stage and must be included when the IEEE P1500 architecture
To WSO comprise a WBR composed entirely of cells with a
WSI n-1 0 dedicated flip-flop on its output.
ShiftWBY WCLK
• WS_PRELOAD
Fig. 6. Wrapper Bypass Register
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The binary value for each instruction is not defined in the WS_EXTEST. It is assumed that all inputs are at the left
standard specification, and may be selected by the side and all outputs at the right side.
wrapper designer (normally the core provider).
Shift: On each rising edge at WRCK data is advanced
It is possible to add any number of user defined one storage position from WSI to WSO, as shown in
instructions. figure 7.
The WS_BYPASS instruction is selected when no test Update: It is an optional event whereby data stored
operation of that core is required, the instruction closest to its shift output is loaded into an off-shift
connects WBY between WSI and WSO. storage element.
The WS_EXTEST instruction allows testing of off-core Capture: The value present on the functional input is
circuitry and core-to-core interconnections. While the stored into its WBR cell storage element closest to its
WS_EXTEST instruction is selected, only the WBR shall shift output.
be connected for serial access between WSI and WSO,
Transfer: It is an optional event whereby shift is carried
i.e. no other test data register may be connected in series
out locally at each individual WBR cell, and not on the
with the WBR.
entire WBR as in the event Shift. On each cell data is
The WX_INTEST instruction allows testing of the core shifted into, out from or within the cell, but not between
circuitry. While the Wx_INTEST instruction is selected, cells in the WBR. This event is introduced to enable test
the WBR shall be in inward facing mode, and the at full clock speed.
operation of the core should not disturb circuitry external
Apply: It is inferred from the operation from the other
to the core (the x in Wx is a place holder for an S, P or H
four events.
to indicate weather the instruction is serial, parallel or
hybrid). A hybrid instruction is a wrapper instruction
which has mixed use of WSP and WPP terminals. A Core Core Core Core
serial instruction is a wrapper instruction that exclusively
uses WSP terminals. A parallel instruction is a wrapper
instruction which uses WPP terminals and also
Shift Update Capture Transfer
configures the WBY between WSI and WSO.
The WS_PRELOAD instruction enables the wrapper to Fig. 7. Function of the four of the five predefined events
be functionally configured, and is used to allow shifting
of the WBR via WSI and WSO, without causing 7. FUTURE WORK
interference to the operation of the core logic. This Investigate if IEEE P1500 is applicable also for designs
instruction would typically be utilised before other of type Network-on-Chip (NoC).
defined instructions are selected (e.g. WS_EXTEST).

8. REFERENCES
6. WRAPPER STATES
[1] IEEE Std. P1500/D0.8, December 2003. Standard
A wrapper can be in one of two main states, disabled and Testability Method for Embedded Core-based
enabled. Integrated Circuits.
As long as WRSTN is equal logic 0, the wrapper is [2] IEEE Std 1149.1-1990; IEEE Standard Test Access
unconditionally in a disable state (i.e. the wrapper is Port and Boundary-Scan Architecture.
transparent, with the instruction WS_BYPASS in the [3] IEEE Std. P1460, December 2003. Extensions to
WIR and with WBY connected between WSI and WSO, STIL for Core Test Language (CTL) Support.
and the core logic is operating in normal mode). STIL is an abbreviation for Standard Test Interface
Language.
As long as WRSTN is equal to logic 1, the wrapper is
enabled. This implies that the operation of the wrapper is
fully defined by the combination of the contents in the
WIR together with the status of the terminals at the WSP.
The terminals at the WSP sets each instruction into one
of the possible pre-defined evens called Shift, Update,
Capture , Transfer and Apply. One or more of these
events apply to each instruction implemented. The
instruction WS_EXTEST will be used, in the text to
follow, to describe the correlation between instruction
and event. In figure 7 is the functionality described for
four different events when the instruction in the WIR is