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Wrapper p1500

The IEEE 1500 standard defines a core wrapper architecture that consists of wrapper cells inserted at core input and output ports. The wrapper interfaces the core ports to wrapper boundary registers, including a wrapper serial input pin, serial output pin, and control pins. The wrapper can operate in INTEST, EXTEST, and bypass modes to test the core logic or interconnect wiring outside the core while isolating or blocking signals.

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3K views8 pages

Wrapper p1500

The IEEE 1500 standard defines a core wrapper architecture that consists of wrapper cells inserted at core input and output ports. The wrapper interfaces the core ports to wrapper boundary registers, including a wrapper serial input pin, serial output pin, and control pins. The wrapper can operate in INTEST, EXTEST, and bypass modes to test the core logic or interconnect wiring outside the core while isolating or blocking signals.

Uploaded by

srikanth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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 The IEEE 1500 standard provides a standard interface to create an isolation boundary

between a core to be tested and the logic external to the core


 The isolation boundary consists of wrapper cells which are inserted for each functional
input and output port on the core.

 Wrapper Boundary Registers (WBR) that consist of one or more wrapper cells which
interface the core functional ports to the chip
 A mandatory Wrapper Serial Input (WSI) pin, Wrapper Serial Output (WSO) pin, and a
set of Wrapper Serial Control (WSC) pins.
 The Wrapper Bypass Register (WBY) is the IEEE 1500 register that provides an
abbreviated data register between wrapper serial input (WSI) and wrapper serial output
(WSO).
 The Wrapper Instruction Register (WIR) is the IEEE 1500 register used to serially load
and store IEEE 1500 instructions.
1500 wrapper architecture can operate in three types of modes

INTEST

 Enable testing of the core logic via the core test wrapper
 Block data signals external to the core at the wrapped input ports

 Allow guarding of core outputs (using the wog signal) since logic external to the core should not
be affected
EXTEST

 Enable testing of the interconnect wiring and logic outside the core

 Block data signals generated internal to the core at wrapped output ports
 Allow guarding of core inputs (using the wig signal) since core logic should not be affected

Wrapper disable modes

 Disable wrapper logic enabling full core testing assuming full pin access and control
 Allow normal functional operation
Input Wrapper Cells:

Output Wrapper Cells:


Dedicated wrappers cells INTEST:

Shared Wrapper Cells


Conditions to statisfy Flop to become shared wrapper cell:
 There has to be at least one flop in the fanin/fanout cone.
 The logic in the fanin/fanout cone should be completely defined; there cannot not be
any black boxes or abstract cells.
 Should be a scan mapped flop
 Should pass the DFT rule checker
 Should have a unique functional connection, that is, only either Q or QB should be
functionally connected.
 Cannot be part of any other scan chains
 Cannot be part of any other scan segment other than pre-existing wrapper segments
 Cannot be preserved (preserve or inherited_preserve attributes cannot be true or
size_ok)

Differece between JTAG and Wrapper:


 JTAG is Seral IN Serial OUT
 Wrapper is Serial In , Parallel Out

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