03 Hardware and Virtual Machines

Candidates should be able to:

Show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC)
processors

Show understanding of the importance/use of pipelining and registers in RISC processors

Show understanding of the four basic computer architectures

Show understanding of the characteristics of massively parallel computers

Show understanding of the concept of a virtual machine

Produce truth tables for logic circuits including half adders and full adders

Show understanding of a flip-flop (SR, JK)

Show understanding of Boolean algebra

Show understanding of Karnaugh maps (K-map)

Definitions
Instruction level parallelism applied to execution of instructions during
Pipelining
Fetch-Execute cycle

SISD (Single Instruction

A single processor handles a single instruction at a time
Single Data)

SIMD (Single Instruction Many processors execute the same instructions but use different data
Multiple Data) inputs

MISD (Multiple Instruction Multiple processors execute different instruction but use the same shared
Single Data) data source

MIMD (Multiple Instruction Multiple processors take instructions independently and use data from a
Multiple Data) separate data source

Massively Parallel Large number of processors working collaboratively on the same program
Computers simultaneously communicating via messaging interface

A software that emulates a different computer system and allows multiple

Virtual Machine Software
guest OS’s to run on one computer

Guest Operating System The OS running in a Virtual Machine

Host Operating System The OS that is controlling the actual physical hardware

Half adder A logic circuit that adds two bits together and outputs their sum

Full adder Adds two bits and a carry bit from the previous calculation together

Circuits in which the output depends on the input value produced form a
Sequential Circuits
previous output value

Karnaugh Maps (K-map) A method used to simplify logic statements and logic circuits

Ordering o binary numbers such that successive numbers differ by 1 bit

Gray Code
only

3.1 Processors, Parallel Processing and Virtual Machines

3.1.1 RISC and CISC Processors

03 Hardware and Virtual Machines 1

 CISC Processors
Complex Instruction Set Computer

A single instruction can be more complex and involve more loading of data from memory

RISC Processors
Reduced Instruction Set Computer

A single instruction is simpler, requiring minimal loading of data from memory

CISC features RISC features

Many instruction formats are possible Uses fewer instruction formats/sets

There are more addressing modes Uses fewer addressing modes

Makes use of multi-cycle instructions Makes use of single-cycle instructions

Instructions can be of a variable length Instructions are of a fixed length

Longer execution time for instructions Faster execution time for instructions

Decoding of instructions is more complex Makes use of general multiple-purpose registers

It is more difficult to make pipelining work Easier to make pipelining function correctly

The design emphasis is on the hardware The design emphasis is on the software

Uses the memory unit to allow complex

Processor chips require fewer transistors
instructions to be carried out

Pipelining
Instruction level parallelism applied to execution of instructions during Fetch-Execute cycle

Execution of instructions is split into stages

Instruction fetch cycle (IF)

Instruction decode cycle (ID)
Operand fetch cycle (OF)
Instruction execution cycle (IE)
Writeback result process (WB)

When one instruction is done, the same stage of another instruction can be executed

Hence, an instruction can start executing before the previous one has finished, allowing several instructions to be
processed simultaneously

Used extensively in RISC processor based systems to reduce the time taken to run processes

Can be a data dependency issue where one instruction is not done with generating a result that is used by the
subsequent instruction.

Solution: Swap the instruction that wants to access to early with the next one that doesn’t depend on the result

Interrupts
Once the processor detects the existence of an interrupt, the current program would be temporarily stopped

The status of each register is stored; the processor can then be stored to its original status before the interrupt was
received and serviced

With pipelining, a number of instructions could be in the pipeline as the instruction is received

Solution: Discard all instructions in the pipeline except for the last instruction in the write-back (WB) stage

Interrupt Service Routine (ISR) can then be applied to this remaining instructions, and once serviced, the processor
can restart with the next instruction in the sequence.

Alternatively, contents of the five stages can be stored in registers

03 Hardware and Virtual Machines 2

 3.1.2 Parallel Processing
Parallel Processor Systems
SISD (Single Instruction Single Data)

A single processor handles a single instruction at a time

SIMD (Single Instruction Multiple Data)

Many processors execute the same instructions but use different data inputs

MISD (Multiple Instruction Single Data)

Multiple processors execute different instruction but use the same shared data source

MIMD (Multiple Instruction Multiple Data)

Multiple processors take instructions independently and use data from a separate data source

Massively Parallel Computers

Large number of processors working collaboratively on the same program simultaneously communicating via
messaging interface

The processors do no share bus

Issue: Complex topology in connecting the processors so that they can communicate

To adapt code to run on it:

Split code into blocks that can be processed simultaneously instead of sequentially

Each block would be processed by a different browser

3.1.3 Virtual Machines (VMs)

Virtual Machine software is a software that creates/delete/manage virtual machine

Emulate the hardware

Protect each virtual machine

Allows multiple guest OS’s to run on one computer

Features of a Virtual Machine

Guest Operating System

This is the OS running in a VM

It controls the virtual hardware during the emulation

This OS is being emulated within another OS

The guest OS is running the control of the host OS software

Host Operating System

This is the OS that is controlling the actual physical hardware

It is the normal OS for the host

The OS runs the virtual machine software

Process when Application in guest OS makes a request to guest OS to get data from file:

Guest OS handles request as normal

I/O request translated by VM software into instructions for host OS

Host OS gets data from file

03 Hardware and Virtual Machines 3

 Host OS passes data to VM software

VM software passes data to guest OS

Guess OS passes data to application

Benefits and Limitations of Virtual Machines

Benefits

Multiple guest OS can be used on the same computer

Different Instructure set architectures can be emulated on a single computer

A virtual machine can crash without affecting the host machine

Security benefits; if it has a virus, it will only infect the virtual machine

Limitations

Has poorer performance than real machines because of extra load on the computer

Performance of the guest system cannot be adequately measured

A virtual machine may be affected by any weaknesses of the host machine

Costly to maintain

Cannot emulate some hardware

03 Hardware and Virtual Machines 4

 Skill Check 1

1. Most desktop or laptop computers uses CISC (Complex Instruction Set Computing) architecture. Most smartphones
and tablets use RISC (Reduced Instruction Set Computing). [4]

State
four features that are different for the CISC and RISC architectures

2. In a RISC processor, four instructions (A, B, C, D) are processed using pipelining.

The following table shows five stages that take place when instructions are fetched and executed. In time interval
1, instruction A has been fetched.

a. In the table, write the instruction labels (A, B, C, D) in the correct time interval for each stage. Each operation
only takes one time interval. [3]

Time Interval

Stage 1 2 3 4 5 6 7

Fetch
A
Instruction

Decode
Instruction

Execute
Instruction

Access
operand in
memory

Write result to
register

b. When completed, the table in part (b)(i) shows how pipelining allows instructions to be carried out more rapidly.
Each time interval represents one clock cycle.
Calculate how many clock cycles are saved by using pipelining in the example in
part (b)(i).
Show your working.

3. The table shows four statements about computer architecture.

Put a cross in each row to identify the computer architecture associated with each statement.

Statement SIMD MIMD SISD

Each processor executes a

different instruction

There is only one processor

Each processor executes the same

instruction input using data
available in the dedicated memory

Each processor typically has its

own partition within a shared
memory

Solution

1. RISC has fewer instructions than CISC. RISC has many registers, while CISC has a few registers. RISCs
instructions are simpler than CISC instructions. RISC has better pipelineability than CISC. RISC makes more use
of RAM than CISC.

03 Hardware and Virtual Machines 5

 2. .

a. Stage 1 2 3 4 5 6

Fetch
A B C D
Instruction

Decode
A B C D
Instruction

Execute
A B C D
Instruction

Access
operand in A B C
memory

Write result to
A B
register

b. Cycles with pipelining = 8

Cycles without pipelining = 4*5 = 20
Cycles saved = 20-8 =
12

3.

Statement SIMD MIMD SISD

Each processor executes a different

X
instruction

There is only one processor X

Each processor executes the same

instruction input using data available in the X
dedicated memory

Each processor typically has its own

X
partition within a shared memory

3.2 Boolean Algebra and Logic Circuits

3.2.1 Boolean Algebra
A form of algebra linked to logic circuits

Laws in Boolean Algebra:

Commutative Laws A + B= B + A A.B = B.A

A + (B + C) = (A + B) +
Associative Laws A.(B.C) = (A.B).C
C

A.(B + C) = (A.B) +
(A.C)
Distributive Laws A + (B.C) = (A + B).(A + C)
(A + B)
.(A + C) = A + B.C

Idempotent Laws A.A = A A+A=A

Identify Laws 1.A = A 0+A=A

Null Laws 0.A = A 1+A=1

Inverse Laws A.A = 0  A + A = 1

Absorption Laws A.(A + B) = A A + A.B = A

03 Hardware and Virtual Machines 6

 A + A.B = A A + A.B = A + B 
De Morgan’s Laws A.B = A + B  A + B = A.B 
​

Double Negative
A = A
Law

Note: The minus sign in the last two row signifies NOT (For example A- = A̅)

3.2.2 Further Logic Circuits

Half Adder Circuit and Full Adder Circuit
Half Adder

A logic circuit that adds two bits together and outputs their sum

S is the Sum bit

C is the Carry bit

Inputs Outputs

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Limitation: Not possible to consider carry when adding

Full Adder

03 Hardware and Virtual Machines 7

 Inputs Output

A B C_in (Carry in) S C_out (Carry out)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

3.2.3 Flip-Flop Circuits

Sequential circuits are circuits in which the output depends on the input value produced form a previous output value

Have 2 states

Store 1 bit, 0 or 1

Used in memory

SR Flip-Flops
Consists of 2 cross-coupled NAND or NOR gates

Q and Q̅ MUST be complements

03 Hardware and Virtual Machines 8

 Inputs Outputs Comment

S R Q Q̅

1 0 1 0

0 0 1 0 following S=1 change

0 1 0 1

0 0 0 1 following R=1 change

1 1 0 0

Problem:

The last row is an invalid state as Q and Q̅ have the same value

Signals may arrive at different times

JK Flip-Flops
To overcome SR issues:

A clock and additional gates are added which helps synchronize the 2 inputs

4 possible input conditions: 1, 0, no change, toggle

When clock is 0, no changes are made

03 Hardware and Virtual Machines 9

 Value of Q
Value of Q after
J K before clock Output
clock pulse
pulse

0 0 0 0
Q is unchanged
after clock pulse
0 0 1 1

1 0 0 1
Q=1
1 0 0 1

0 1 0 0
Q=0
0 1 1 0

1 1 0 1
Q value toggles
between 0 and 1
1 1 1 0

Uses of JK Flip-Flops

Used to produce shift registers in a computer

A simple binary counter can be made by linking up several JK flip-flop circuits

3.2.4 Karnaugh maps (K-maps)

A method used to simplify logic statements and logic circuits

It uses gray codes

Gray Code: Ordering o binary numbers such that successive numbers differ by 1 bit only

Rules:

The values along the top and the bottom follow Gray code rules

Only cells containing a 1 are taken account of

Groups can be a row, a column or a rectangle

Groups must contain an even number of 1s (2, 4, 6, and so on)

Groups should be as large as possible

Groups may overlap within the above rules

Single values can be regarded as a group even if they cannot be combined with other values to form a larger group

The final Boolean expression can only consider those values which remain constant within the group

03 Hardware and Virtual Machines 10

 Skill Check 2

1. Complete the Karnaugh map (K-map) for the Boolean expression

Z = A.B.C .D + A.B.C .D + A.B.C .D + A.B.C .D + A.B.C .D + A.B.C .D

2. Draw loop(s) around appropriate group(s) in the K-map to produce an optimal sum-of-products

3. Write the Boolean expression from your answer to part (b) as a simplified sum-of-products. Use Boolean algebra
to give your answer in its simplest form.

Solution

1.

2.

03 Hardware and Virtual Machines 11

 3. Z = BC + AC 
Z = C (A + B)

Points To Note
A control unit can be hard-wired or microprogrammed

RISC (Reduced Instruction Set Computers) processors have a number of advantages compared to CISC (Complex
Instruction Set Computers)

Pipelining is one of the reasons for choosing a RISC architecture

Parallelism can be based at the instruction level, processor level or computer level

A system virtual machine is software emulating hardware

The Java Virtual Machine is an example of a process virtual machine

Binary addition can be carried out using a half adder or a full adder circuit

SR or JK flip-flop circuits can be used to store a bit value

There are Boolean algebra laws that can be used to simplify logic expressions

The sum-of-products method can be used to create an equivalent logic expression containing minterms from a truth
table

A Karnaugh map is a representation of a truth table that allows a simplified logic expression to be derived from a truth
table

03 Hardware and Virtual Machines 12