CENTRE FOR MEDICAL AND RADIATION

PHYSICS
NISER BHUBANESWAR

LABORATORY REPORT
Study of Boolean Logic Expressions and Adder ,
Subtractor Circuits

Submitted By: Satya Prabodh Nayak

Roll No: 241126004
2nd Semester, Session: 2024-25

Date of Experiment:19th February 2025

Date of Submission:12th March 2025

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Contents
1 Aim 3

2 Apparatus Required 3

3 Theory 3

4 Observation 9
4.1 De Morgan’s Law Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Conclusion 21

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1 Aim
To verify the De Morgan’s law and Study of adder and subtractor using digital ICs.

2 Apparatus Required
• Breadboard
• Power Supply – To connect the power source (+5V and GND).
• Connecting Wires – For interconnecting IC pins and components.

Logic Gate IC Number Description

AND Gate 7408 Quad 2-input AND gate
OR Gate 7432 Quad 2-input OR gate
NOT Gate 7404 Hex Inverter (NOT gate)
NAND Gate 7400 Quad 2-input NAND gate
NOR Gate 7402 Quad 2-input NOR gate
XOR Gate 7486 Quad 2-input XOR gate

3 Theory
Boolean algebra consists of postulates and identities that help in simplifying expressions or trans-
forming them into more desirable forms. One of the fundamental theorems in Boolean algebra is

De-Morgan’s Laws
De-Morgan’s Laws consist of two important conditions:

First Law
The complement of the product of two variables is equal to the sum of the complement of each
variable. Mathematically, if A and B are Boolean variables, then:

A·B =A+B

Second Law
The complement of the sum of two variables is equal to the product of the complement of each
variable. Mathematically, if A and B are Boolean variables, then:

A+B =A·B
These laws are widely used in Boolean algebra for simplification and logic circuit design.
Logic families refer to different technological approaches used to construct logic gates. Logic
gates are digital circuits that execute fundamental logical operations such as AND, OR, NOT,

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NAND, and NOR. A logic family consists of a set of ICs that share the same logic levels and oper-
ating voltage, making them compatible with each other for implementing various logical functions.

Logic Levels
Logic levels define how binary states (0 and 1) are represented in a circuit. There are two main
types:

• Positive Logic: A low voltage level represents 0, while a high voltage level represents 1. In
this system, an ON state corresponds to a high voltage, whereas an OFF state corresponds
to a low voltage.
• Negative Logic: A high voltage level represents 0, while a low voltage level represents 1.
Here, the ON state is indicated by a low voltage, and the OFF state is indicated by a high
voltage.

Logical Functions
Logical functions correspond to the operations performed by logic gates. The most commonly used
logical functions include:

• AND

• OR
• NOT
• NAND
• NOR

• XOR

Fabrication of Logic Families

Logic families are built using semiconductor technologies that incorporate diodes and transistors as
switching elements.

• Diodes: Function as simple switches with two states—ON in forward bias and OFF in reverse
bias.
• Transistors: Consist of three terminals (collector, base, and emitter). Their switching state
is controlled by the base voltage, enabling or blocking current flow between the collector and
emitter.

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Selection of Logic Families
The choice of logic families depends on several factors, including:

• Switching Speed – Determines how fast the circuit operates.

• Fan-Out Capability – Defines the number of gates that can be driven by a single output.
• Power Consumption – Affects the efficiency and thermal performance of the circuit.

Transistor-Transistor Logic (TTL) is a digital logic family that utilizes bipolar junction transistors
(BJTs) for logic operations and switching. It operates with a supply voltage of approximately 5V,
offers high-speed switching, and has a typical fan-out of 10. TTL circuits exhibit low propagation
delay, consume around 10mW of power, and are widely used in logic gates, memory circuits, and
microprocessors.

Half Adder
A half adder is a combinational logic circuit designed to add two single-bit binary numbers. It
produces two outputs: the sum and the carry.

The circuit is referred to as a half adder because it only performs the addition of two bits but
does not consider any carry input from a previous addition. Since a complete addition operation
requires handling the carry input, this circuit performs only half the function, hence the name.

Truth Table for Half Adder

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Boolean Expressions
• Sum: SUM = A′ B + AB ′ = A ⊕ B (XOR gate)
• Carry: CARRY = AB (AND gate)

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 Figure 1: Half Adder

Full Adder
A full adder extends the functionality of a half adder by incorporating an additional carry input,
enabling it to process multi-bit binary addition.

Truth Table for Full Adder

A B Y (Carry In) SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Expressions
• Sum: SUM = A ⊕ B ⊕ Y
• Carry: CARRY = AB + BY + AY

Full Adder Using Half Adders

A full adder can be constructed using two half adders. The sum output of the first half adder is
XORed with the carry input, and the carry output is obtained by ORing the carry outputs of both
half adders.

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 Figure 2: Full Adder

Half Subtractor
A half subtractor is a combinational circuit that performs subtraction of two 1-bit binary numbers.
It produces two outputs: the difference and the borrow. Since it does not consider borrow from
a previous stage, it is called a half subtractor.

Truth Table for Half Subtractor

A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Boolean Expressions
• Difference: DIFFERENCE = A′ B + AB ′ = A ⊕ B (XOR gate)

• Borrow: BORROW = A′ B (AND gate with NOT)

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 Figure 3: Half Subtractor

Full Subtractor
A full subtractor accounts for the borrow from the previous stage, making it a complete subtrac-
tion circuit.

Truth Table for Full Subtractor

A B D (Borrow In) DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Boolean Expressions
• Difference: DIFFERENCE = A ⊕ B ⊕ D

• Borrow: BORROW = A′ D + BD + A′ B

Full Subtractor Using Half Subtractors

A full subtractor can be designed using two half subtractors. The difference is obtained by XORing
the third input with the output of the half subtractor, while the borrow output combines additional
terms logically.

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 Figure 4: Full Subtractor

4 Observation
We have verified the truth table for logic gates and boolean expressions using ICs resistors and
LED.

NOT (Inverter)
Input (V) Output (V)
5V (1) 0V (0) (LED OFF)
0V (0) 5V (1) (LED ON)

Figure 5: Inverter Circuit

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AND Gate
A (V) B (V) Output (V)
0V (0) 0V (0) 0V (0) (LED OFF)
0V (0) 5V (1) 0V (0) (LED OFF)
5V (1) 0V (0) 0V (0) (LED OFF)
5V (1) 5V (1) 5V (1) (LED ON)

Figure 6: AND gate Circuit

OR Gate
A (V) B (V) Output (V)
0V (0) 0V (0) 0V (0) (LED OFF)
0V (0) 5V (1) 5V (1) (LED ON)
5V (1) 0V (0) 5V (1) (LED ON)
5V (1) 5V (1) 5V (1) (LED ON)

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 Figure 7: OR Gate Circuit

NAND Gate
A (V) B (V) Output (V)
0V (0) 0V (0) 5V (1) (LED ON)
0V (0) 5V (1) 5V (1) (LED ON)
5V (1) 0V (0) 5V (1) (LED ON)
5V (1) 5V (1) 0V (0) (LED OFF)

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Figure 8: Nand Circuit

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 Figure 9: 3 INPUT NAND Circuit

NOR Gate
A (V) B (V) Output (V)
0V (0) 0V (0) 5V (1) (LED ON)
0V (0) 5V (1) 0V (0) (LED OFF)
5V (1) 0V (0) 0V (0) (LED OFF)
5V (1) 5V (1) 0V (0) (LED OFF)

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 Figure 10: NOR Circuit

XOR Gate
A (V) B (V) Output (LED)
0V (0) 0V (0) LED OFF
0V (0) 5V (1) LED ON
5V (1) 0V (0) LED ON
5V (1) 5V (1) LED OFF

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 Figure 11: XOR Circuit

Half Adder
A (V) B (V) SUM (V) CARRY (V)
0V (0) 0V (0) 0V (0) (LED OFF) 0V (0) (LED OFF)
0V (0) 5V (1) 5V (1) (LED ON) 0V (0) (LED OFF)
5V (1) 0V (0) 5V (1) (LED ON) 0V (0) (LED OFF)
5V (1) 5V (1) 0V (0) (LED OFF) 5V (1) (LED ON)

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 Figure 12: Half adder Circuit

Full Adder
A (V) B (V) Cin (V) SUM (V) CARRY (V)
0V (0) 0V (0) 0V (0) 0V (0) (LED OFF) 0V (0) (LED OFF)
0V (0) 0V (0) 5V (1) 5V (1) (LED ON) 0V (0) (LED OFF)
0V (0) 5V (1) 0V (0) 5V (1) (LED ON) 0V (0) (LED OFF)
0V (0) 5V (1) 5V (1) 0V (0) (LED OFF) 5V (1) (LED ON)
5V (1) 0V (0) 0V (0) 5V (1) (LED ON) 0V (0) (LED OFF)
5V (1) 0V (0) 5V (1) 0V (0) (LED OFF) 5V (1) (LED ON)
5V (1) 5V (1) 0V (0) 0V (0) (LED OFF) 5V (1) (LED ON)
5V (1) 5V (1) 5V (1) 5V (1) (LED ON) 5V (1) (LED ON)

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 Figure 13: Full Adder Circuit

Half Subtractor
A (V) B (V) DIFFERENCE (V) BORROW (V)
0V (0) 0V (0) 0V (0) (LED OFF) 0V (0) (LED OFF)
0V (0) 5V (1) 5V (1) (LED ON) 5V (1) (LED ON)
5V (1) 0V (0) 5V (1) (LED ON) 0V (0) (LED OFF)
5V (1) 5V (1) 0V (0) (LED OFF) 0V (0) (LED OFF)

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 Figure 14: Half Subtractor Circuit

Full Subtractor
A (V) B (V) Borrow In (V) DIFFERENCE (LED) BORROW OUT (LED)
0V (0) 0V (0) 0V (0) LED OFF LED OFF
0V (0) 0V (0) 5V (1) LED ON LED ON
0V (0) 5V (1) 0V (0) LED ON LED ON
0V (0) 5V (1) 5V (1) LED OFF LED ON
5V (1) 0V (0) 0V (0) LED ON LED OFF
5V (1) 0V (0) 5V (1) LED OFF LED OFF
5V (1) 5V (1) 0V (0) LED OFF LED OFF
5V (1) 5V (1) 5V (1) LED ON LED ON

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 Figure 15: Full Subtractor Circuit

4.1 De Morgan’s Law Verification

The verification of De Morgan’s laws was conducted by constructing the equivalent logic circuits
and comparing their outputs. The truth table results, observed using LED indicators, confirmed
that the complement of a product equals the sum of the complements, and vice versa.

A (V) B (V) A · B (LED) A + B (LED)

0V (0) 0V (0) LED ON LED ON
0V (0) 5V (1) LED ON LED ON
5V (1) 0V (0) LED ON LED ON
5V (1) 5V (1) LED OFF LED OFF

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A (V) B (V) A + B (LED) A · B (LED)
0V (0) 0V (0) LED ON LED ON
0V (0) 5V (1) LED OFF LED OFF
5V (1) 0V (0) LED OFF LED OFF
5V (1) 5V (1) LED OFF LED OFF

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5 Conclusion
In this experiment, we analyzed the functionality of basic logic gates, adders, and subtractors by
verifying their truth tables. The outputs were observed using LED indicators, where logic high (5V)
turned the LED ON, and logic low (0V) turned the LED OFF. The experimental results confirmed
the expected behavior of each logic circuit, demonstrating their practical applications in digital
systems.

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