Topic 3

Large Scale Integration (LSI) Design

[PLDs]

Mar 07 2025
By Dr. Ahuna
By Dr. Ahuna
 PLDs
2
Introduction
 Most popular digital ICs were TTL logic family (74xxx series). Today they
are hardly used in industrial applications. They are used only in education
field for learning the concepts of digital electronics. They are very rapidly
being replaced by new kind of devices called as Programmable Logic
Devices (in short PLDs)
 74xx and other contemporary ICs are fixed function ICs. Normally they are
SSI (small scale integration) and MSI (Medium scale integration) chips.
Once the function is implemented by manufacturer it can never be changed.
 Whereas in PLDs the logic function is programmed by the user. In this
case, the user can reprogram the device as many times as they want. Hence
these ICs are called PLDs. Today PLDs are used extensively in industry.
 For programming PLDs the user needs to know the features of Hardware
Description Language (HDL). Either VHDL or VERILOG is used for
programming PLDs.
By Dr. Ahuna
 PLDs
Types of PLDs
3
 Programmable logic devices are mainly of three types. These are classified
according to the complexity in design.
1. SPLD (Simple Programmable Logic Device)
2. CPLD (Complex Programmable Logic Device)
3. FPGA (Field Programmable Gate Array)

By Dr. Ahuna
 PLDs
Types of PLDs
4
 Programmable logic devices are mainly of three types. These are classified
according to the complexity in design.
1. SPLD (Simple Programmable Logic Device)
2. CPLD (Complex Programmable Logic Device)
3. FPGA (Field Programmable Gate Array)
Construction of PLDs:
 All PLDs consist of programmable arrays. An array is essentially a grid of
conductors forming rows and columns with fusible links at each cross point
(similar to matrix of diode at each cross point).
 Arrays are of fixed type or programmable type. A PLD consists of an OR array
and AND array.

By Dr. Ahuna
 PLDs
The OR Array
5
 Construction of OR array is shown in Fig. 1. It consist of a matrix of rows and
columns and number of OR gates.
 The rows and columns are interconnected with the help of fusible links. In the
beginning all the links are closed. Selectively some of these links are open and
others are retained. This is called as programming the array.
 The matrix connections of two dimensional structures are given to the OR gates. In
a row to connect the desired input to the OR gate, only one fuse is left intact. The
other links are open.
 Vertically to the columns the inputs and their compliments are connected (A, A’, B,
B’). This process of programming is carried out till the last row. The equations are
then implemented by an OR array.

By Dr. Ahuna
 PLDs
The OR Array
6 X = programming to be done

Figure1: Logic diagram of OR array with six rows and four columns
By Dr. Ahuna
 PLDs
The OR Array
7 X = programming to be done

Figure 2: An OR array after programming

By Dr. Ahuna
 PLDs
The OR Array
8 X = programming to be done

NOTE: Cross indicates programming to be done and dot indicates programmed connection

By Dr. Ahuna
 PLDs
The OR Array
9
 Construction of OR array is shown in Fig. 1. It consist of a matrix of rows and
columns and number of OR gates.
 The rows and columns are interconnected with the help of fusible links. In the
beginning all the links are closed. Selectively some of these links are open and
others are retained. This is called as programming the array.
 The matrix connections of two dimensional structures are given to the OR gates. In
a row to connect the desired input to the OR gate, only one fuse is left intact. The
other links are open.
 Vertically to the columns the inputs and their compliments are connected (A, A’, B,
B’). This process of programming is carried out till the last row. The equations are
then implemented by an OR array.
 For example if the equation to be implemented is X1= A + B then A is selected on
row1 and B is selected on row2 so OR gate implements A+B. Similarly other
expressions are implemented by using other rows and columns and other OR gates.
By Dr. Ahuna
 PLDs
The OR Array
10
 As discussed earlier the OR array consists of an array of OR gates connected to
programmable matrix with fusible links at each cross point of a row and column.
 The OR array is programmed by blowing the fuses to eliminate the variables and
retain only one connection in a row. Therefore for each i/p to OR gate only one
fuse is left intact in order to connect the desired variable to the gate i/p.
 Once the fuse is blown it cannot be reconnected.

By Dr. Ahuna
 PLDs
The OR Array
11
 As discussed earlier the OR array consists of an array of OR gates connected to
programmable matrix with fusible links at each cross point of a row and column.
 The OR array is programmed by blowing the fuses to eliminate the variables and
retain only one connection in a row. Therefore for each i/p to OR gate only one
fuse is left intact in order to connect the desired variable to the gate i/p.
 Once the fuse is blown it cannot be reconnected.

Note:
Another method of programming a PLD is to use an antifuse. It is opposite to fuse. In
this normally open contact is shorted by melting the antifuse material to form a
contact or short a connection. Other places are left open.

By Dr. Ahuna
 PLDs
The AND Array
12  Construction of AND array is depicted in Figure3.It consist of matrix of rows and
columns and number of AND gates. The rows and columns are interconnected
with help of fusible links.
 In the beginning all the links are closed. Selectively some of these links are open
and others are retained. This is called as programming the array. The matrix
connections of two dimensional structures are given to the AND gates. In a row to
connect the desired input to the AND gate only one fuse is left intact. The other
links are open.
 Vertically to the columns the inputs and their compliments are connected (A, A’, B,
B’). This process of programming is carried out till the last row. The equations are
then implemented by an OR array.
 For example if the equation to be implemented is X1= A . B then A is selected on
row1 and B is selected on row2 so AND gate implements A+B. Similarly other
expressions are implemented by using other rows and columns and other AND
gates.

By Dr. Ahuna
 PLDs
The AND Array
13 X = programming to be done

Figure3: Logic diagram of AND array with six rows and four columns
By Dr. Ahuna
 PLDs
The AND Array
14 X = programming to be done

By Dr. Ahuna
 PLDs
The AND Array
15 X = programming to be done

Figure 4: An AND array after programming

By Dr. Ahuna
 PLDs
The AND Array
16
 As discuss earlier the AND array consists of an array of AND gates connected to
programmable matrix with fusible links at each cross point of a row and column.
 The AND array is programmed by blowing the fuses to eliminate the variables and
retain only one connection in a row. Therefore for each i/p to AND gate only one
fuse is left intact in order to connect the desired variable to the gate i/p.
 Again, once the fuse is blown it cannot be reconnected.

By Dr. Ahuna
 PLDs
Types of SPLD
17
 All the programmable basically carry combination of OR array and AND array.
With the help of the links different programming devices are obtain.
 Basically it implements SOP (Sum Of the Products) types expressions.
 Depending upon ability of programming the SPLDs are of the following types:

1. PROM (Programmable Read Only Memory)

2. PLA (Programmable Logic Array)
3. PAL (Programmable Array Logic)
4. GAL (Generic Array Logic)

By Dr. Ahuna
 PLDs
PROM
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Figure 5: Block diagram of PROM

By Dr. Ahuna
 PLDs
PROM
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By Dr. Ahuna
 PLDs
PROM
20

Figure 6: Pin diagram of 28C64 Memory

By Dr. Ahuna
 PLDs
PLA
21 It consists of a programmable AND array and programmable OR array. It is also called FPLA
(field programmable logic array). Because, it is programmed by user.
It is not programmed by manufacturer. E.g. Signetics: 82S100. It was introduced in 1974
having 16 inputs and 8 outputs.
It has 48 AND gates in AND array and 8 OR gates in OR array. It has 2x16x48=1536 fuses in
AND array and 8x48=384 fuses in OR array.

By Dr. Ahuna
 PLDs
PLA
22

Figure 7: Block diagram of PLA

By Dr. Ahuna
 PLDs
PAL
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 It consists of programmable AND array and fixed OR array with output logic. It is
OTP. i.e. one time programmable device. It is implemented by using TTL or ECL
technology.
 Examples: PAL16L8; PAL20L8; PAL12H6; PAL10P8; PAL10L8.

Figure 8: Block diagram of PAL

By Dr. Ahuna
 PLDs
PAL
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Figure 9: Pin Diagram of PAL 16L8

By Dr. Ahuna
 PLDs
The GAL
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 It has reprogrammable AND array and fixed OR array with programmable output
logic. It uses E2CMOS technology or floating gate technology. Therefore it is
generic and so many other PAL like structures can be developed.
 Examples: GAL18V6; GAL16V8C; PALCE20V8
 Note that these ICs have changed the size of the electronic products. Because if the
same circuits are to be realized by using fix function ICs then it takes lot of spaces.
It’s very bulcky.but with PLDs these product is very light in weight.
 Using these technologies custom or semi custom IC’s were manufactured. Such
IC’s are called as ASICs (Application Specific Integrated Circuits).

By Dr. Ahuna
 PLDs
GAL
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Figure 10: Block diagram of GAL

By Dr. Ahuna
 PLDs
ASIC
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 There are many manufacturers of PLDs. So they are available as off the shelf
components. As they are programmable, most logic circuits in digital hardware can
be implemented using them.
 But the problem with these PLDs is that they occupy a lot of chip area. Also the
speed of operation is less because of programmable switches or connections. So
they are costly and they may not give desired performances. In such cases or when
the digital products are required in large numbers, a different approach of ASIC is
taken.
 In this approach the digital products is designed by a chip that implements the
desired logic circuits. Then the appropriate technology is selected. The chip is then
outsourced for manufacturing to a company that has the fabrication facilities. This
chip is then used in digital products for a specific application. Such chips are
called ASICs.

By Dr. Ahuna
 PLDs
ASIC
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Advantages of ASICs:
1. It is designed to optimize the specific task so it gives the best performance.
2. It is possible to put large amount of logic circuitry in a single chip
3. As these ICs are produced in bulk, cost of the manufacture per chip is very low.
So the cost per chip is far less than the fixed function ICs.
4. They can be used in embedded systems.

Disadvantage of ASICs:
 It takes considerably long time to manufacture ASIC or custom chip.

By Dr. Ahuna
 PLDs
ASIC
29 Disadvantage of ASICs
Cost
 ASICs can be expensive to develop, especially for small companies.
 The cost per unit can be high when producing a small number of units.
Development time
 The process of designing and manufacturing an ASIC can take several months or
even years.
 The design flow for ASICs is more complex and time-consuming than for
FPGAs.
Inflexibility
 Once designed and manufactured, ASICs cannot be altered or updated.
 This means that ASICs can become obsolete more quickly, especially in fast-
evolving fields.
When choosing between custom ASICs and off-the-shelf components, it's important
to consider a project's requirements, budget, and timeline.
By Dr. Ahuna
 PLDs
PLD Programming
30
 PLD need to be programmed by an expert designer. He/she needs to know how to
programs these ICs by using one of the hardware description languages (HDLs).
For Fixed function IC, the designer need not to know HDL.
 Logic circuit design for PLDs is entered using computer by two methods.
1. Schematic Entry
2. Text Base Entry

By Dr. Ahuna
 PLDs
PLD Programming:
31
 In schematic entry the software permits the user to enter the symbols to logic
gates, flip flops and also to interconnect them. On the screen, a schematic diagram
similar to logic diagram is seen.
 In text based entry, the software permits the user to enter the design by using a text
of HDL. For this either ABEL (Advanced Boolean Expression Language), CUPL
(Complier for Universal Programmable Logic) , VHDL( Very high Speed
Hardware Description Language) or Verilog can be used as language.
 PLD design is simulated on the screen using one the above techniques. If
simulation works fine then the implementation of the design is done on PLD. This
is done by using an ADDON unit to a computer where the PLD is burnt. Later on
it is used in real products.

By Dr. Ahuna
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By Dr. Ahuna
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Assignment
1) Group yourselves in to four groups
2) Design a digital clock using sequential circuits
3) Prepare a 10-slide Powerpoint presentation of your work for
assessment
4) Prepare a 1-page report on the design process of your digital clock

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Topic 4
Large Scale Integration (LSI) Design
By Dr. Ahuna