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8086 Architecture

The 8086 architecture features a 20-bit address bus and a 16-bit data bus, allowing for a memory capacity of 1MB and supporting pipelining with a 6-byte prefetch queue. It consists of a Bus Interface Unit (BIU) for address generation and control signals, and an Execution Unit (EU) for executing instructions with various registers and flags. The architecture utilizes segment registers for memory segmentation and offset registers to generate physical addresses for data access.

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6 views4 pages

8086 Architecture

The 8086 architecture features a 20-bit address bus and a 16-bit data bus, allowing for a memory capacity of 1MB and supporting pipelining with a 6-byte prefetch queue. It consists of a Bus Interface Unit (BIU) for address generation and control signals, and an Execution Unit (EU) for executing instructions with various registers and flags. The architecture utilizes segment registers for memory segmentation and offset registers to generate physical addresses for data access.

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shreyansm.developer
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We take content rights seriously. If you suspect this is your content, claim it here.
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8086 architecture

FEATURES 8085 8086


Address bus 16 bit address bus 20 bit address bus
Data bus 8 bit data bus 16 bit data bus
Memory capacity 64 KB 1MB
Pipelining Absent Supports pipelining using 6 byte queue
Memory segmentation Absent Segmentation in form of four memory
segments – code, data, extra and stack
Memory banks Absent (continuous memory) Even and odd memory bank(to access
16 bits in one fetch cycle)
IO addresses 8 bit I/O address 8/16 bit I/O address
Operating modes NA Minimum mode and maximum mode
 BUS INTERFACE UNIT
The BIU contains a pre fetch 6 byte queue, a bus controller, segment registers, instruction
pointer and adder

The main purposes of the BIU are:


 To generate 20 bit memory physical address or I/O port number.
 To keep the pre fetch queue filled with instructions and support pipelining.
 To act as a window between the EU and peripherals for data transfer
 To generate and accept the control signals.

 EXECUTION UNIT
The EU contains; an arithmetic and logic unit, flag register, an instruction register, temporary
register (not accessible to the programmer), EU control unit and a register array

The purpose of the EU is to carry out instructions that are fetched from the pre fetch queue.

 The instruction register receives the instructions from the pre fetch queue. From here these
instructions are decoded by the instruction decoder and the decoded information is sent to
control circuit to direct the operation of the execution unit.
 The register (AX, BX, CX, DX ) array holds information temporarily. It also contains
pointers(SP and BP) or index registers(SI and DI) used to address operand data located in the
memory.
 The ALU performs arithmetic and logic operations on memory and or register data
 Flag register

Flag Register is a 16-bit register containing 9 1-bit flags:

* Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to
fit into destination operand. (range -128 to +127 for bytes and -32768 to+32768 for words)
* Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers.
If cleared then the index registers will be auto-incremented.
* Interrupt-enable Flag (IF) - setting this bit enables INTR interrupt.
* Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction, useful for
program debugging
* Sign Flag (SF) - set if the most significant bit of the result is set.
* Zero Flag (ZF) - set if the result is zero.
* Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
* Parity Flag (PF) - set if parity (the number of "1"s) of the result is even.
* Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result
calculation.

All the registers of 8086


To define the position of memory segments, 8086/88 has 4 segments registers
• Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES)
and Stack Segment (SS) register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16 bit address of the starting address of the
corresponding segments.
Offset registers (16 bit registers) are specified below
IP – Instruction pointer
SP – stack pointer
BP – base pointer
SI – source index
DI – destination index
BX – one of the general purpose registers
20 bit physical address is generated by combination and segment register and offset
register
• CS:IP(for accessing instruction bytes)
• SS:SP(for storing and retrieving return address and register values while transferring
control from main program to subroutine)
• SS:BP(for accessing stack randomly)
• DS:BX (for general data access)
• DS:SI (for string and non string operations)
• DS:DI (for other than string operations)
• ES:DI (for string operations)
If DS = 4657 and SI =0004 then 20 bit physical address in 46570+0004 = 46574H
A hexadecimal 0 is attached to the segment register LSB and then segment register is added to
corresponding offset register to generate 20 bit physical address

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