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Microprocessor 8086

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9 views14 pages

Microprocessor 8086

Uploaded by

ayanalikhan1133
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MicroProcessor 8086

MicroProcessor: 8086
• Contain 2 processing units: Bus Interface Unit (BIU) and
the Execution Unit (EU).
• Each has dedicated functions and operate in parallel
• Makes fetching and execution of instructions
independent
• BIU is responsible for performing all the external bus
operations; instruction fetching, read/write data
operands, I/O peripherals
• Bus includes 8 bits bidirectional data bus, and 20 bits
address bus and signals to controls transfers.
MicroProcessor: 8086
• BIU contains the segment registers, the IP, address
generation adder, bus control logic and instruction queue.
• Instruction queue implements parallelism and contains up to 6
bytes of instruction code.
• BIU looks for free bus slot to add instruction to the FIFO queue
• The free bus slots, when both EU and BIU do not require the bus,
are called idle states
• The EU is responsible for decoding and executing instructions
• EU consists of ALU, status and control flags, general purpose
registers.
• EU obtains instructions from FIFO queue and data from register
or memory.
MicroProcessor: 8086
• EU decodes the instructions, generates
data addresses if required, and passes them
to BIU
• EU performs the execution and updates the
flag registers
• EU may have to wait if the instruction queue
is empty
Pointer and Index Registers
• Two pointer (SP & BP) and two index registers (SI &
DI)
• Used as offset addresses to reference 64KB segment
of memory
• Index register used relative to data segment or extra
segment
• Pointer register used relative to stack segment
register
• Values can be read and write through software
• Can only be accessed as word
• To use the addresses the instruction simply specifies the
Pointer and Index Registers
• SP and BP used as offset to current value of SS (SS:SP)
• SP represents the offset of next stack location
• BP is also used relative to SS
• BP is used access data within the stack segment of
memory
• Used in based addressing mode
• BP also used to reference parameters that are
passed to subroutine by way of the stack.
• In this case the subroutine uses based addressing to
access the values of parameters from stack
Pointer and Index Registers
• The index registers hold the offset for DS and ES.
• In indexed addressing the Source Index (SI) register
holds the offset of source operands
• While the Destination Index (DI) holds the offset of
destination operand
• Some of the operation (arithmetic or logical) can be
applied directly on data in memory, instead of
registers
• In this case, index address is used to identify the
operands in memory
Pointer and Index Registers
• The arithmetic operation can be applied directly to
index register
• For example, adding 2 to SI, to point the next word in
memory
Status Register

• 16 bit register, only 9 of its bits are implement


• Six of these bis represent; carry flag (CF), parity flag (PF),
auxiliary carry flag (AF), zero Flag (ZF), sign Flag (SF) and
Overflow Flag (OF)
• The flag represents the conditions that are produced as the
result of execution of on instruction
• CF: is set (1) when there is carry out (or a borrow in) of most
significant bit otherwise reset (0)
• PF: is set when the instruction produces the result with even
parity (even number of 1s) and reset otherwise
• AF: is set when there is carry out (or a borrow in) of lower
nibble to the higher nibble
Status Register
• ZF: is set when the result produced by an instruction in zero
• SF: The MSB of result is copied to SF. Thus, SF is set if result is a
negative number and reset otherwise
• OF: is set when result is out of range
• TF (Trap Flag): when set, a single-step mode is enabled. That is,
after completion of single instruction the program jumps to a
special routine, to determine the effect of instruction (debugging).
• IF (interrupt Flag): when set the maskable interrupts will be
recognized otherwise it will ignore the interrupts
• DF (Direction Flag): determins the direction in which string
operations will occur. When set the string data will be transferred
from higher address to lower address
• The user software can read write some of the flags. For example, Cf,
DF and IF.
Generating Memory Addresses
• A segment base and offset describe a logical address
• Both the base and offset quantities are 16 bit
• However, the physical address is 20 bit
• Generating the physical address involves combining offset and base
values
• The source of offset depends upon which type of memory reference is
taking place
• It can be BP, SP, BX, SI, DI OR IP
• While the segment resisters are; CS, DS, SS or ES.
• e.g., when fetching instruction, the segment register is CS while the
offset is IP.
• When pushing values in stack, segment register is SS and offset is SP,
SS:SP
Generating Memory Addresses
• The segment registers represent
the starting location of the
64KB segment in memory
• That is, the lowest address in
the segment
• The lowest byte in a segment is
offset 0000H and highest
address byte has offset of
FFFFH
Generating Memory Addresses
• The value in segment register is shifted 4 bits to left, filling 4 zeros in
LSB
• The 16-bit offset is added to shifted segment register value to produce
20 bit physical address
• If the segment value is 1234H, then after shifting it will become 12340H
• If the offset is 0022H, then the physical address will be: 12362H
Generating Memory Addresses
Q: what would be the offset required to map to
physical address location 002C3H if the contents of the
corresponding segment register are 002AH?
Sol:
Shifting the segment bits: 002A0H
Now subtracting: 002C3H – 002A0H = 0023H

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