=D- =D- ARITHMETIC-LOGIC UNITS TThe arithmetic-logic unit (ALU) is the number-crunching part of a computer. This means not only arithmetic opera- tions but logic as well (OR, AND, Nor, and so forth), In this chapter you will learn how the ALU adds and subtracts binary numbers. Later chapters will discuss the logic ‘operations. 6-1 BINARY ADDITION ALUs don’t process decimal numbers; they process binary numbers. Before you can understand the circuits inside an ALU, you must learn how to add binary numbers. There are five basic cases that must be understood before Case 1 ‘When no pebbles are added to no pebbles, the total is no pebbles, As a word equation, None + none = none With binary numbers, this equation is written as o+0=0 Case 2 If no pebbles are added to one pebble, the total is one pebble: None + @=@ In terms of binary numbers, o+iet Case 3 Addition is commutative. This means you can transpose the numbers of the preceding case to get @ + none = @ l+o=1 Case 4 Next, one pebble added to one pebble gi ives two pebbles: Asa binary equation 1+1=10 To avoid confusion with decimal numbers, read this as ‘one plus one equals one-rero."" An alternative way of the equation is “one plus one equals zero, carry Case 5 One pebble plus one pebble plus one pebble gives a total of three pebbles: ere+e- ‘The binary equation is leis Read this as “one plus one plus one equals one-one."” Allernatively, “one plus one plus one equals one, carry 79Rules to Remember ‘The foregoing cases are all you need for more complicated binary addition. Therefore, memorize these five rules: oF (6-1) oF (62) 1+ 63) 1+ (6-4) 41+ (5) Larger Binary Numbers Column-by-column addition applies to binary numbers as well as decimal. For example, suppose you have this problem in binary addition: L100 + 11010 ‘Start with the least significant column to get 11100 + 11010 0 Here, 0 + 0 gives 0. Next, add the bits of the second column as follows: 11100 + 1010 10 ‘This time, O + 1 results in 1 The third column gives 11100 + 11010 110 In this case, 1 + 0 produces 1 The fourth column results in 11100 + 11010 0110 (carry 1) AAs you see, 1 + 1 equals 0 with a carry of 1 Finally, the last column gives 11100 + 11010 10110 Here, 1 + 1+ 1 (carry) produces 11, recorded as 1 with 4 cary to the next higher column. BO digtat computer Electronics EXAMPLE 6-1 ‘Add the binary numbers 01010111 and 00110101, SOLUTION ‘This is the problem 1010111 00110101, If you add the bits column by column as previously demonstrated, you will get o1o101n1 400110101 10001100 Expressed in hexadecimal numbers, the foregoing addi- tion is 37 435 8c For clarity, we can use subscripts: Shs 35) 8Ci6 In microprocessor work, it is more convenient t0 use the letter H to signify hexadecimal numbers. In other words, the usual way £0 express the foregoing addition is STH + 35H 8CH 6-2 BINARY SUBTRACTION To subtract binary numbers, we need to discuss four cases, Case 1 o- Case 2: V- Case 3 1 Case 4: 10 - ‘The last result represents which makes sense‘To subtract larger binary numbers, subtract column by column, borrowing from the next higher column when necessary. For instance, in subtracting 101 from 111, proceed like this: 7 11 =s =101 2 010 Starting on the right, 1 — 1 gives 0; then, 1 — 0 is 1s finally, 1 — 1 is 0 Here is another example: subtract 1010 from L101 B 1101 =10 = 1010 3 Con In the least significant column, 1 — 0 is I. In the second column, we have to borrow from the next higher column: then, 10 — 1 is 1. In the third column, 0 (after borrow) 0 is 0. In the fourth column, 1 ~ 1 = 0. Direct subtraction like the foregoing has been used in computers; however, itis possible to subtract in a different ‘way. Later sections of this chapter wll show you how 6-3 HALF-ADDERS Figure 6-1 is a half-adder, a logie circuit that adds 2 bits Notice the outputs: SUM and CARRY. The boolean equations for these outputs are SUM =A@B (6-6) CARRY = AB ©) ‘The SUM output is A xOR B: the CARRY output is A AND. B, Therefore, SUM is a 1 when A and B are different; CARRY is a1 when A and B are Is. ‘Table 6-1 summarizes the operation. When A and B are Os, the SUM is 0 with a CARRY of 0. When A is and B is, the SUM is 1 with a CARRY of 0. When A is | and B is 0, the SUM equals 1 with CARRY of 0. Finally, when A is 1 and B is 1, the SUM is O with a CARRY of 1 ‘The logic circuit of Fig. 6-1 does electronically what we do mentally when we add 2 bits. Applications for the half= adder are limited. What we need is a circuit that ean add 3 bits at atime. canny C | I Fig, 6-1 Hatf-adder. 1, HALF-ADDER AB | CARRY SUM_ 0 0 0 0 oot 0 o1 10 oo1 ma 10 6-4 FULL ADDERS Figure 6-2 shows a full adder, a logie circuit that can add 3 bits. Again there are two outputs, SUM and CARRY. The boolean equations are SUM = A@B@C (68) CARRY = AB + AC + BC (6-9) ee CO Fig. 6-2 Full adder, In this case, SUM equals A xoR B xOR C; CARRY equals AB og AC 08 BC. Therefore, SUM is | when the number of input Is is odd; CARRY is a 1 when two or more inputs are Is, Table 6-2 summarizes the circuit action. A, B, and C are the bits being added. If you check each entry, you will see that the circuit adds 3 bits ata time and comes up with the correct answer. ‘TABLE 6-2, FULL ADDER ABC _| CARRY sum 20 0) Oat 0 1 to 0 1 iat 1 o 02. 10) 0 1 Oat 1 0 1 1 0 1 0 rai L 1 Chapter 6 ArithmeticLogic Units 81Here’s the point, The circuitof Fig. 6-2 does electronically what we do mentally when we add 3 bits. The full adder can be cascaded to add large binary numbers. The next section tells you how 6-5 BINARY ADDERS Figure 6-3 shows a binary adder, a logic circuit that can add (0 binary numbers, The block on the right (labeled HA) represents a half-adder. The inputs are Ay and By; the ‘outputs are Sy (SUM) and C, (CARRY). All other blocks are full adders (abbreviated FA). Each of these full adders has three inputs (4,, B,, and C,) and two outputs. ‘The circuit adds two binary numbers. In other words, it carries out the following addition: Here’s an example. Suppose A = 1100 and B = 1001 ‘Then the problem is 1100 + 1001 Figure 6-4 shows the binary adder with the same inputs, 1100 and 1001. The half-adder produces a sum of 1 and carry of 0, the first full adder produces a sum of 0 and a carry of 0, the second full adder produces a sum of 1 and a cary of O, and the third full adder produces a sum of 0 and a carry of 1. The overall output is 10101, the same answer we would get with pencil and paper. By using more full adders, we can build binary adders of any length, For example, to add 16-bit numbers, we need I half-adder and 15 full adders. From now on, we will use the abbreviated symbol of Fig. 6-5 to represent @ binary adder of any length. Notice the solid arrows, the standard way to indicate words in motion. In Fig. 6-5 words A and B are added to get a sum of § plus a final carry. ty ty canny «— cer U Fig. 65 Symbol for binary adder. EXAMPLE 6-2 Find the output in Fig. 6-5 if the two input words are ‘A = 0000 0001 0000 1100, B = 0000 00000100 1001 r* | T 7 Fig, 63 Binary addor Fig, 64 Adding 12 and 9 to get 21 82 digital Computer ElectronicsSOLUTION ‘The binary adder adds the two inputs to get (0000 0001 0000 1100 + 0000 0000 0100 1001 ‘0000 0001 O101 O101 In hexadecimal form, the foregoing addition is 10CH + 009H O1SSH 6-6 SIGNED BINARY NUMBERS ‘The negative decimal numbers are —1, -2, ~3, and so ‘on. One way to code these as binary numbers is to convert the magnitude (1, 2, 3, . . .) to its binary equivalent and prefix the sign. With this approach, —1, —2, and —3 becomes —001, —010, and —011. It's customary to use (O for the + sign and 1 for the ~ sign. Therefore, 001, =010, and ~O11 are coded as 1001, 1010, and 1011 ‘The foregoing numbers have the sign bit followed by the magnitude bits. Numbers in this form are called signed binary numbers or sign-magnitude numbers. For larger decimal numbers you need more than 4 bits. But the idea is still the same: the leading bit represents the sign and the remaining bits stand for the magnitude. EXAMPLE 6-3 Express each of the following as 16-bit signed binary numbers. b. 4. SOLUTION a, +7 = 0000 0000 0000 0111 b. =7 = 1000 0000 0000 0111 ©. #25 = 0000 0000 0001 1001 4, =25 = 1000 0000 0001 1001 No subscripts are used in these equations because it's clear from the context that decimal numbers are being expressed in binary form. Nevertheless, you can use subscripts if you prefer. The first equation can be written as +10 (0000 0000 0000 01113 the next equation as = 1000 0000 0000 0111; and so forth EXAMPLE 6-4 Convert the following signed binary numbers to decimal numbers: ‘2, 0000 0000 0000 1001 . 1000 0000 0000 1111 c. 1000 0000 0011 0000 d. 0000 0000 1010 0101 SOLUTION ‘As usual, the leading bit gives the sign and the remaining bits give the magnitude. a. 0000 0000 0000 1001 = +9 b. 1000 0000 0000 1111 = —15 ©. 1000 0000 0011 0000 = 48 d. 0000 0000 1010 0101 = +165 6-7 2's COMPLEMENT Sign-magnitude numbers are easy to understand, but they require to0 much hardware for addition and subtraction. This has led to the widespread use of complements for binary arithmetic, Definition Recall that a high invert signal to a controlled inverter produces the 1’s complement. For instance, if A=olll (6-10a) the 1s complement is 1000 (6-105) ‘The 2°s complement is defined as the new word obtained by adding 1 to 1's complement. As an equation, re Re 1) where A’ = 2's complement K = I's complement Here are some examples. If Aoi Chapter 6 ArithmeticLogic Units 83the 1’s complement is 1000 and the 2's complement is A’ = 1001 In terms of a binary odometer, the 2°s complement is the next reading after the 1's complement. Another example, If A 000 1000 then Holl and = 1111 1000 Double Complement If you take the 2's complement twice, you get the original word back. For instance, if A= ol the 2's complement is A’ = 1001 If you take the 2°s complement of this, you get "= 0111 which is the original word. In general, this means that Ava (612) Read this as “the double complement of A equals A. Because of this property, the 2's complement of a binary number is equivalent to the negative of a decimal number This idea is explained in the following discussion, nor mom = o ° Fig, 6-6 Decimal numbers and odometer readings 84 Digital Computer Electronics Back to the Odometer Chapter 1 used an odometer to introduce binary numbers The discussion was about positive numbers only. But odometer readings can also indicate negative numbers Here's how. If a car has a binary odometer, all bits eventually reset to Os. A few readings before and after a complete reset look like this: Ho 110 mt 0000 (nes 001 010 oon 1) 1101 is the reading 3 miles before reset, 1110 occurs 2 miles before reset. and 1111 indicates | mile before reset. Then, 0001 is the reading 1 mile after reset, 0010 occurs 2 miles after reset, and 0011 indicates 3 miles after reset. ‘Before’’ and “after” are synonymous with “negative” and “positive.”” Figure 646 illustrates this idea with the number line learned in basic algebra: 0 marks the origin, positive decimal numbers are on the right, and negative decimal numbers are on the left. The odometer readings are the binary equivalent of positive and negative decimal ‘numbers: 1101 is the binary equivalent of ~3, 1110 stands for —2, IL11 for = 1; 0000 for 0; 0001 for +1; 0010 for +2, and OO1L for +3. ‘The odometer readings of Fig. 6-6 demonstrate how positive and negative numbers are stored in a typical ‘microcomputer. Positive decimal numbers are expressed in sign-magnitude form, but negative decimal numbers are represented as 2's complements. As before, positive num- bers have a leading sign bit of 0, and negative numbers hhave a leading sign bit of | 2's Complement Same as Decimal Sign Change Taking the 2's complement of a binary number is the same as changing the sign of the equivalent decimal number. For example, if A= 0001 (+1 in Fig. 6-6) 00010010 ont sataking the 2's complement gives A'S IIL (1 in Fig. 66) Similarly, if A= 0010 (42 in Fig, 66) then the 2's complement is Av = 1110 (~2in Fig. 66) Again, if A= 001 (43 in Fig. 66) the 2's complement is MOL (—3 in Fig. 6-6) ‘The same principle applies to binary numbers of any length: taking the 2's complement of any binary number is the same as changing the sign of the equivalent decimal ‘number, As will be shown later, this property allows us to use a binary adder for both addition and subtraction. Summary Here are the main things to remember about 2's complement representation: 1. The leading bit isthe sign bit; 0 for plus, 1 for minus. 2. Positive decimal numbers are in sign-magnitude form. 3. Negative decimal numbers are in 2's-complement form. EXAMPLE 6-5 ‘What is the 2's complement of this word? ‘A = 0011 0101 1001 1100 SOLUTION The 2's complement is A’ = 1100 1010 0110 0100 EXAMPLE 6-6 What is the binary form of +5 and ~5 in 2°s-complement representation? Express the answers as 8-bit numbers, SOLUTION Decimal +5 is expressed in sign-magnitude form: 5 = 0000 0101 On the other hand, ~5 appears as the 2's complement: 111 1011 EXAMPLE 6-7 What is the 2°s-complement representation of —24 in a 16-bit microcomputer? SOLUTION Start with the positive form: 24 = 0000 0000 0001 1000 ‘Then take the 2's complement to get the negative form =24 = LLL TILL 1110 1000 EXAMPLE 6-8 ‘What decimal number does this represent in 2's representation? ‘complement 1111 0001 SOLUTION Start by taking the 2's complement to get (0000 1111 This represents +15. Therefore, the original number is 1111 000 -15 6-8 2's-COMPLEMENT ADDER- SUBTRACTER Early computers used signed binary for both positive and negative numbers. This led to complicated arithmetic cir- cuits. Then, engineers discovered that the 2's-complement representation could greatly simplify arithmetic hardware. Chapter 6 Arithmetic-Logle Units 85This is why 2's-complement adder-subtracters are now the ‘most widely used arithmetic circuits. Addition Figure 6-7 shows @ 2's-complement adder-subtracter, logic circuit that can add or subtract binary numbers. Here's hhow it works. When SUB is low, the B bits pass through the controlled inverter without inversion. Therefore, the full adders produce the sum (6-13) Incidentally, as indicated in Fig. 6-7, the final CARRY is not used. This is because S; is the sign bit and S; to 5, are the numerical bits. The final CARRY therefore has no significance at this time. Subtraction When SUB is high, the controlled inverter produces the 1's complement. Furthermore, the high SUB adds a I to the frst full alder. This adlton of 1 to the 1's complement forms the 2's complement of B. In other words, the controlled inverter produces B, and adding 1 results in B’ The output of the ull adders is S=A+B 6-14) which is equivalent to S=A-B (15) because the 2's complement is equivalent to a sign change. EXAMPLE 6-9 ‘A 7483 is a TTL circuit with four full adders. This means that it can add nibbles (4-bit numbers) Figure 6-8 shows a TTL adder-subtracter. The CARRY cout (pin 14) of the least significant nibble is used as the CARRY in (pin 13) for the most significant nibble. This allows the two 7483s to add 8-bit numbers. Two 7486s form the controlled inverter needed for subtraction sue canny, ‘ot FA FA oe FA FA % Fig. 6-7 A 2's-complement adser-suberacter. 1 [a fsfs[efuolizfia ig. 68 TTL adder-subsracter. 86 digital Computer Electronics Ay Bs BB suSuppose the circuit has these inputs ‘A = 0001 1000, B = 0001 0000 If SUB = 0, what is the output of the adder-subtracter? SOLUTION When SUB is 0, the adder-subtracter adds the (wo inputs as follows: 0001 1000 +0001 0000 ‘0010 1000 ‘Therefore, the output is 0010 1000, Notice that the decimal ‘equivalent of the foregoing addition is 4 tls 20 EXAMPLE 6-10 Ropeat the preceding example for SUB = 1 SOLUTION When SUB is 1, the adder-subtracter subtracts the inputs by adding the 2's complement as follows: 0001 1000 + 1111 0000 ‘0000 1000 The decimal equivalent is EXAMPLE 6-11 In Fig. 6-8, what are the largest positive and negative sums we can get? SOLUTION ‘The largest positive output is oui which represents decimal + 127. The largest negative output 1000 0000 which represents ~ 128. With 8 bits, therefore, all answers must lic between ~128 and +127. If you try to add ‘numbers with a sum outside this range, you get an overflow into the sign-bit position, causing an error. Chapter 12 discusses the overflow problem in more detail All you have to remember for now is that an overfiow or error will occur if the true sum lies outside the range of 28 to +127 GLOSSARY ALU Arithmetic-logie unit. The ALU carries out arith- metic and logie operations, binary adder Jogic circuit that can add two binary numbers. full adder A \ogic circiut that can add 3 bits. hhalf-adder A logic circuit that adds 2 bits. overflow In 2's-complement representation, a carry into the sign-bit position, which results in an error. For an 8 bit adder-substracter, the true sum must lic between ~ 128 and +127 to avoid overfiow signed binary A system in which the leading bit represents the sign and the remaining bits the magnitude of the number. Also called sign magnitude 2's complement The new number you get when you take the 1’s complement and then add 1 Chapter 6 Arithmetic-Logle Units 87SELF-TESTING REVIEW Read each of the following and provide the missing words, Answers appear at the beginning of the next question, take the complement, then add 6 Gs Ps, 1) Ifyou take the 2's complement twice, Be ALU cain tne and ———$ 9 ei ina) wun tsk os of somber thr tan deine! mame this propery taking the Sera an i te can bits, A 2 inuy nber sae hanging hes full adder adds — - bits, producing a SUM at fates ring 4. Gro ina meceapter positive number oe re a tee sented in-form and negative numbers in 1¢ 7483 is a TTL binary adder. It can add two 4-bi ee ay abe DMM ate can aad oo (signmagninae, sign) A 2s-somplement addersib- 4. (io) With signed binary numbers, so known as tet can aor ubactbnary numer, Sin sign-magnitide numbers, the leading bit stands for SS] —— the and the remaining bits forthe rumbers, and 2's complements stand for Gecimal numbers. You can tell one fom the other by 5. Gign, magnitude) Signed binary numbers require too the leading it, which represents the ——— ee eee in nan eee (positive, negav, sign) With 2'scomplement repre sateen rpc Renate nus To ae Sniton and an 8 alder sb nooner i the 2's complement of a binary number, you first sete Ache Sai Oe te ee PROBLEMS 6-1. Add these Sit numbers 65. Conver each of those sigmmagnitude numbers 0 3.0001 0000 and 0000 1000 its decimal equivalent 0001 1900 and 0000 1100 2, 0001 1110 €. 0001 1100 and 0000 1110 1000 0111 &. 0010 1000 and 0011 1011 <. 1001 1100 ‘Aller you have each binary sum, conver it to 3.0011 0001 hexadecimal frm 66. The following hexadecimal numbers represent 6-2, Add these 16-bit numbers sign-magntde numbers. Convert each tis deci- 1000 0001 1100 1001 ae + 0011 0011 0001 0111 oa Express the answor in hexadecimal form ©. TFA 6-3. In each ofthe following, conver to binary to do a. FH the addition, then conver the answer back to 6-7. Find the 2° complements hexadecimal: a. 0000 0111 a. 2CH + FH =? bona b. SEH + 1AH =? ein Hot ©. 3B + 6DH =? 4. 1110 0001 @. ASH + 2CH =? Express your answers in hexadecimal form, 6-4. Convert each ofthe following decimal numbers to 68, Convert each ofthe following 0 binary. Then an B.hitsign- magnitude number: take the 2's complement 2427 a 4CH b. -27 b. 8H e. +80 ©. CBH a 80 a. FH ‘After you have the sign-magnitade numbers conver thom to hexadecimal form BB _igitat computer ElectronicsAy Ag Ag Aa 8 8% 5 Ay Ap Ay Ap 8 BB su 1 [2 fefs[ofuofrefa 1 Je [as [o frolie)is 1486 7498 5 % Se Se res oy a Fig. 69 After you have the 2's complements, convert them high SUB? Express your final answers in bexa- to hexadecimal form decimal form, 6-9, An 8:bit microprocessor uses 2's-complement rep- 6-12. In Fig. 6-9 which of the following inputs cause an resentation. How do the following decimal num- overflow when SUB is low? bers appear: a. 2DH and 4BH a -19 b. SPH and C3H b. 48, c. SEH and BRH e437 d. 23H and 14H a 33 6-13, Why are applications for the half-adder limited, Express your answers in binary and hexadecimal what does the full adder do which makes it more form. useful than the half-adder, and what can be done 6-10. The output of an ALU is BEH, What decimal with a full adder as a result of this feature? umber does this represent in 2's-complement 614, Since sign-magnitude numbers are fairly easy to representation? understand, why has the 2°s-complement system 6-11. Suppose the inputs to Fig. 6-9 are A = 3CH and become so widespread”? B = SFH, What is the output for a low SUB? A Chapter 6 Arithmetic-Logic Unis 89