Digital Systems Design Arithmetic Circuits

6 Arithmetic Circuits
In computers, arithmetic computations such as binary addition and subtraction are done in arithmetic logic unit (ALU)
that consists of logic gates and flip-flops. Logic gates perform the arithmetic operation while the flip-flops (i.e. register and
accumulator) are used as temporary memory storage (something like a scratch pad that we use to perform mathematical
computation). We will look at adder and subtractor circuits in this chapter.

6.1 Half adder

Consider adding two bits, A0 and B0 to give sum Σ0 and carry-out, C1. Table 6.1 shows the possible combinations that
can take place.

Table 6.1: Half adder combination

A0 B0 C1 Σ

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A0 Σ0
HA
B0 C1

Figure 6.1: Half adder (HA) symbol.

Using K-maps as shown in Figure 6.2, we can obtain the logic expressions for Σ0 and C1. It can be seen that for Σ0, it is
not possible to simplify the expression as no looping is possible and the expression is

Σ 0 = A0 B0 + A0 B0 .

Since this is XOR expression (see Section 3.5), it can also be expressed as

Σ 0 = A0 ⊕ B0 .

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Digital Systems Design Arithmetic Circuits

Similarly, the expression for C1 is

C1 = A0 B0 .

Figure 6.2: Half adder K-maps for (a) Σ0 (b) C1.

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Digital Systems Design Arithmetic Circuits

The half-adder logic circuit is shown in Figure 6.3.

A0
Σ0
B0

C1

Figure 6.3: Half adder logic circuit.

6.2 Full adder

Very often when adding two bits, A0 and B0 to give sum Σ0 and carry-out C1, there can be another input, carry-in C0
resulting from addition of previous bits. The possible combinations for a full adder are shown in Table 6.2 where it can
be seen that the three binary inputs, A0, B0 and C0 add to give the two binary outputs, Σ0 and C1. Full adder symbol is
shown in Figure 6.4.

Table 6.2: Full adder combinations

A0 Σ0
B0 FA
C0 C1

Figure 6.4: Full adder (FA) symbol.

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Digital Systems Design Arithmetic Circuits

K-maps for the two full adder outputs are shown in Figure 6.5. For Σ0, no looping is possible and the expression is

Σ 0 = A0 B0 C 0 + A0 B0 C 0 + A0 B0 C 0 + A0 B0 C 0

Σ 0 = C 0 ( A0 B0 + A0 B0 ) + C 0 ( A0 B0 + A0 B0 )

which can also be expressed in simpler form using XOR and XNOR expressions as ( A0 B0 + A0 B0 ) = A0 ⊕ B0 and
( A0 B0 + A0 B0 ) = A0 ⊕ B0 to give

Σ 0 = C o ( A0 ⊕ B0 ) + C 0 ( A0 ⊕ B0 ) .

We can actually simplify this further by allowing X = A0 ⊕ B0 :

Σ 0 = C0 X + C0 X .

Further simplification can be made using an XOR expression to give

Σ 0 = X ⊕ C0

Σ 0 = A0 ⊕ B0 ⊕ C 0

For C1, three pair loops are possible resulting in

C1 = A0 B0 + A0 C 0 + B0 C o .

(a)

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Digital Systems Design Arithmetic Circuits

(b)

Figure 6.5: Full adder K-maps for (a) Σ0 (b) C1.

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Digital Systems Design Arithmetic Circuits

The full adder circuitry is shown in Figure 6.6.

Figure 6.6: Full adder logic circuitry.

It should be obvious that a half-adder can be constructed using a full adder by setting C0=0. This is illustrated in Figure 6.7.

A0 Σ0
B0 FA
C0=0 C1

Figure 6.7: Half adder design using full adder.

6.3 Parallel adder

Usually, addition is done on a number of bits using a parallel adder that consists of several full adders as shown in Figure
6.8 for addition of two 3 bit numbers.


C2 C1 C0=0

FA2 FA1 FA0

A2 B2 A1 B1 A0 B0
C3 Σ2 Σ1 Σ0

Figure 6.8: Parallel adder layout for addition of two 3 bit numbers.

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Digital Systems Design Arithmetic Circuits

As an example, consider adding A = 1 1 1 with B = 1 0 1 as depicted in Figure 6.9 to give sum = 1 0 0 and final carry of 1.

C2=1 C1=1 C0=0

FA2 FA1 FA0

A2=1 B2=1 A1=1 B1=0 A0=1 B0=1

C3=1 Σ2=1 Σ1=0 Σ0=0

Figure 6.9: Parallel addition example of two 3 bit numbers.

6.4 Parallel addition using integrated circuits

Parallel adders in integrated circuits (IC) form are available such as the four bit TTL 74LS283 as shown in Figure 6.10
(with pin configurations). Such adders can be cascaded to add more bits. For example, two 74LS283 ICs can be used to add
two 8 bit numbers as illustrated in Figure 6.11 (pin layout has been modified for ease of understanding, the actual layout
is as shown in Figure 6.10). The two numbers: A0, A1, A2, A3, A4, A5, A7 and B0, B1, B2, B3, B4, B5, B7 are added together
with carry input C0 to give sum S0, S1, S2, S3, S4, S5, S7 and carry out C8. The carry out from the first IC, C4 is passed as the
carry input to the second IC.

Vcc B2 A2 Σ2 A3 B3 Σ3 C3

16 15 14 13 12 11 10 9

74LS283

1 2 3 4 5 6 7 8

Σ1 B1 A1 Σ0 A0 B0 C0 GND

Figure 6.10: Four bit adder IC, 74LS283 showing pin configurations.

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93
Digital Systems Design Arithmetic Circuits

A7 A6 A5 A4 A3 A2 A1 A0

C8 C4
74LS283 74LS283 C0

Σ7 Σ6 Σ5 Σ4 B7 B6 B5 B4 Σ3 Σ2 Σ1 Σ0 B3 B2 B1 B0

Figure 6.11: Cascading two 74LS283 to add 8 bit numbers.

6.5 Parallel subtraction

Consider a simple subtraction problem: 6 - 4 = 2. In binary, this will be 0110 – 0100 = 0010. Subtraction in binary can
be performed through addition by converting the number to be subtracted (i.e. the subtrahend) to 2’s complement form
and adding to the minued9.

9 In the example, 6 – 2 = 4, 6 is the minued and 2 is the subtrahend.

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Digital Systems Design Arithmetic Circuits

6.5.1 2’s complement

A binary number can be converted to 2’s complement simply by performing 1’s complement (i.e. inverting) each bit and
then adding 1 to the inverted bits. Any carry from this operation should be discarded. For example, 2’s complement of
4 in binary is

4 in binary → 0100

1’s complement of 4 → 1011

2’s complement of 4 → 1100

Now, 6 - 4 can be represented in binary as shown in Figure 6.12. The carry is discarded to give the correct answer of 2.

Figure 6.12: Subtracting two numbers using 2’s complement method for subtrahend.

It should be obvious that an adder can also function as subtractor with additional gates. For example, the full adder shown
in Figure 6.4 can be used to design a subtractor by inverting B0 and setting C0=1 (both these actions will result in 2’s
complement form for B0) as shown in Figure 6.13. Similar to parallel adders, parallel subtractors can be designed using
several full adders as shown in Figure 6.14.

A0 Σ0
B0 FA
C0=1 C1

Figure 6.13: A full adder used as subtractor.

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Digital Systems Design Arithmetic Circuits

C2 C1 C0=1

FA2 FA1 FA0

A2 A1 A0
C3 Σ2 Σ1 Σ0
B2 B1 B0

Figure 6.14: Designing a parallel subtractor using several full adders.

Using the example in Figure 6.12, 74LS283 can be modified to act as subtractor as shown in Figure 6.15. The minued is
represented by A0, A1, A2, A3 and the inverters convert the subtrahend (B0, B1, B2, B3) to 1’s complement and C0 is set to
1 to convert this 1’s complement number to 2’s complement. The outputs (Σ0, Σ1, Σ2, Σ3) denote the correct answer as 4
and the carry out, C4 = 1 is discarded.

A3 A2 A1 A0

0 1 1 0

1 1
C4 74LS283 C0
(discarded)

1 0 1 1

0 0 1 0
Σ3 Σ2 Σ1 Σ0 0 1 0 0
B3 B2 B1 B0

Figure 6.15: Using 74LS283 as subtractor.

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Digital Systems Design Arithmetic Circuits

6.5.2 Dual adder/subtractor

Replacing the inverters in Figure 6.15 with XOR gates will result in a dual mode adder/subtractor circuit. This is illustrated
in Figure 6.16. When the control input is 1, the circuit acts as a subtractor and when the control input is 0, it acts as an
adder. For example, when B0=1 and control input=1 (during subtraction), the output of XOR is 0, i.e. the XOR gate acts as
an inverter to give 1’s complement and C0=1 to give 2’s complement. When B0=1 and control input=0 (during addition),
C0=0 and the output of XOR is 1, i.e. the XOR gate acts just as a buffer without changing the logic value.

A3 A2 A1 A0

C0
C4 74LS283

Σ3 Σ2 Σ1 Σ0 B3 B2 B1 B0

Control
input

Figure 6.16: Using 74LS283 in dual mode: adder/subtractor.

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