CMOS Fabrication Using Silicon-On-Insulator (SOI)

Technology
Silicon-on-Insulator (SOI) CMOS technology is an advanced fabrication
technique that provides several advantages over conventional bulk CMOS.
Instead of fabricating transistors on a silicon substrate, SOI builds them on a
thin silicon layer separated from the substrate by an insulating layer (such as
sapphire or SiO₂). This reduces parasitic capacitance, improves performance,
and eliminates latch-up issues.

Step-by-Step CMOS Fabrication Using SOI Technology

1. SOI Substrate Preparation
 A thin film (7–8 µm) of lightly doped n-type silicon is grown over an insulating layer (such
as sapphire or SiO₂).
 The insulating layer electrically isolates the transistors, reducing parasitic capacitances and
improving speed.

2. Definition of Silicon Islands

 A photoresist layer is deposited on the silicon film, and photolithography is used to define
the regions (islands) where transistors will be formed.
 An anisotropic etch is performed, removing the unwanted silicon and leaving behind isolated
silicon "islands" on the insulator.
 These islands serve as the active regions for NMOS and PMOS transistors.
3. Well Formation
p-Islands (for NMOS transistors)
 A photoresist mask covers regions where p-channel devices will be placed.
 Boron (p-type dopant) is implanted in the exposed silicon regions to create p-islands.
 These p-islands will serve as the wells for NMOS transistors.
n-Islands (for PMOS transistors)
 A photoresist mask now covers the p-islands.
 Phosphorus (n-type dopant) is implanted in the exposed silicon regions to form n-islands.
 These n-islands will serve as the wells for PMOS transistors.

4. Gate Oxide Growth

 A thin oxide layer (500–600 Å thick) is grown over the entire silicon surface via thermal
oxidation.
 This insulating layer separates the gate terminal from the underlying silicon channel.
5. Polysilicon Deposition and Patterning
 A polysilicon layer is deposited over the gate oxide.
 The polysilicon is doped with phosphorus to reduce resistivity.
 Photolithography and etching are used to define the polysilicon gate structures over the
silicon islands

6. Formation of Source and Drain Regions

For NMOS Transistors (in p-islands)
 A photoresist mask covers PMOS regions.
 Phosphorus (n-type dopant) is implanted into the exposed p-islands, forming the n+ source
and drain regions.
 The polysilicon gate blocks phosphorus from the gate region, preventing doping
underneath the gate.
For PMOS Transistors (in n-islands)
 A photoresist mask covers NMOS regions.
 Boron (p-type dopant) is implanted into the exposed n-islands, forming the p+ source and
drain regions.
 The polysilicon gate blocks boron from the gate region, preventing doping underneath the
gate.


7. Deposition of Insulating Layer
 A silicon dioxide (SiO₂) or phosphorus glass is deposited over the wafer as an insulating
layer.
 Contact holes are etched at predefined locations to expose the source, drain, and gate
terminals.

8. Metal Deposition and Patterning

 A thin layer of aluminium is deposited over the entire wafer.
 Photolithography and etching define the metal interconnections.

9. Final Passivation and Bonding Pad Formation

 A final passivation layer (phosphorus glass) is deposited over the entire wafer to protect
the circuitry.
 Openings are etched to expose the bonding pads, which allow the chip to connect with
external circuits.

Advantages of SOI Technology

 No well regions required, allowing denser circuits and direct n-to-p connections.
 Low capacitances, enabling very fast circuits.
 No field inversion issues, as the insulating substrate prevents unwanted conduction paths.
 No latch-up problems, due to isolation of n- and p-transistors by the insulating layer.
 No body effect, since the substrate does not conduct.
 Enhanced radiation tolerance, making SOI ideal for aerospace and radiation-sensitive
applications.
Disadvantages of SOI Technology
 No substrate diodes, making input protection more difficult.
 Lower device gain, requiring larger I/O structures.
 High cost, as single-crystal sapphire and spinel substrates are expensive.
 Less developed processing techniques, compared to bulk silicon.

SOI Technologies

1. SOS (Silicon on Sapphire)

 The topmost silicon layer is directly grown on a sapphire insulator.
 Sapphire (Al₂O₃) provides electrical isolation, reducing parasitic capacitance.
 Homeoepitaxy is required, meaning the silicon must be oriented appropriately.
 Drawback: Low electron mobility in SOS MOSFETs (230-250 cm²/V·s).
2. SIMOX (Separation by Implanted Oxygen)
 Oxygen ions are implanted into a silicon wafer at high energy (120-200 keV).
 The wafer is annealed at >1300°C to form a buried oxide (BOX) layer.
 Typical BOX thickness: 100, 200, or 400 nm.
 SOI film thickness varies between 50-240 nm.
 There are two essential stages of the process: ion implantation and annealing.
 In the implantation stage, oxygen ions are implanted in the silicon wafer and react with the
silicon to form silicon dioxide precipitates. However, the implantation causes considerable
damage to the wafer and the layer of silicon dioxide precipitates is not continuous.
 Thus high-temperature annealing helps repair the damage and form the oxide precipitates into
a continuous layer. Now the silicon's quality is restored and the buried oxide (BOX) layer can
act as a highly effective insulator.

3. BESOI (Bond and Etch-back SOI)

 By using bonding chemistry between silicon (Si) and silicon dioxide(SiO2) or between SiO2
and SiO2 effectively, two Si wafers are tightly bonded with a SiO2 layer as an insulator inside
the bonded pair. After one side of the Si bulk is thinned down properly with a desired active
Si layer thickness, bonded SOI wafers are obtained.

 The fabrication process is accomplished by three basic steps.

 The first step is to mate a thermally oxidized wafer on a non-oxidized wafer at room
temperature.

 The second step is to anneal the bonded pair to increase bonding strength.

 The third step is to thin down one side of the bonded pair to an appropriate thickness by
grinding, etching and polishing.
5. ELTRAN (Epitaxial Layer Transfer)
 Start – Begin with a seed wafer.
 Anodizing – Create a double-layer porous silicon structure through anodization.
 Epitaxial Growth – Grow a monocrystalline silicon layer on top of the porous silicon.
 Oxidation – Form a thin SiO₂ layer on the silicon surface.
 Bonding – Bond the oxidized silicon layer to a handle wafer.
 Splitting – Separate the silicon layer from the seed wafer at the porous silicon interface.
 Etching – Remove residual porous silicon.
 H₂ Annealing – Final annealing process to improve the SOI wafer quality.
5. Smart-Cut Technology

 A thin oxide layer (BOX layer) is grown on the wafer surface to act as an insulating layer.
 Hydrogen (H₂) ions are implanted into the wafer just below the BOX layer.
 This creates a layer of microcavities where splitting will occur.
 The oxidized wafer is flipped and bonded to a handle wafer.
 Upon heating, hydrogen accumulates at the implanted region, forming bubbles and
microcracks.
 This weakens the structure along the H₂ implantation depth.
 The applied heat causes the implanted wafer to split along the hydrogen plane.
 After CMP (Chemical Mechanical Polishing) and cut, we obtain a high-quality SOI
wafer.
Types of SOI devices

1. Partially Depleted Silicon On Insulator (PD-SOI)

 In Partially Depleted SOI (PD-SOI) MOSFETs, the silicon layer on top of the buried oxide
(BOX) is thicker compared to Fully Depleted SOI (FD-SOI).
 This means that when the MOSFET operates, not all of the body region beneath the gate gets
inverted.
 Since the silicon layer is thick, there is an extra body region between the channel and the
buried oxide.
 Holes get trapped in this body region.
 This region is floating (not connected to a fixed voltage like Vss or Vdd), so it can store
charge temporarily.
 The extra charge stored in the floating body changes the threshold voltage of the MOSFET.
 This means the MOSFET’s switching behavior depends on its previous states (this is called
the history effect).
 Since the body is floating, its voltage keeps changing based on how the transistor has been
used before.
 If the body voltage changes, the threshold voltage (Vth) also changes, which affects:
o Switching speed (how fast the transistor turns on/off).
o Parasitic capacitances (which influence circuit timing).
o Mismatch issues between two supposedly identical transistors.
  In bulk CMOS, the body is tied to a fixed voltage (Vss for NMOS, Vdd for PMOS), so
threshold voltage remains stable.
 In PD-SOI, the floating body makes the threshold voltage change dynamically, leading to
delay variations.
 To reduce short-channel effects (SCEs), PD-SOI MOSFETs use high channel doping.
 This helps control leakage currents and improve performance.

2. Fully Depleted Silicon On Insulator (FD-SOI)

 FD-SOI is based on bulk CMOS but with two key changes:

o A very thin insulating layer called the buried oxide (BOX) is added above the
silicon substrate.
o A thin silicon film is placed on top of the BOX to form NMOS and PMOS
transistors.
 The silicon layer under the gate is very thin and lightly doped.
 This makes the entire channel fully depleted of charge carriers, eliminating the floating
body effect seen in PD-SOI.
 Since the channel is so thin, the depletion region extends across the entire body.
 This structure is called Ultra-Thin Body and Buried Oxide (UTBB-FD-SOI).
 The buried oxide layer reduces unwanted capacitance between source, drain, and
substrate.
 This allows for faster operation and lower power consumption.
 The BOX layer prevents leakage from the channel to the substrate.
 This improves power efficiency and performance stability.
 FD-SOI operates at lower voltages, making it more power-efficient.

 Body Biasing: In order to improve transistor performance a voltage can be applied to the
substrate. This method called body biasing or back biasing facilitates the creation of the
channel between the source and the drain resulting in faster switching of the transistor.
 In bulk CMOS, body biasing is very limited due to leakage current and reduced transistor
geometry. Because of the ultra thin insulator layer in FD-SOI, the body biasing creates a
buried gate below the channel making the FD-SOI act like a vertical double gate transistor.
 Different voltages can be applied to the top and buried gates which effectively changes the
characteristics of the transistor. FD-SOI can be made to work in either high performance
mode or low power mode based on the voltages applied on top and buried gates.