Maharashtra State Board of Technical Education

Mumbai. (M.S.)

MICRO PROJECT
On
“PREPARE REPORT OF CMOS FABRICATION PROCESS”

Submitted by

JOSHI ABHAY CHANDRASHEKHAR

GAIKWAD NIKHIL SANJAY
JADHAV RAHUL DAULAT

G.S. Mandal’s

Department of Electronics and Telecommunication

Engineering
Marathwada Institute of Technology, Polytechnic,
Aurangabad.

Academic Year: - 2021-2022

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 MAHARASHTRA STATE
BOARD OF TECHNICAL EDUCATION

CERTIFICATE
Roll Enrollment Exam
No. Name of Student No. Seat No.
10. JOSHI ABHAY CHANDRASHEKHAR 1900660056

11. GAIKWAD NIKHIL SANJAY 200660047

12. JADHAV RAHUL DAULAT 2000660048

This is to certify that: - have successfully completed “PREPARE REPORT OF

CMOS FABRICATION PROCESS” Micro-project for the subject VLSI
22062 as in the enclosed ‘Portfolio ‘during her tenure of completing the
Diploma in Electronics and Telecommunication Engineering (EJ6I) in
Academic Year 2021-2022 from M.I.T. Polytechnic, Aurangabad with Institute
Code 0066.

Date:

Mrs.V.P.Thakare Prof. M.G.Granthi

Guide H.O.D.

Principal
Marathwada Institute of Technology, Polytechnic,
Aurangabad
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 Micro Project

Name of Department: Diploma in Electronics and Telecommunication Engineering

semester: 6

Course Title: 22062 - VLSI with VHDL Code: 22062

Title of Micro Project: PREPARE REPORT OF CMOS FABRICATION PROCESS

Roll
No. Name of Student Enrollment No. Exam Seat No.

10. JOSHI ABHAY CHANDRASHEKHAR 1900660056

11. GAIKWAD NIKHIL SANJAY 200660047

12. JADHAV RAHUL DAULAT 2000660048

Comments / Suggestions about work:

_________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

Signature of Teacher :

Name and Designation :

Of the Teacher

Micro-Project Report
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Title:-PREPARE REPORT OF CMOS FABRICATION PROCESS

1. INTRODUCTION

CMOS stands for Complementary Metal Oxide Semiconductor

Complementary:

There are N-type and P-type transistors.

1. N-type transistors use electrons as the current carriers.

2. P-type transistors use holes as the current carriers.

Electrons are free carriers in the conduction band with energy of Ec or just above the
Conduction band edge. Free electrons are generated by doping the silicon with an N-type
Impurity such as phosphorous or arsenic.

A hole is a current carrier due to the absence of an electron in a covalent bond state, i.e.
a
Missing electron which would otherwise be part of a silicon-to-silicon bond. Holes are
free
Carriers in the valence band with energy of Ev or just below the valence band edge. Holes
are generated by doping the silicon with a P-type impurity such as boron.

• Metal:
The gate of the transistor was made of aluminum metal in the early days, but is
Made of polysilicon today (for the past 25 years or more).

• Oxide:
Silicon dioxide is the material between the gate and the channel
Semiconductor: the semiconductor material is silicon, a type IV element in the periodic
chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral crystal structure.
.
CMOS fabrication can be accomplished using either of the three technologies:

• N-well/P-well technologies
• Twin well technology
• Silicon on Insulator (SOI)

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 2. Twin Well Technology

Using twin well technology, we can optimize NMOS and PMOS transistors
separately. This means that transistor parameters such as threshold voltage,
body effect and the channel
Tran’s conductance of both types of transistors can be tuned independently.
n+ or p+ substrate, with a lightly doped epitaxial layer on top, forms the starting
material for this technology. The n-well and P-well are formed on this epitaxial
layer which forms

The conventional n-well CMOS process suffers from, among other effects, the
problem of
Unbalanced drain parasitic since the doping density of the well region typically
being about
One order of magnitude higher than the substrate. This problem is absent in the
twin-tub
Process.

3. Silicon on Insulator (SOI)

To improve process characteristics such as speed and latch-up susceptibility,

technologists
Have sought to use an insulating substrate instead of silicon as the substrate
material.
Completely isolated NMOS and PMOS transistors can be created virtually side
by side on an
Insulating substrate (e.g. sapphire) by using the SOI CMOS technology.
This technology offers advantages in the form of higher integration density
(because of the
Absence of well regions), complete avoidance of the latch-up problem, and
lower parasitic
Capacitances compared to the conventional n-well or twin-tub CMOS
processes.
But this technology comes with the disadvantage of higher cost than the
standard n-well
CMOS process. Yet the improvements of device performance and the absence
of latch up
Problems can justify its use, especially in deep submicron devices.

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 4. N-well Technology

In this discussion we will concentrate on the well-established n

technology, which requires that both N same chip substrate. To accommodate
this, special regions are created with a semiconductor type opposite to the
substrate type. The regions thus formed are called wells or tubs. In an n type
substrate, we can create a p substrate. We present here a simple n NMOS
transistor is created in the p built-in into the p-type substrate.

1) N-well regions are created for PMOS transistors, by impurity implantation

into the substrate.

2) This is followed by the growth of a thick oxide in the regions surround the
NMOS and PMOS active regions.

3) The thin gate oxide is subsequently grown on the surface through thermal
oxidation.

4) After this n+ and p+ regions (source, drain and channel-stop implants) are
created.

5) The metallization step (creation of metal interconnects) forms the final step
in this process.

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The first step of the process is the oxidation of the silicon substrate Fig which creates a
relatively thick silicon dioxide layer on the surface. This oxide layer is called field oxide
Figures. The field oxide is then selectively etched to expose the silicon surface on which
the transistor will be created Figures. After this the surface is covered with a thin, high-
quality oxide layer. This oxide layer will form the gate oxide of the MOS transistor
Figures. Then a polysilicon layer is deposited on the thin oxide Figures. Polysilicon is
used as both a gate electrode material for MOS transistors as well as an interconnect
medium in silicon integrated circuits. The resistivity of polysilicon, which is usually high,
is reduced by doping it with impurity atoms.

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 D : Proc e -

Deposition is followed by patterning and etching of polysilicon layer to form the

interconnects and the MOS transistor gates Figures. The thin gate oxide not masked by
polysilicon is also etched away exposing the bare silicon surface. The drain and source
junctions are to be formed Figures. Diffusion or ion implantation is used to dope the entire
silicon surface with a high concentration of impurities (in this case donor atoms to
produce ntype doping). Figures. shows two n-type regions (source and drain junctions) in
the p-type substrate as doping penetrates the exposed areas of the silicon surface. The
penetration of impurity doping into the polysilicon reduces its resistivity. The polysilicon
gate is patterned before the doping and it precisely defines the location of the channel
region and hence, the location of the source and drain regions. Hence this process is called
a self-aligning process.

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The entire surface is again covered with an insulating layer of silicon dioxide after the
source and drain regions are completed Figures. Next contact windows for the source and
drain are patterned into the oxide layer Figures. Interconnects are formed by evaporating
aluminium on the surface (Figures), which is followed by patterning and etching of the
metal layer Figures. A second or third layer of metallic interconnect can also be added
after adding another oxide layer, cutting (via) holes, depositing and patterning the metal.
We now return to the generalized fabrication sequence of n-well CMOS integrated
circuits. The following figures illustrate some of the important process steps of the
fabrication of a CMOS inverter by a top view of the lithographic masks and a cross-
sectional view of the relevant areas.
The n-well CMOS process starts with a moderately doped (with impurity concentration
typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer is
grown on the entire surface. The first lithographic mask defines the n-well region. Donor
atoms, usually phosphorus, are implanted through this window in the oxide. Once the n-
well is created, the active areas of the nMOS and pMOS transistors can be defined
The creation of the n-well region is followed by the growth of a thick field oxide in the
areas surrounding the transistor active regions, and a thin gate oxide on top of the active
regions. The two most important critical fabrication parameters are the thickness and
quality of the gate oxide. These strongly affect the operational characteristics of the MOS
transistor, as well as its long-term stability.
Chemical vapour deposition (CVD) is used for deposition of polysilicon layer and
patterned by dry (plasma) etching. The resulting polysilicon lines function as the gate
electrodes of the nMOS and the pMOS transistors and their interconnects. The polysilicon
gates also act as self-aligned masks for source and drain implantations.

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