Electronic Devices and Circuits

MOS Field-Effect Transistors (MOSFETs)

Lecture 2
MOSFET Circuits at DC

Prepared By: Muhammad Abdullah

muhammad.abdullah@nu.edu.pk , uetian.09@gmail.com

National University FAST (CFD Campus)

My YouTube Channel:
https://www.youtube.com/@BlueFish506

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p-Channel MOSFET

Figure 1: Physical Structure of PMOS

PMOS Structure: Similar to NMOS, with reversed semiconductor regions and

polarities.

Channel Formation: A negative gate-to-source voltage (𝑣𝐺𝑆 ) greater than |𝑉𝑡𝑝 |

induces a 𝑝 channel.

Voltage Condition: 𝑣𝐺𝑆 ≤ 𝑉𝑡𝑝 or |𝑣𝐺𝑆 | ≥ |𝑉𝑡𝑝 |

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Current Flow:
• A negative 𝑣𝐷𝑆 allows current (𝑖𝐷 ) to flow through the 𝑝-channel.

• The current 𝑖𝐷 is carried by holes moving from source to drain.

Transconductance Parameter: 𝑘𝑝′ = 𝜇𝑝 𝐶𝑜𝑥

Effective transconductance parameter: 𝑘𝑝 = 𝑘𝑝′ (𝑊/𝐿)

where 𝑊/𝐿 is the transistor aspect ratio

Modern CMOS (Complementary MOS):
• Combines NMOS and PMOS on the same chip.

Characteristics of the p-Channel MOSFET

Figure 2: Circuit symbols for the p-channel enhancement-type MOSFET

Drain current equation in PMOS considering channel modulation effect is;

1 𝑊 2
𝑖𝐷 = 𝑘𝑝′ ( ) (𝑣𝑆𝐺 − |𝑉𝑡𝑝 |) (1 + |𝜆|𝑣𝑆𝐷 )
2 𝐿
1 𝑊 2 𝑣𝑆𝐷
𝑖𝐷 = 𝑘𝑝′ ( ) (𝑣𝑆𝐺 − |𝑉𝑡𝑝 |) (1 + )
2 𝐿 |𝑉𝐴 |
where 𝜆 and 𝑉𝐴 are by convention negative quantities, hence we use |𝜆| and |𝑉𝐴 |.

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Example 1

The PMOS transistor shown in Figure 3 has 𝑉𝑡𝑝 = −1 V, 𝑘𝑝′ = 60𝜇 A/V 2 , and
𝑊/𝐿 = 10.

a) Find the range of 𝑉𝐺 for which the transistor conducts.

b) In terms of 𝑉𝐺 , find the range of 𝑉𝐷 for which the transistor operates in the
triode region.
c) In terms of 𝑉𝐺 , find the range of 𝑉𝐷 for which the transistor operates in
saturation.
d) Neglecting channel-length modulation (i.e., assuming 𝜆 = 0 ), find the values
of |𝑉𝑂𝑉 | and 𝑉𝐺 and the corresponding range of 𝑉𝐷 to operate the transistor in
the saturation mode with 𝐼𝐷 = 75𝜇 A.
e) If 𝜆 = −0.02 V −1 , find the value of 𝑟𝑜 corresponding to the overdrive voltage
determined in (d).
f) For 𝜆 = −0.02 V −1 and for the value of 𝑉𝑂𝑉 determined in (d), find 𝐼𝐷 at 𝑉𝐷 =
+3 V and at 𝑉𝐷 = 0 V; hence, calculate the value of the apparent output
resistance in saturation. Compare to the value found in (e).

VS

(a) Given Circuit (b) Labelled Circuit

Figure 3

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Solution:
It is given that: 𝑉𝑡𝑝 = −1 V ; 𝑘𝑝′ = 60𝜇 A/V 2 ; 𝑊/𝐿 = 10
𝑊
𝑘𝑝 = 𝑘𝑝′ ( ) = 60𝜇 × 10 = 600𝜇 A/V 2
𝐿

Part (a)
Conduction occurs for 𝑉𝑆𝐺 ≥ |𝑉𝑡𝑝 |
𝑉𝑆 − 𝑉𝐺 ≤ |𝑉𝑡𝑝 |
𝑉𝐺 ≤ 𝑉𝑆 − |𝑉𝑡𝑝 |
𝑉𝐺 ≤ 5 − 1
𝑉𝐺 ≤ 4 V
So, transistor conducts as long as 𝑉𝐺 ≤ 4 V

Part (b)
Triode region occurs for 𝑉𝐷𝐺 ≥ |𝑉𝑡𝑝 |
𝑉𝐷 − 𝑉𝐺 ≥ |𝑉𝑡𝑝 |
𝑉𝐷 ≥ 𝑉𝐺 + |𝑉𝑡𝑝 |
𝑉𝐷 ≥ 𝑉𝐺 + 1

Part (c)
Conversely, for saturation
𝑉𝐷𝐺 ≤ |𝑉𝑡𝑝 |
𝑉𝐷 − 𝑉𝐺 ≤ |𝑉𝑡𝑝 |
𝑉𝐷 ≤ 𝑉𝐺 + |𝑉𝑡𝑝 |
𝑉𝐷 ≤ 𝑉𝐺 + 1

Part (d)
Given 𝜆 ≅ 0

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It is given that: 𝐼𝐷 = 75𝜇 A
1
𝐼𝐷 = 𝑘𝑝 |𝑉𝑂𝑉 |2
2

2𝐼𝐷 2 × 75𝜇
|𝑉𝑂𝑉 | = √ =√ = 0.5 𝑉
𝑘𝑝 600𝜇

|𝑉𝑂𝑉 | = 𝑉𝑆𝐺 − |𝑉𝑡𝑝 |  𝑉𝑆𝐺 = |𝑉𝑂𝑉 | + |𝑉𝑡𝑝 | = 0.5 + 1 = 1.5 𝑉

𝑉𝑆𝐺 = 𝑉𝑆 − 𝑉𝐺  𝑉𝐺 = 𝑉𝑆 − 𝑉𝑆𝐺 = 5 − 1.5 = 3.5 𝑉
In part (c), we have derived the following condition for transistor to be in saturation
𝑉𝐷 ≤ 𝑉𝐺 + 1
𝑉𝐷 ≤ 3.5 + 1
𝑉𝐷 ≤ 4.5

Part (e)
For 𝜆 = −0.02 V −1 and |𝑉𝑂𝑉 | = 0.5 V, 𝐼𝐷 = 75𝜇 A
1 1
𝑟𝑜 = = = 667 kΩ
|𝜆|𝐼𝐷 0.5 × 75𝜇

Part (f)
1
𝐼𝐷 = 𝑘𝑝 |𝑉𝑂𝑉 |2 (1 + |𝜆||𝑉𝑆𝐷 |)
2
At 𝑉𝐷 = 3 V  𝑉𝑆𝐷 = 𝑉𝑆 − 𝑉𝐷 = 5 − 3 = 2 𝑉
1
𝐼𝐷 = × 60𝜇 × (0.5)2 (1 + 0.02 × 2) = 78𝜇 𝐴
2
At 𝑉𝐷 = 0 V  𝑉𝑆𝐷 = 𝑉𝑆 − 𝑉𝐷 = 5 − 0 = 5 𝑉
1
𝐼𝐷 = × 60𝜇 × (0.5)2 (1 + 0.02 × 5) = 82.5𝜇 𝐴
2
Δ𝑉𝐷𝑆 3−0 3
𝑟𝑜 = = = = 667 𝑘Ω
Δ𝐼𝐷 82.5𝜇 − 78𝜇 4.5𝜇 A
which is the same value found in (c)

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MOSFET Circuits at DC

Having studied the current–voltage characteristics of MOSFETs, we now consider

circuits in which only dc voltages and currents are of concern.
This section covers the analysis of MOSFET circuits with DC voltages and currents,
emphasizing simplicity by neglecting channel-length modulation (𝜆 = 0). The
overdrive voltage is used for analysis:
• 𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛 for NMOS
• |𝑉𝑂𝑉 | = 𝑉𝑆𝐺 − |𝑉𝑡𝑝 | for PMOS
The goal is to enable quick and effective understanding of MOSFET circuit behavior.

Example 2

Design the circuit of Figure 4: that is, determine the values of 𝑅𝐷 and 𝑅𝑆 so that the
transistor operates at 𝐼𝐷 = 0.4 mA and 𝑉𝐷 = +0.5 V. The NMOS transistor has 𝑉𝑡 =
0.7 V, 𝜇𝑛 𝐶𝑜𝑥 = 100𝜇 A/V 2 , 𝐿 = 1𝜇 m, and 𝑊 = 32𝜇 m. Neglect the channel-
length modulation effect (i.e., assume that 𝜆 = 0 ).

VG

VS

(a) Given Circuit (b) Labelled Circuit

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 Figure 4

Solution:
𝑊 𝑊 32
𝑘𝑛 = 𝑘𝑛′ ( ) = 𝜇𝑛 𝐶𝑜𝑥 = 100𝜇 × = 3200𝜇 A/V 2
𝐿 𝐿 1
𝑉𝐷𝐷 − 𝑉𝐷 2.5 − 0.5
𝑅𝐷 = = = 5 kΩ
𝐼𝐷 0.4𝑚
𝑉𝑆 − 𝑉𝑆𝑆
𝑅𝑆 =
𝐼𝐷
So, to find 𝑅𝑆 first of all we need to find 𝑉𝑆 .
As 𝑉𝐷 = 0.5𝑉 > 𝑉𝐺 = 0𝑉, so NMOS transistor is operating in saturation. So;
1 2
𝐼𝐷 = 𝑘𝑛 𝑉𝑂𝑉
2

2𝐼𝐷 2 × 400𝜇
𝑉𝑂𝑉 = √ =√ = 0.5 𝑉
𝑘𝑛 3200𝜇

𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡  𝑉𝐺𝑆 = 𝑉𝑡 + 𝑉𝑂𝑉 = 0.7 + 0.5 = 1.2 V

𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆  𝑉𝑆 = 𝑉𝐺 − 𝑉𝐺𝑆 = 0 − 1.2 = −1.2 𝑉
So, now 𝑅𝑆 can be calculated as;
𝑉𝑆 − 𝑉𝑆𝑆 −1.2 − (−2.5) −1.2 + 2.5
𝑅𝑆 = = = = 3.25 kΩ
𝐼𝐷 400𝜇 400𝜇

Example 3

Figure 5 shows an NMOS transistor with its drain and gate terminals connected
together. Find the 𝑖 − 𝑣 relationship of the resulting two-terminal device in terms of
the MOSFET parameters 𝑘𝑛 = 𝑘𝑛′ (𝑊/𝐿) and 𝑉𝑡𝑛 . Neglect channel-length
modulation (i.e., 𝜆 = 0 ). Note that this two-terminal device is known as a diode-
connected transistor.

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 VD
VG

VS

(a) Given Circuit (b) Labelled Circuit

Figure 5

Solution:
As 𝑉𝐷 = 𝑉𝐺 so  𝑉𝐺𝐷 = 𝑉𝐺 − 𝑉𝐷 = 0 𝑉
As 𝑉𝐺𝐷 ≤ 𝑉𝑡𝑛  0 ≤ 𝑉𝑡𝑛
So, NMOS is operating in saturation mode.
1 𝑊
𝐼𝐷 = 𝑘𝑛′ ( ) (𝑉𝐺𝑆 − 𝑉𝑡𝑛 )2
2 𝐿
Now, 𝑖 = 𝐼𝐷 and 𝑣 = 𝑉𝐺𝑆 , thus
𝑖 = 𝑘𝑛 (𝑣 − 𝑉𝑡𝑛 )2

Example 4

For the circuit in Figure 6, find the value of 𝑅 that results in 𝑉𝐷 = 0.7 V. The
MOSFET has 𝑉𝑡𝑛 = 0.5 V, 𝜆 = 0 and
𝑊 0.72𝜇 m
𝜇𝑛 𝐶𝑜𝑥 = 0.4𝑚 A/V 2 , = =4
𝐿 0.18𝜇 m

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 VDD =

ID

VG

VS

(a) Given Circuit (b) Labelled Circuit

Figure 6

Solution:
𝑊 𝑊
𝑘𝑛 = 𝑘𝑛′ ( ) = 𝜇𝑛 𝐶𝑜𝑥 = 0.4𝑚 × 4 = 1.6𝑚 A/V 2
𝐿 𝐿
As 𝑉𝐷 = 𝑉𝐺 so  𝑉𝐺𝐷 = 𝑉𝐺 − 𝑉𝐷 = 0 𝑉
As 𝑣𝐺𝐷 ≤ 𝑉𝑡𝑛  0 ≤ 𝑉𝑡𝑛
So, NMOS is operating in saturation mode.
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 0.7 − 0 = 0.7
𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛 = 0.7 − 0.5 = 0.2 𝑉
1 2
1
𝐼𝐷 = 𝑘𝑛 𝑉𝑂𝑉 = 1.6𝑚 × (0.2)2 = 0.032 𝑚𝐴
2 2
Now, 𝑅𝐷 can be calculated as;
𝑉𝐷𝐷 − 𝑉𝐷 1.8 − 0.7
𝑅𝐷 = = = 34.4 𝑘Ω
𝐼𝐷 0.032𝑚

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Example 5

Figure 7 shows a circuit obtained by augmenting the circuit of Figure 6 considered

in Example 4 with a transistor 𝑄2 identical to 𝑄1 and a resistance 𝑅2 . Find the value
of 𝑅2 that results in 𝑄2 operating at the edge of the saturation region. Use your
solution to Example 4.

(a) Given Circuit

I D2 I D1

VD2 VD1

VS VS
VG
(b) Labelled Circuit

Figure 7

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Solution:
Since 𝑄2 is identical to 𝑄1 and their 𝑉𝐺𝑆 values are the same,
𝐼𝐷2 = 𝐼𝐷1 = 0.032 mA
For 𝑄2 to operate at the edge of the saturation region, we must have;
𝑉𝐷2 = 𝑉𝑂𝑉 = 0.2 V
𝑉𝐷𝐷 − 𝑉𝐷2 1.8 V − 0.2 V
𝑅2 = = = 50kΩ
𝐼𝐷2 0.032 mA

Example 6

Design the circuit in Figure 8 to establish a drain voltage of 0.1 V . What is the
effective resistance between drain and source at this operating point? Let 𝑉𝑡𝑛 = 1 V
and 𝑘𝑛′ (𝑊/𝐿) = 1 mA/V 2 .

VG
VS

(a) Given Circuit (b) Labelled Circuit

Figure 8

Solution:
It is given that: 𝑉𝐺 = 𝑉𝐷𝐷 = 5𝑉 ; 𝑉𝐷 = 0.1 𝑉 ; 𝑉𝑆 = 0𝑉
𝑉𝐺𝐷 = 𝑉𝐺 − 𝑉𝐷 = 5 − 0.1 = 4.9 𝑉
𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛 = 5 − 1 = 4 𝑉
As 𝑉𝐺𝐷 > 𝑉𝑡𝑛 so NMOS is operating in triode region. So,
1 2
𝐼𝐷 = 𝑘𝑛 [𝑉𝑂𝑉 𝑉𝐷𝑆 − 𝑉𝐷𝑆 ]
2

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 1
𝐼𝐷 = 1𝑚 × [4 × 0.1 − × (0.1)2 ] = 0.395 mA
2
𝑉𝐷𝐷 − 𝑉𝐷 5 − 0.1
𝑅𝐷 = = = 12.4 kΩ
𝐼𝐷 0.395𝑚
𝑉𝐷𝑆 0.1
𝑟𝐷𝑆 = = = 253Ω or
𝐼𝐷 0.395𝑚
1 1
𝑟𝐷𝑆 = = = 0.25kΩ = 250Ω
𝑘𝑛 𝑉𝑂𝑉 1𝑚 × 4

Example 7

Analyze the circuit shown in Figure 9 to determine the voltages at all nodes and the
currents through all branches. Let 𝑉𝑡𝑛 = 1 V and 𝑘𝑛′ (𝑊/𝐿) = 1 mA/V 2 . Neglect the
channel-length modulation effect (i.e., assume 𝜆 = 0 ).
VDD

ID RD
R G1
VD
VG
VS
RG2 ID RS

(a) Given Circuit (b) Labelled Circuit

Figure 9

Solution:
Since the gate current is zero, the voltage at the gate is simply determined by the
voltage divider formula;

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 𝑅𝐺2 10𝑀
𝑉𝐺 = 𝑉𝐷𝐷 ( ) = 10 ( )=5V
𝑅𝐺2 + 𝑅𝐺1 10𝑀 + 10𝑀
When a positive voltage is applied to the gate of an NMOS transistor, it turns on. To
determine its operating region (saturation or triode), assume saturation operation,
solve the problem, and validate the assumption. If incorrect, reevaluate for triode-
region operation.
So, assuming that NMOS is operating in Saturation Region.
𝑉𝑆 = 𝐼𝐷 𝑅𝑆 = 6000𝐼𝐷
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 5 − 6000𝐼𝐷
𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛 = 5 − 6000𝐼𝐷 − 1 = 4 − 6000𝐼𝐷
Drain current in saturation region is;
1
𝐼𝐷 = 𝑘𝑛 (𝑉𝑂𝑉 )2
2
1
𝐼𝐷 = × 1𝑚 × (4 − 6000𝐼𝐷 )2
2
By simplifying the above equation, we get;
2250000𝐼𝐷 2 − 3125𝐼𝐷 + 1 = 0
By solving above quadratic equation, we get;
𝐼𝐷 = 0.89 𝑚𝐴, 0.5 𝑚𝐴
When 𝐼𝐷 = 0.89 𝑚𝐴
𝑉𝑆 = 𝐼𝐷 𝑅𝑆 = 0.89𝑚 × 6000 = 5.34 𝑉
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 5 − 5.34 = −0.34 𝑉
As 𝑉𝐺𝑆 < 𝑉𝑡𝑛 , so NMOS will be in cutoff mode, so this value of 𝐼𝐷 does not make
sense physically. Thus, required value of 𝐼𝐷 = 0.5 𝑚𝐴
𝑉𝑆 = 𝐼𝐷 𝑅𝑆 = 0.5𝑚 × 6000 = 3 𝑉
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 5 − 3 = 2 𝑉
𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 10 − 0.5𝑚 × 6𝑘 = 7 𝑉

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𝑉𝐺𝐷 = 𝑉𝐺 − 𝑉𝐷 = 5 − 7 = −2 𝑉
As 𝑉𝐺𝐷 ≤ 𝑉𝑡𝑛 , so it is verified that transistor is operating in saturation region. Hence
our initial assumption is correct and hence the above analysis is also correct.

Example 8

Design the circuit of Figure 10 so that the transistor operates in saturation with
𝐼𝐷 = 0.5 mA and 𝑉𝐷 = +3 V. Let the enhancement-type PMOS transistor have
𝑉𝑡𝑝 = −1 V and 𝑘𝑝′ (𝑊/𝐿) = 1 mA/V 2 . Assume 𝜆 = 0. What is the largest value
that 𝑅𝐷 can have while maintaining saturation-region operation?

VS
VG

(a) Given Circuit (b) Labelled Circuit

Figure 10

Solution:
Drain current in saturation region is;
1
𝐼𝐷 = 𝑘𝑝 (𝑉𝑂𝑉 )2
2

2𝐼𝐷 2 × 0.5𝑚
𝑉𝑂𝑉 = √ =√ =1𝑉
𝑘𝑝 1𝑚

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|𝑉𝑂𝑉 | = 𝑉𝑆𝐺 − |𝑉𝑡𝑝 |
𝑉𝑆𝐺 = |𝑉𝑡𝑝 | + |𝑉𝑂𝑉 | = 1 + 1 = 2 V
𝑉𝑆𝐺 = 𝑉𝑆 − 𝑉𝐺  𝑉𝐺 = 𝑉𝑆 − 𝑉𝑆𝐺 = 5 − 2 = 3 𝑉
Using voltage division rule
𝑅𝐺2
𝑉𝐺 = 𝑉𝐷𝐷 ( )
𝑅𝐺1 + 𝑅𝐺2
𝑅𝐺2
3 = 5( )
𝑅𝐺1 + 𝑅𝐺2
3𝑅𝐺1 + 3𝑅𝐺2 = 5𝑅𝐺2
3𝑅𝐺1 = 2𝑅𝐺2
2
𝑅𝐺1 = 𝑅𝐺2
3
Assuming 𝑅𝐺2 = 3 𝑀Ω gives 𝑅𝐺1 = 2 𝑀Ω
So, now 𝑅𝐷 can be calculated as;
𝑉𝐷 3
𝑅𝐷 = = = 6 kΩ
𝐼𝐷 0.5𝑚
Saturation region is maintained as long as 𝑉𝐷𝐺 ≤ |𝑉𝑡𝑝 |
𝑉𝐷𝑚𝑎𝑥 − 𝑉𝐺 = |𝑉𝑡𝑝 |
𝑉𝐷𝑚𝑎𝑥 = |𝑉𝑡𝑝 | + 𝑉𝐺 = 1 + 3 = 4 𝑉
This value of drain voltage is obtained with 𝑅𝐷 given by;
𝑉𝐷𝑚𝑎𝑥 4
𝑅𝐷,𝑚𝑎𝑥 = = = 8 kΩ
𝐼𝐷 0.5𝑚

Example 9

For the circuit in Figure 11, find the value of 𝑅 that results in the PMOS transistor
operating with an overdrive voltage |𝑉𝑂𝑉 | = 0.6 V. The threshold voltage is 𝑉𝑡𝑝 =

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−0.4 V, the process transconductance parameter 𝑘𝑝 ′ = 0.1 mA/V 2 , and 𝑊/𝐿 =
10𝜇 m/0.18𝜇 m.
VDD

VG VS

VD

(a) Given Circuit (b) Labelled Circuit

Figure 11

Solution:
𝑊 10𝜇
𝑘𝑝 = 𝑘𝑝′ ( ) = 0.1𝑚 ( ) = 5.56 mA/V 2
𝐿 0.18𝜇
As 𝑉𝐺 = 𝑉𝐷 = 0  𝑉𝐷𝐺 ≤ |𝑉𝑡𝑝 |
So, PMOS is operating in saturation mode.
|𝑉𝑂𝑉 | = 𝑉𝑆𝐺 − |𝑉𝑡𝑝 |
𝑉𝑆𝐺 = |𝑉𝑡𝑝 | + |𝑉𝑂𝑉 | = 0.4 + 0.6 = 1 V
𝑉𝑆 − 𝑉𝐺 = 1  𝑉𝑆 − 0 = 1  𝑉𝑆 = 1 𝑉
Drain current in saturation region is;
1 1
𝐼𝐷 = 𝑘𝑝 (𝑉𝑂𝑉 )2 = × 5.56𝑚 × (0.6)2 = 1 𝑚𝐴
2 2
𝑉𝑆𝑆 − 𝑉𝑆 1.8 − 1
𝑅𝐷 = = = 800 Ω
𝐼𝐷 1𝑚

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