Scribd
Upload
15 views3 pages

8086 Microprocessor Solutions

The document provides an overview of 8086 microprocessor concepts, including addressing modes, I/O addressing with BIOS and DOS, and the use of interrupts. It discusses various instructions like MUL and DIV, differences between certain commands, and the architecture of multi-core ICs. Additionally, it covers VM8086 mode, duty cycles, and the multi-segment model, along with short notes on overlapping segments and co-processors.

Uploaded by

mansoureh225
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
15 views3 pages

8086 Microprocessor Solutions

The document provides an overview of 8086 microprocessor concepts, including addressing modes, I/O addressing with BIOS and DOS, and the use of interrupts. It discusses various instructions like MUL and DIV, differences between certain commands, and the architecture of multi-core ICs. Additionally, it covers VM8086 mode, duty cycles, and the multi-segment model, along with short notes on overlapping segments and co-processors.

Uploaded by

mansoureh225
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

8086 Microprocessor Concepts - Solutions

1. a) Addressing Mode:

An addressing mode tells the CPU where to find the data (operand) for an instruction.

Examples include immediate, register, direct, and indirect addressing.

I/O Addressing with BIOS and DOS:

- BIOS provides low-level I/O control using interrupts like INT 10H, INT 13H.

- DOS provides high-level I/O services using INT 21H.

b) ISR Address for INT 31H:

The interrupt vector table starts at 0000:0000. Each ISR has 4 bytes (2 for offset, 2 for segment).

For INT 31H: 31 * 4 = 124 = 7CH ISR pointer is stored at 0000:007C.

c) MUL and DIV in 8086:

i. Using Register Addressing:

MOV AL, 4

MOV BL, 3

MUL BL ; AL = 12

MOV AX, 0018H

MOV BL, 6

DIV BL ; AL = 4, AH = 0

ii. Using Bit Manipulation:

SHL AL, 2 ; multiply by 4

SHR AL, 1 ; divide by 2

2. a) Differences:

- ALE vs BHE: ALE is for address latch, BHE for enabling high byte of data.

- LEA vs OFFSET: LEA computes at runtime, OFFSET is resolved at compile time.

- NOT vs NEG: NOT is bitwise invert, NEG is arithmetic negation.


- AND vs TEST: AND stores result, TEST only sets flags.

b) Min vs Max Mode (Pins 2431):

- Min: uses ALE, INTA, WR, RD signals.

- Max: uses status signals S0S2 and bus controller (e.g., 8288).

c) LABEL vs LOOP:

LABEL is a marker. LOOP uses CX to control iterations.

Program reserves 64KB data, 1024B stack.

3. a) READ Bus Timing:

Uses T1T4 states. ALE generates address latch. RD low enables read. WAIT states delay T3. Address 10000H.

b) Multi-core IC:

Combines multiple cores in a single die for parallelism. Example: Intel Core i7 has 4+ cores sharing cache.

c) Parity & Memory Banks:

Pentium uses ECC and parity. Memory bank comparisons:

- 8085: 8-bit

- 8086: 16-bit (2 banks)

- 80386: 32-bit

- Pentium: 64-bit, interleaved

4. a) VM8086 Mode:

Allows running 8086 apps in protected mode.

Flags:

- 8085: 8-bit

- 8086: 16-bit

- 80286: Adds VM

- 80386: 32-bit with NT, VM, IOPL, etc.

b) Duty Cycle:
= (Active Time / Total Time) x 100%

Clock State Machine Cycle Instruction Cycle

c) PROCEDURE vs MACRO:

PROCEDURE: code reused with CALL/RET.

MACRO: code is expanded inline.

5. a) Multi-Segment Model:

Code + multiple Data Segments + Stack. Example: .DATA, .DATA1, .DATA2

b) Linear Address & Pentium Pipeline:

Linear address = Segment base + Offset.

U-pipeline and V-pipeline allow dual instruction execution.

GDT occupies 64KB: 8-byte descriptor 8192 entries.

6. Short Notes:

i. Overlapping Segments: EMU8086 allows shared DS, ES, etc.

ii. Co-processors: 8087, 80287, 80387.

iii. MSW: Contains system control flags.

iv. FPU: Handles float operations, uses stack registers.

v. Paging: Converts logical to physical addresses using page tables.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy