Embedded System Design

Presented by,
C Sharmila Suttur
ECE,RIT

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 EMBEDDED SYSTEM DESIGN-SYLLABUS

UNIT 1
Typical Embedded Systems: Core of the embedded system, memory, sensors
and actuators, communication interface, other system components,
characteristics and quality attributes of embedded systems

UNIT – II
Programming for Embedded Systems: Overview of ANSI C, GNU
development tools, bit manipulation using C, memory management, timing of
programs, device drivers.
Types of files generated on cross compilation, disassembler/decompiler,
simulators and emulators.
Hardware Software Co-Design and Program Modelling: Fundamental issues
in hardware software co-design, computational models in embedded systems
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 EMBEDDED SYSTEM DESIGN-SYLLABUS

UNIT – III
GPIO and Interfacing: General purpose input/output ports, Interfacing of
ADC, DAC, UART, I2C, LCD, stepper motor, LED, keypad and 7-segment
display using data sheets of a microcontroller
UNIT – IV
RTOS and IDE for Embedded System Design: Operating system basics, types
of operating systems, tasks, Processes, Signals, process and threads,
Multithreading, Multiprocessing and Multitasking, Task Scheduling:
Scheduling Algorithms-Non Preemptive Scheduling, preemptive scheduling
with numerical.
UNIT – V
Inter-process communication: Task communication: Shared Memory, Pipes,
Message Passing, Task Synchronization: task synchronization issues – racing
and deadlock, Priority Inversion, Task Synchronisation Techniques:
Semaphores-concept of binary and counting semaphores, how to choose an
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RTOS.
 EMBEDDED SYSTEM DESIGN-SYLLABUS

TEXT BOOKS / REFERENCES

1. Dr. K. V. K. K. Prasad, “Embedded Real-Time Systems: Concepts,

Design & Programming”, Reprint Edition, Dreamtech Press, 2013.

2. Shibu K. V, “Introduction to Embedded Systems”, 2nd Edition, Tata

McGraw Hill Education, 2017. 23

3. James K. Peckol, “Embedded Systems – A Contemporary Design

Tool”, Student Edition, John Wiley and Sons, 2014

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• DSP Processors: Examples: SHARK , Blackfin Processors

• ASIP: TVs, algorithms for cryptography, DSP or neural networks

• Gaming Consoles: ASICs enhance graphics rendering and processing speeds.

• Wearables: Devices like fitness trackers rely on ASICs for health monitoring

and connectivity.

• chip designed to run in a digital voice recorder

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Sensors and Actuators

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Communication Interface

• Communication interface is essential for communicating with

various subsystems of the embedded system and with the external
world

• The communication interface can be viewed in two different

perspectives; namely;

1. Device/board level communication interface (Onboard

Communication Interface)
2. Product level communication interface (External
Communication Interface)
Serial Peripheral Interface

□ The serial peripheral interface was introduced by

Motorola and is the simplest synchronous
communication protocol in general use.

□ The only problem is that it is not a fixed standard like

I²C. There are plenty of options within “standard” SPI
and innumerable variations that go beyond this.

□ You must always read the data sheet closely for a

device that uses SPI and ensure that you understand
the details of the protocol precisely.
□ One device is the master and the other the slave. The master provides
the clock for both devices and a signal to select (enable) the slave
The concept of SPI is based on

□ two shift registers, one in each device, which are connected to form
a loop.
□ The registers usually hold 8 bits.
□ Each device places a new bit on its output from the most significant
bit (msb) of the shift register when the clock has a negative edge and
reads its input into the lsb of the shift register on a positive edge of
the clock.
□ Thus a bit is transferred in each direction during each clock cycle.
□ After eight cycles the contents of the shift registers have been
exchanged and the transfer is complete.
Two ways of connecting two slaves to a single master using SPI
□ The alternative is to connect all the devices in a “daisy chain,”.
□ In this configuration the MOSI pins are not all connected together,
nor the MISO pins
□ The MISO pin of a slave is connected to the MOSI pin of the next
slave in the chain.
□ The MOSI pin of of the final slave is connected to MOSI on the
master.
□ Effectively all the shift registers inside each device are connected
into a single, long loop.
Inter-integrated Circuit Bus

The I²C bus was introduced by Philips (now NXP) Semiconductors.

The I²C bus uses only two, bidirectional lines:

• Serial data (SDA).
• Serial clock (SCL).
□ It is often called the two-wire interface.
□ Thus I²C provides the full functionality of a bus while using fewer
lines than SPI.

□ Inevitably there are penalties.

□ The first is that it is slow, only 100 kbit/sec in standard mode.

□ Second, a protocol must be observed: You cannot merely transmit

the data and nothing more, as in SPI. More hardware is needed than
a simple shift register and transmissions must be controlled by
logic such as a state machine.
I²C Protocol
□ Transfers consist of a sequence of 8-bit bytes, which are sent with
the msb first and must be acknowledged to confirm successful
reception.

□ The recipient does this by writing a further acknowledgment (A) bit

of 0 to SDA.

□ The timing relationship between the data on the SDA line and the
clock on SCL is
• Data on SDA must be stable while SCL is high.
• The state of SDA may change only while SCL is low.

This means that data should be read after a rising edge of SCL and new
values should be written after a falling edge of SCL.
1.The master sends a start condition (S) by pulling SDA low
while SCL is high.

2. The master starts the clock and puts the first bit of the
address on SDA after SCL has gone low.
3. The value on SDA is valid after SCL has gone high and is
read by all slaves on the bus.
4. The last two steps are repeated until all 7 bits of the address
have been sent.
5. The final bit of the first byte specifies the direction for the
rest of the transfer. Here it is R/W*= 1, which shows that
the master wishes to read data from the slave.
6. The ninth bit is the acknowledgment (A or Ack), which is
low and is sent by the slave that recognizes its address.
7. The master must check that a slave acknowledges the address and abort
the transfer if the low bit is missing.

8. The next 8 clock cycles are used to transmit 1 byte of data from the
slave to the master. The master continues to provide the clock.

9. The ninth bit would normally be an acknowledgment. The master does

not acknowledge the final byte that it wishes to read in a transfer. This
signals to the slave that the master has received sufficient data. Here
the master expects only a single byte so it does not pull SDA low. This
is a “not acknowledgment” signal (A or Nack).

10. There is a final cycle of the clock to set up the stop signal. The master
pulls SDA low after the falling edge of the clock, which is the normal
time for changing SDA. It releases it again after the final rising edge
of the clock to give a rising edge on SDA while SCL is high, which
provides the stop signal (P).
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