ASM-HEMT: Compact Modeling of

GaN HEMTs for High Frequency and

High Power Applications
Dr. Yogesh S. Chauhan
Associate Professor
Nanolab, Department of Electrical Engineering
IIT Kanpur
Email: chauhan@iitk.ac.in
Homepage – http://home.iitk.ac.in/~chauhan/
 Outline
• Overview of Compact Modeling

• GaN HEMT

• ASM-HEMT Model Overview

• Model Validation

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Joint Development & Collaboration

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 PDK and Compact Model

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 Enablers of a silicon chip design

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Source: David HARAME at. al., IBM J. RES. & DEV. MARCH/MAY 2003
Goal of a PDK – The output of Enablement
Enablement PDK
Technology Innovation Key to Happy Designers!! Circuit Designers

• Offer a circuit design environment that enables full

exploitation of technology
• Capture all device physics
• Model impact of layout choices on device mean and variance
• Include typical layout effects for simulation from schematic
• Accurate modeling of layout effects for simulation from layout
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 Compact Modeling or SPICE Modeling

Medium of
information
exchange

 Good model should be • Excellent Convergence

 Accurate: Trustworthy simulations. • Simulation Time – ~µsec
 Simple: Parameter extraction is
easy. • Accuracy requirements
 Balance between accuracy and • ~ 1% RMS error after fitting
simplicity depends on end application
• Example: BSIM6, BSIM-
CMG
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 Industry Standard Compact
Models
• Standardization Body – Compact Model Coalition

• CMC Members – EDA Vendors, Foundries, IDMs,

Fabless, Research Institutions/Consortia

• CMC is by the industry and for the industry

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 GaN Properties

Device characteristics:
• High Breakdown Voltage ( )
• Low ON Resistance ( )

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[U. K. Mishra et al., Proc. IEEE, 96 (2), 287 (2008)]
 GaN HEMT: Advantages

Alex Q. Huang pp. 528-531, IEDM 2016

advantage of fast gate Reduction in switching Reverse recovery

driving capability loss in hard or soft loss reduction
switched converter

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 Polarization
Polarization!

Wurtzite

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[O. Ambacher et al., JAP, 85 (6), 3222 (1999)]
 GaN Wafers
• Sapphire (Al2O3)
TEM Image of GaN on Sapphire
 Semi-insulating  Low thermal conductivity
 High growth temperatures  Lattice mismatch
 Relatively cheap  CTE mismatch
Dislocations ~ 10
• Silicon (Si)
 Low cost  Lattice mismatch
 Large diameters  CTE mismatch
 Acceptable thermal conductivity
 Processing in standard silicon fabs

• Silicon Carbide (SiC)

 High thermal conductivity  Highly costly
 Low Lattice mismatch  Smaller Wafers
 Low CTE mismatch

[S. Huang, JJAP, 47 (10), 7998 (2008)]

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[U. K. Mishra et al., Proc. IEEE, 96 (2), 287-305 (2008)] [S. L. Selvaraj et al., Proc. DRC, 53 (2012)]
 GaN HEMT Structure
Ti/Al/Ti/Au Pt/Au Ti/Al/Ti/Au
S G
G D
AlGaN
AlGaN Spacer Layer (UID)

2DEG GaN

Graded AlGaN to GaN

Substrate

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 AlGaN/GaN Hetero-structure
• The AlGaN/GaN hetero-structure is used to take
advantage of the two dimensional electron gas (2-DEG)
• AlGaN/GaN materials create piezoelectric and
spontaneous polarization effects using an un-doped
hetero-interface

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 2DEG Source

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[J. P. Ibbetson et al., APL, 77 (2), 250 (2000)]
 Design Rules – Materials
Perspective
• Thickness of the barrier – 2DEG control

• Al Mole Fraction – 2DEG Concentration

• Nucleation and Buffer Layer – Dislocations

• Substrate – Thermal Properties

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 GaN HEMT
Some interesting features of III-
nitride system:
• Wide bandgap
• High 2-DEG charge density
• High electron mobility
• High breakdown voltage
• Excellent thermal conductivity
• High power density per mm of gate
periphery

• GaN based HEMTs are able to operate in

high frequency, high power as well as
high temperature device applications

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 Field Plates
Distribution of

Field Plated Structure

and

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[H Huang, et al., IEEE TPEL, 29 (5), 2164 (2014)] [W. Saito et al., IEEE TED, 50 (12), 2528 (2003)]
 Switching applications

• Small terminal capacitances

• Less reverse recovery charge
• Power loss is low
[X. Huang, et al., IEEE TPEL, 29 (5), 2453 (2014)]

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 Modeling GaN!

Modeling Strategy

Existing Models

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[L. Dunleavy et al., Microwave Magazine 11 (6), 82 (2010)]
 Modeling Continued…
Angelov model

Angelov Model Deficiencies

• Emperical model with ~ 90 parameters

• Fails to capture non-linear behaviour and

harmonic accuracy in power circuits

• Challenging to use for multiple device

dimensions
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[I. Angelov et al., IEEE T-MTT, 44 (10), 1664 (1996)] [I. Angelov et al., IEEE T-MTT, 40 (12), 2258 (1992)]
Status of Compact Model – GaN HEMT
Compact Model
GaN-HEMT

Table-Based Empirical Physics Based

Threshold- Surface-
Voltage Based Potential Based

Advanced SPICE Model for GaN HEMT device

CMC candidate models for industry standardization

(Two models are in final phase)
•ASM-HEMT model: Our model
•MIT Unified VS GaNFET (MVSG) model: MIT, Prof. D. Antoniadis
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 Advantages of SP-Based Model
• Better Model Scalability
• Device Insight
• Better Statistical Behavior
• Accurate Charges and Capacitances
• Better Temperature Scalability
• Less number of parameters
• Easier parameter extraction
• Uses a single expression for all regions
• Inherent Model Symmetry
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 ASM-HEMT Model Overview
Analytical Solution of 2-DEG Charge
Fermi-level (Ef),
Schrӧdiger’s & Poisson’s Surface-potential (SP)

SP-Based Id Ig & ChargeModel Accurate I-V and C-V

Physical parameters
Real Device effects included DIBL, Rs, VS, ...

Noise Model, Trapping Effects DC, AC, Transient

Harmonic Simulations,
Model, Self-Heating Noise etc.

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 ASM-HEMT Model Overview
Core Model

Analytical Solution of 2-DEG Charge

Fermi-level (Ef),
Schrӧdiger’s & Poisson’s Surface-potential (SP)

SP-Based Id, Ig & Charge

Model

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Assumptions:
Surface-Potential Calculation
• Quasi-constant electric field in the potential well (triangular well
approximation)
• Only the contribution of the first two sub-bands are important

Quasi-Fermi-potential and SP

• Basic device equations are transcendental in nature

• We divide variation of Ef with Vg into regions to develop fully
analytical expression
• Regional models are combined in one analytical expression
• No fitting parameters introduced, accuracy (order of nano-Volts)
S. Khandelwal, TED, VOL. 59, NO. 10, OCTOBER 2012
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 ASM-HEMT Model Overview

Mobility Temperature
CLM
Degradation Dependence

Bias Dependent
Series Resistance
Core Drain Current Complete Drain
Self-Heating Model Current Model

DIBL
Velocity Saturation Sub-threshold Slope

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 Drain-Current Model and
Intrinsic Charges
• We apply the drift-diffusion framework for carrier transport
• An analytical and continuous expression for the core drain-current is
developed including the velocity-field relation and mobility degradation
• Core Drain Current Model: • Ward-Dutton Partitioning for S/D charges
• Capacitances are calculated as derivatives of
the terminal charges: Cij=-dQi/dVj (i≠j),
Cii=dQi/dVi (i=j)

Charge conservation

• Velocity-Field relation and mobility-degradation:

 ds   d  s  m   d  s  2  sat   eff vsat L

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 is the CLM parameter
 Temperature Dependence

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 Model Parameter Extraction
Set L, W, NF, Tbar Obtain LAMBDA, Improve
Device Dimensions VSAT, ETA from IDVD

Obtain VOFF, NF, CDSCD,

ETA from log-IDVG, LINEAR Temperature Parameters
And Saturation

Obtain U0, UA, UB and RDS

Capacitance Modeling
from IDVG-LIN

Model Implemented in Verilog-A

Obtain VSAT, Improve ETA Simulations performed in: ADS,
From LINEAR IDVG Spectre, HSPICE
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 List of Main Parameters
Parameters Physical Meaning
U0 Low field Mobility
UA Mobility degradation parameter
UB Mobility degradation parameter
VOFF Cut-off Voltage of Device
• Physical Constants VSAT Saturation Velocity
• Simulation Conditions RTH Thermal Resistance
DIBL DIBL effect parameter
• Device dimensions
LAMBDA Channel length modulation
• Physically-Linked VOFFT Temperature dependence of Voff
Parameters UTE Mobility dependence of mu0
RS Source Side Resistance
RD Drain Side Resistance
….. …..

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 Importance of Rd/s Model
• Aggressive lateral scaling of source-drain access regions improve
the RF performance of GaN HEMT but at the cost of breakdown
voltage (BV)
• Too short Lgd increases electric field which is responsible for lowering
of BV
• Scaling of Lgd also affects the fmax due to increasing Cgd and gds of
device
• As a trade-off, a short Lgs and optimized Lgd is required to achieve
high fT , fmax and BV altogether

• In GaN HEMT, gate-to-drain/source access region works as

nonlinear resistance (Rd/s) which limits maximum drain current
• Accurate model of Rd/s is of great importance to predict the Id and
gm for high power as well as high frequency GaN HEMTs

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 Nonlinear source/drain access
region resistance model

Fig. 1: Nonlinear variation of source/ drain access

resistances with Ids extracted from TCAD
simulation and comparison with model.

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 Rd/s Model Validation with
Measurement
Effect of high access region
resistance at high Vg

Fig. 2: Id ‐ Vg and trans‐conductance for

the Toshiba power HEMT. Different slopes
above Voff in gm‐Vg: self‐heating governs
the first slope while velocity saturation in
access region affects second slope.

Fig. 3: (a) Ids‐Vds, (b) gds and (c) reverse Ids‐Vds fitting with
experimental data. The non‐linear Rs/d model shows correct
behavior for the higher Vg curves in the Id ‐ Vd plot; the S‐P based
model can accurately capture the reverse output characteristics.
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Modeling of Temperature dependence
The temperature dependence of Rd/s model is extremely important as it increases
significantly with increasing temperature

Temperature dependence of 2-DEG charge density in

the drain or source side access region:

Temperature dependence of Saturation Velocity:

Temperature dependence of electron Mobility:

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 Temperature Model Validation

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 Temperature Model Validation
Id‐Vg at three different temperatures 300, 365 and 425 K
RDS variation

VSAT variation

Mobility variation

VOFF variation
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 Temperature Model Validation
• Id-Vd at two different temperatures 300 and 573K
RDS Temperature dependences

VSAT variation

Mobility variation

VOFF variation

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Model Validation – IEMN France data

Lg = 0.125 µm, W=100 µm

Lg = 0.35 μm

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Modeling of Field-Plates in HEMTs

Affects capacitance and

breakdown behavior.

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Field-Plate Capacitance Modeling

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 Cross‐Coupling Capacitance
Both FPs

Appearance of fringing electric field between the

vertical wall of the GFP and the 2-DEGSFP causes
the cross-coupling effect giving rise to the second
plateau
Only GFP

Significant number of fringing field lines reach

the GFP through the insulator stack in the
absence of SFP causing more fringing capacitance

Both FPs
In the presence of the SFP, most of them end up at
the SFP leading to a reduced fringing capacitance
component in Cgd
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Substrate Capacitance
Vgs = −7 V Vds = 20 V

(a) Field lines originating from the 2-DEG reach the

substrate electrode leading to the existence of CSUBD

(b) whereas without substrate node, field lines from the

drain side of the 2-DEG terminate at the 2-DEG on
the source side through the GaN buffer

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 Current Collapse

Stephen Sque - ESSDERC tutorial Sept. 2013

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 Current Collapse

[S. DasGupta et al., Appl. Phys. Lett. 101 (24), 243506 (2012)] Stephen Sque - ESSDERC tutorial Sept. 2013
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 Issues-Virtual-gate effect

[R. Vetury et al., Trans. Elec. Dev. 48 (3), 560 (2001)] Stephen Sque - ESSDERC tutorial Sept. 2013
[T. Mizutani et al., TED 50, 2015 (2003)]
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 Issues-Buffer trapping

[E. Kohn et al., Trans. Microw. Theory Tech. 51 (2), 634 (2003)] Stephen Sque - ESSDERC tutorial Sept. 2013
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Pulsed IV Measurements

Vgq, Vdq
Vgq, Vdq
0, 0
‐8, 0
‐8, 0
‐8, 20

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Trap Model and Pulsed IV Scheme

The trapping effects are modeled with the help of two R-C sub-circuits. The generated trap voltages
Vtrap1 and Vtrap2 are fed back into the model which update parameters like the cut-off voltage, sub-
threshold slope, source and drain-resistances to capture the effects of traps.
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 Modeling of Trapping effect
Traps in GaN HEMTs play huge role in determining the performance of the device,
especially in high frequency operations

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 Switching Collapse Setup

Signal generator at gate terminal switches device from high negative stress voltage (Vgsq) to some value
higher than Voff . Variable resistor is used to make device working in linear region of operation.

 Waveform (i) is the input at the gate, which is switching the device from ON to OFF-state and vice
versa. Waveform (ii) is the constant input applied at drain terminal via a variable resistor.
 Waveform (iii) is showing the output drain current with time. The drain current is kept fixed at 0.3A
with the help of variable resistor.
 Waveform (iv) is the value of Vds which is equal to VDD when device is in OFF-state and becomes
Von when device is in ON-state.
 Waveform (iv) illustrates the fact that, as the device is turning ON, capacitor assumed for the trap-
states start to discharge and due to reduction in depletion of 2-DEG, Von of the device recovers with
time.
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 Switching Collapse Model

 Modeling of trapping effect by using RC network with different time constant. This RC network is
contributing to drain-access region resistance as Rtrap (as a function of Vtrap) to capture the trapping effect
on device ON-resistance (Ron)

 Model-Hardware correlation for pulsed I-V, Von data for 1, 5 and 10 kHz input applied at gate terminal for
various Vds. Von is the value of Vds at which the value of drain current is 0.3A. As VDD is increasing, Ron
of the device increases which results in switching collapse. Measured data is from Toshiba for CMC
standardization.

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Toshiba DC I-V Results for High
Power HEMT

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 Room Temperature I‐V
Id (A) (m/s) [E+0]
/

[LOG]
Gds' (A/V2) (m/s)
/

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 Reverse IdVd @ room temperature

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 Room Temperature I‐V

gm (mA/V)
Id (A)

gm’ (mA/V2)

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Log (Id) ‐ Vds (Vd>0) T=25 Log (Id) ‐ Vds (Vd<0) T=25

Id (A)

Log (Id) ‐ Vgs T=25

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Id (A) I‐V @ ‐20 deg C

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Rev IdVd @ T=150 C
Vg from ‐12 to 3 V @ 0.5V step

id (m/s) [LOG]
/
Lin‐Scale Log‐Scale

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Rev IdVd @ T=‐20 C
Vg from ‐12 to 3 V @ 0.5V step

Lin‐Scale Log‐Scale

gds' (m/s) [E-3]

/

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 I‐V @ ‐20 deg C

gm
Id (mA)

gm’
/
/

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 I‐V @ ‐20 deg C

Log ‐Scale

Id (A)

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 I‐V @ 100 deg C

Id (mA)
Id (mA)

Id (mA)

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 Temperature Scaling

Vd = 0.1, 0.5, 1 and 10V

Id (mA)

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 DC I-V Results of Multifinger
RF HEMT
Lg = 125 nm, Wg = 10 × 90 μm, Lsg = 200 nm, Ldg = 1.7 μm

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 DC Parameter Extraction Flow

S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics‐based Multi‐bias RF Large‐Signal GaN

HEMT Modeling and Parameter Extraction Flow", IEEE Journal of the Electron Devices Society, Sept. 2017.
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 12

RF Measurements
S-Parameters
• Easy for high frequencies (hard to do
open/short for Z/Y)
• Calculate other quantities
• Cascadable
• Transformation VNA Architecture
• Compatibility with simulation tools

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[Advanced Design System, Design Guide]
 13

De-embedding
De-embedding : Negating effects of unwanted portion

“Real” DUT SP= Measured SP–Fixture Characteristic

De-embedding is a mathematical process that removes the

effects of unwanted embedded portions of the structure
in the measured data by subtracting their contribution.

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[De-embedding Techniques in Advanced Design System, Agilent Manual]
Device Layout and Manifolds

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Equivalent Circuit Model at RF

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 Small Signal Modeling

Cgs Cgd

gm gds

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S. A. Ahsan, ..,Y. S. Chauhan, IEEE Journal of the Electron Devices Society, Sept. 2017.
 Impact of Gate Resistance
• Large resistors Rgs and Rgd – Capture the differential gate
resistance for current flowing through the gate-source and
gate-drain Schottky diodes.
• Their inclusion significantly impacts the overall gate
resistance (Rg) at low frequencies as shown in Fig.
• Rsub and Csub – Capture the substrate loss at the output port.
Total Rg

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S-Parameters
• Frequency: 0.5 −
50 GHz
• 2 different drain-
bias conditions,
with 10 different
gate biases (Id =
10 − 100 mA/mm)

Lines – Model
11/08/2017 Yogesh S. Chauhan, IIT Kanpur Symbols – Measured Data 74
 Y-Parameters

• The peaks and dips and their bias dependence is a

manifestation of the interaction between the intrinsic
capacitances and the extrinsic inductances.
• The values of bus-inductances can be fine-tuned to fit the
peaks/dips in measured and modeled extrinsic-level Y-
parameters.
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 RF Parameter Extraction Flow

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 16

Power Amplifier Design Goals

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 17

Load Pull Technique

Helps us:

• Determine Optimum load impedance for

maximum Pout and PAE performance

• Matching networks

• Understand tradeoffs!

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[M. S. Hashmi et. al, IEEE Instrum. Meas. Mag., 16 (2), Feb., (2013)]
Load-Pull Schematic & Overlays

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S. A. Ahsan, et. al, IEEE Trans. Microwave Theory Tech, 2017.
 Load Pull Contours

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Harmonic Balance Power Sweeps

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S. A. Ahsan, et. al, IEEE Trans. Microwave Theory Tech, 2017.
 Model Quality

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 Toshiba device Id and derivatives

ID

ID’ = GX
Smooth and continuous Id and its derivatives

ID’’ = GX’ ID’’’=GX’’

Full device (simulation)

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 Toshiba device
Intrinsic device (simulation)

Intrinsic device passes Gummel Symmetry Test

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 Characterization and Parameter
Extraction for RFMD RF 3931 Device
(Devices received from ISRO)

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 Summary
• Physics-based fully analytical model for the GaN
HEMTs
• Excellent agreement with the measured data at
different temperatures for different channel length
devices
• Model is implemented in the Verilog - A code
• Tested on Agilent ADS, Synopsys HSPICE and
Cadence’s Spectre simulators
• In final phase of industry standardization at CMC

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 My Group and Nanolab
Current members – 30
• Postdoc – 5 2017 2016 2015 2014 2013 2012
• Ph.D. – 17 Books
• Three PhD graduated
1 1
– Postdocs in UC Berkeley and U. Journal
Bordeaux France 20 18 9 5 3 3
Conference 8 30 30 8 4 6

Device Characterization Lab

‐ Pulsed IV/RF
‐ PNA‐X 43.5GHz
Funding in last 5 years: ‐ High Power IV
> Rs. 8.5 Crore
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 GaN-HEMT Journal Publications
1. S. A. Ahsan, A. Pampori, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "A New Small-signal Parameter
Extraction Technique for large gate-periphery GaN HEMTs", in IEEE Microwave and Wireless Components
Letters, Vol. 27, Issue 10, Oct. 2017.
2. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Multi-bias RF Large-Signal GaN
HEMT Modeling and Parameter Extraction Flow", in IEEE Journal of the Electron Devices Society, Vol. 5,
Issue 5, Sept. 2017.
3. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Pole-Zero Approach to Analyze and Model the
Kink in Gain-Frequency Plot of GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27,
Issue 3, Mar. 2017.
4. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Cross-Coupling and
Substrate Capacitance in GaN HEMTs for Power-Electronic Applications", IEEE Transactions on Electron
Devices (Special Issue), Vol. 64, Issue 3, Mar. 2017.
5. A. Dasgupta and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise in HEMTs", IEEE Microwave and
Wireless Components Letters, Vol. 26, Issue 6, June 2016.
6. S. A. Ahsan, S. Ghosh, A. Dasgupta, K. Sharma, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling in
Dual Field Plate Power GaN HEMT for Accurate Switching Behaviour", IEEE Transactions on Electron
Devices, Vol. 63, Issue 2, Feb. 2016.
7. A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for
HEMT circuit simulation", IEEE Microwave and Wireless Components Letters, Vol. 25, Issue 6, June 2015.
8. S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact
Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2,
Feb. 2015.
9. A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Compact Modeling of Flicker Noise in HEMTs", IEEE
Journal of Electron Devices Society, Vol. 2, Issue 6, Nov. 2014.
10. S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance
and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design", IEEE
Transactions on Electron Devices, Vol. 60, Issue 10, Oct. 2013.
11. S. Khandelwal, Y. S. Chauhan, and T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic
Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 8, Oct. 2012.
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GaN-HEMT Conference Publications
S. Khandelwal, S. Ghosh, S. A. Ahsan and Y. S. Chauhan, "Dependence of GaN HEMT AM/AM and AM/PM Non-Linearity on AlGaN Barrier Layer Thickness", IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur,
Malaysia, Nov. 2017.

2. S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Surface-potential-based Gate-periphery-scalable Small-signal Model for GaN HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), Miami, USA, Oct. 2017.

3. S. Ghosh, S. A. Ahsan, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "GaN HEMT Modeling for Power and RF Applications using ASM-HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India,
Dec. 2016.

4. S. Ghosh, A. Dasgupta, A. K. Dutta, S. Khandelwal, and Y. S. Chauhan, "Physics based Modeling of Gate Current including Fowler-Nordheim Tunneling in GaN HEMT", IEEE International Conference on Emerging Electronics
(ICEE), Mumbai, India, Dec. 2016.

5. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Statistical Simulation for GaN HEMT Large Signal RF performance using a Physics-based Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai,
India, Dec. 2016.

6. A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, N. Defrance, and Y. S. Chauhan, "Modeling DC, RF and Noise behavior of GaN HEMTs using ASM-HEMT Compact Model", IEEE International Microwave and RF Conference
(IMaRC), Delhi, India, Dec. 2016.

7. S. A. Ahsan, S. Ghosh, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Advanced SPICE Model for Gallium Nitride High Electron Mobility Transistors", International Conference of Young Researchers on Advanced
Materials (ICYRAM), Bangalore, India, Dec. 2016.

8. S. Ghosh, S. A. Ahsan, S. Khandelwal and Y. S. Chauhan, "Modeling of Source/Drain Access Resistances and their Temperature Dependence in GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC),
Hong Kong, Aug. 2016.

9. S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Modeling of Kink-Effect in RF Behaviour of GaN HEMTs using ASM-HEMT Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong,
Aug. 2016.

10. R. Nune, A. Anurag, S. Anand and Y. S. Chauhan, "Comparative Analysis of Power Density in Si MOSFET and GaN HEMT based Flyback Converters", IEEE International Conference on Compatibility and Power Electronics,
Bydgoszcz, Poland, June 2016.

11. S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec. 2015.

12. S. Ghosh, S. Agnihotri, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Trapping Effects in RF GaN HEMTs under Pulsed Conditions", International Workshop on Physics of Semiconductor Devices
(IWPSD), Bangalore, India, Dec. 2015.

13. S. Agnihotri, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Impact of Gate Field Plate on DC, C-V, and Transient Characteristics of Gallium Nitride HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD),
Bangalore, India, Dec. 2015.

14. K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec.
2015.

15. S. A. Ahsan, S. Ghosh, J. Bandarupalli, S. Khandelwal, and Y. S. Chauhan, "Physics based large signal modeling for RF performance of GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD),
Bangalore, India, Dec. 2015.

16. S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, T. A. Fjeldly and C. Hu, "Surface-Potential-Based RF Large Signal Model for Gallium Nitride HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), New Orleans,
USA, Oct. 2015.

17. S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", IEEE International Symposium on Compound Semiconductors (ISCS),
Santa Barbara, USA, June 2015.

18. A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.

19. S. Khandelwal, Y. S. Chauhan, B. Iniguez, and T. Fjeldly, "RF Large Signal Modeling of Gallium Nitride HEMTs with Surface-Potential Based ASM-HEMT Model", IEEE International Symposium on Compound Semiconductors
(ISCS), Santa Barbara, USA, June 2015. (Invited)

20. A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.

21. K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", IEEE Conference on Electron Devices and Solid-State Circuits
(EDSSC), Singapore, June 2015.

22. S. Ghosh, K. Sharma, S. Khandelwal, S. Agnihotri, T. A. Fjeldly, F. M. Yigletu, B. Iniguez, and Y. S. Chauhan, "Modeling of Temperature Effects in a Surface-Potential Based ASM-HEMT model", IEEE International Conference on
Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.

23. S. Agnihotri, S. Ghosh, A. Dasgupta, S. Khandewal, and Y. S. Chauhan, "A Surface Potential based Model for GaN HEMTs", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
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