Islamic University of Technology

Name : Abdur Rahman AL-Anam

Student ID : 220021301
Section : C
Department : Electrical and Electronic Engineering
Course Title : Electrical Circuit 1 (Software Lab)
Course No : 4102
Name of the experiment : Verification of KCL, KVL & Tellegen’s theorem and
Solving Mesh-Current Equations.
Experiment no : 02 (A, B, C & D)
Date of performance : 12/09/2023
Date of submission : 27/09/2023
Experiment No. : 02(A)
Experiment Name : VERIFICATION OF KCL.
Kircchoff's Current Law (KCL): The algebraic sum of currents entering any node equals
the sum of currents leaving the node.

Fig. 1
In the above figure, according to KCL: 𝐼1 + 𝐼3 = 𝐼2 + 𝐼4

Circuit diagram:

Fig. 2
The following figure shows the circuit of Fig. 2 drawn using Capture CIS:

Fig. 3
With bias point simulation in PSpice,

Fig.4
Current flowing through 𝑅1, 𝐼1 = 8.332 𝑚𝐴 Current flowing through 𝑅4, 𝐼4 = 2.934 𝑚𝐴
Current flowing through 𝑅2, 𝐼2 = 2.997 𝑚𝐴 Current flowing through 𝑅5, 𝐼5 = 2.197 𝑚𝐴
Current flowing through 𝑅3, 𝐼3 = 2.391 𝑚𝐴 Current flowing through 𝑅6, 𝐼6 = 3.129 𝑚𝐴

Again, the following figure shows the circuit of Fig. 2 drawn using Capture CIS after interchanging
1KΩ and 560Ω:

Fig. 5
With bias point simulation in PSpice,

Fig.6
Current flowing through 𝑅1, 𝐼1 = 12.51 𝑚𝐴 Current flowing through 𝑅4, 𝐼4 = 5.240 𝑚𝐴
Current flowing through 𝑅2, 𝐼2 = 2.997 𝑚𝐴 Current flowing through 𝑅5, 𝐼5 = 3.923 𝑚𝐴
Current flowing through 𝑅3, 𝐼3 = 4.270 𝑚𝐴 Current flowing through 𝑅6, 𝐼6 = 5.587 𝑚𝐴

Calculation:
From fig. 3,
For node 1, Incoming current 𝐼1 = 8.322 𝑚𝐴
Outgoing current 𝐼2 + 𝐼3 + 𝐼4 = (2.997 + 2.391 + 2.934) 𝑚𝐴 = 8.322 𝑚𝐴
∴ Incoming current = Outgoing current

For node 2, Incoming current 𝐼3+𝐼4 = (2.391 + 2.934) 𝑚𝐴 = 5.325 𝑚𝐴

Outgoing current 𝐼5 + 𝐼6 = (2.197 + 3.129) 𝑚𝐴 = 5.326 𝑚𝐴
∴ Incoming current ≈ Outgoing current
From fig. 5,
For node 1, Incoming current 𝐼1 = 12.51 𝑚𝐴
Outgoing current 𝐼2 + 𝐼3 + 𝐼4 = (2.997 + 4.270 + 5.240) 𝑚𝐴 = 12.507 𝑚𝐴
∴ Incoming current ≈ Outgoing current

For node 2, Incoming current 𝐼3+𝐼4 = (4.270 + 5.240) 𝑚𝐴 = 9.510 𝑚𝐴

Outgoing current 𝐼5 + 𝐼6 = (3.923 + 5.587) 𝑚𝐴 = 9.510 𝑚𝐴
∴ Incoming current = Outgoing current

Result:
For both node A and node B, the summation of incoming currents are equal to the summation of
the outgoing currents. Therefore, both the nodes abide by KCL.

Discussion:
Total number of incoming currents in a node of the given circuit is equal or approximately equal
to the summation of total outgoing currents. The slight variation is due to taking the near
approximate values. Hence, it can be said that, the experiment using Pspice simulation verifies
KCL.

Experiment No. : 02 (B)

Experiment Name : VERIFICATION OF KVL.
Kircchoff's Voltage Law (KVL): Around any closed path (or loop)
the algebraic sum of voltage rises equals the algebraic sum of the
voltage drops. Or, Kirchhoff’s voltage law (KVL) states that the
algebraic sum of allvoltages around a closed path (or loop) is zero.

Fig. 7
In the above figure, according to KVL: −𝑉1 + 𝑉2 + 𝑉3 − 𝑉4 + 𝑉5 = 0
Or, 𝑉2 + 𝑉3 + 𝑉5 = 𝑉4 + 𝑉1
Which implies, 𝑺𝒖𝒎 𝒐𝒇 𝒗𝒐𝒍𝒕𝒂𝒈𝒆 𝒅𝒓𝒐𝒑𝒔 = 𝑺𝒖𝒎 𝒐𝒇 𝒗𝒐𝒍𝒕𝒂𝒈𝒆 𝒓𝒊𝒔𝒆𝒔

Circuit diagram:

Fig. 8
The following figure shows the circuit of Fig. 8 drawn using Capture CIS:

Fig. 9
With bias point simulation in PSpice,

Fig.10

Voltage across 𝑅1, 𝑉1 = 𝐼1. 𝑅1 = 3.213 𝑉 Voltage across 𝑅2, 𝑉2 = 𝐼2. 𝑅2 = 0.9844 𝑉
Voltage across 𝑅3, 𝑉3 = 𝐼3. 𝑅3 = 0.80212 𝑉 Voltage across 𝑅4, 𝑉4 = 𝐼4. 𝑅4 = 1.78696 𝑉
Again, the following figure shows the circuit of Fig. 8 drawn using Capture CIS after interchanging
470Ω and 560Ω:

Fig. 11
 With bias point simulation in PSpice,

Fig.12

Voltage across 𝑅1, 𝑉1 = 𝐼1. 𝑅1 = 3.50 𝑉 Voltage across 𝑅2, = 𝐼2. 𝑅2 = 0.8252𝑉
Voltage across 𝑅3, 𝑉3 = 𝐼3. 𝑅3 = 0.6733 𝑉 Voltage across 𝑅4, 𝑉4 = 𝐼4. 𝑅4 = 1.50 𝑉

Data:
No of Observations Source Voltage Voltage Across (𝑉)
(𝑉) 𝑅1 𝑅2 𝑅3 𝑅4
1 5.00 3.213 0.985 0.802 1.787
2 5.00 3.500 𝑜. 826 0.673 1.499

Calculation:
From fig. 9,
For the first loop, Voltage drop = 𝑉1 + 𝑉4 = 5.00 𝑉
Voltage gain = 5.00 𝑉
∴Voltage drop = Voltage gain
For the second loop, Voltage drop = 𝑉2 + 𝑉3 = 1.78652 𝑉
Voltage gain = 𝑉4 = 1.78696𝑉
∴Voltage drop ≈ Voltage gain
From fig. 11,
For the first loop, Voltage drop = 𝑉1 + 𝑉4 = 5.00 𝑉
Voltage gain = 5.00 𝑉
∴Voltage drop = Voltage gain
For the second loop, Voltage drop = 𝑉2 + 𝑉3 = 1.4995 𝑉
Voltage gain = 𝑉4 = 1.5 𝑉
∴Voltage drop ≈ Voltage gain
Result:
For both circuits, the summation of voltage drop is equal to the summation of voltage gain in any
loop of a closed circuit. Therefore, both the circuits abide by KVL.

Discussion:
Total voltage drop is equal or approximately equal to the total voltage gain in every loop of the
given circuits. The slight variation is due to taking the near approximate values. Hence, it can be
said that, the experiment using Pspice simulation verifies KVL.
Experiment No. : 02 (C)
Experiment Name : VERIFICATION OF TELLEGEN’S THEOREM.
Tellegen’s Theorem: The algebraic sum of instantaneous powers for all branches in an electrical
network is zero. Or, The algebraic sum of powers delivered by all the sources is equal to the
algebraic sum of powers absorbed by all the elements in an electrical circuit at a particular instant.
Suppose, a network consists of ‘n’ number of branches. 𝐼1, 𝐼2, 𝐼𝑛 In are the instantaneous currents
flowing through each branch and . 𝑉1, 𝑉2, . . . . . . 𝑉𝑛 are the instantaneous voltages across each branch.
If these currents and voltages follow the Kirchhoff’s Current Law (KCL) and Kirchhoff’s Voltage
Law (KVL) respectively, then according to Tellegen’s theorem:
𝑛

∑ 𝑉𝐾 . 𝐼𝐾 = 0
𝐾=1
Here, 𝑉𝐾 is the instantaneous voltage across the kth branch and 𝐼𝐾 is the instantaneous current
flowing through this branch.

Using bias point simulation in PSpice on fig. 3,

Fig.13
Using bias point simulation in PSpice on fig. 9,

Fig.14
Calculation:
From fig. 13,
Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 = 83.22 𝑚𝑊 s
Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑 = 𝑃1 + 𝑃2 + 𝑃3 + 𝑃4 + 𝑃5 + 𝑃6
= 69.26 + 5.028 + 1.544 + 1.894 + 2.268 + 3.230 = 83.184 𝑚𝑊
∴ Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 ≈ Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑

From fig. 14,

Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 = 34.18 𝑚𝑊
Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑 = 𝑃1 + 𝑃2 + 𝑃3 + 𝑃4
= 21.97 + 5.701 + 3.590 + 2.925 = 34.186 𝑚𝑊
∴ Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 ≈ Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑
Result:
For both circuits, the summation of Supplied power is equal to the summation of Absorbed
power in any electrical circuit. Therefore, both the circuits abide by Tellegen’s theorem.

Discussion:
Total Supplied power is equal or approximately equal to the total Absorbed power in the given
circuits. The slight variation is due to taking the near approximate values. Hence, it can be said
that, the experiment using Pspice simulation verifies Tellegen’s theorem.

Experiment No. : 02 (D)

Experiment Name : SOLVING MESH-CURRENT EQUATIONS USING MATLAB
SOFTWARE.
Circuit diagram:

Fig.15
The mesh-current equations for the above circuit can be written as:

9i1 - 2i2 - 2i3 + 0i4 + 0i5 = 4

-2i1 + 10i2 -4i3 -i4 -i5 =6
-2i1 - 4i2 + 9i3 + 0i4 + 0i5=-6
0i1 - 1i2 + 0i3 + 8i4 - 3i5=0
0i1 - 1i2 + 0i3 - 3i4 + 4i5=-6
9 −2 −2 0 0 𝑖1 4
−1 ⎡ ⎤
−10 ⎢𝑖𝑖2 ⎥
In Matrix equation form: −2
−2
10
−4
−4
9 0 0 . 3 = −66
⎢ ⎥
⎢ 0 −1 0 8 −3 ⎥ ⎢𝑖4⎥ 0
[ 0 −1 0 −3 4 ] [𝑖5] [−6]
This matrix equation can be written as: 𝐴 ∗ 𝑖 = 𝐵
The mesh current vector ‘i’ can be calculated as: 𝑖 = 𝐴−1 ∗ 𝐵

MATLAB Code in Command Window:

Fig.16
Output in Command Window:

Fig.17
Result:
𝑖1 = 0.3829 𝐴
𝑖2 = 0.2110 𝐴
𝑖3 = −0.4878 𝐴
𝑖4 = −0.7184 𝐴
𝑖5 = −1.9860 𝐴

Discussion:
The new MATLAB software enabled us to perform the solution of lengthy and tough equations
very easily. Now we can solve various mesh-analysis problems with this software.

Assignment (i)
Circuit diagram:

Fig. 18

The following figure shows the circuit of Fig. 18 drawn using Capture CIS:

Fig. 19
With Bias Point simulation in PSpice,

Fig. 20
Calculation:
Node Voltages,
𝑉1 = 25.59 𝑉
𝑉2 = 22.05 𝑉
𝑉3 = 14.84 𝑉
𝑉4 = 15.06 𝑉
Verifying KCL,
For node 𝑉1, Incoming current = 4 𝐴
Outgoing current = 3.477 + 0.5234 = 4.0004 𝐴
∴ Incoming current ≈ Outgoing current
For node 𝑉2, Incoming current = 3.477 𝐴
Outgoing current = 2.756 + 0.7206 = 3.4766 𝐴
∴ Incoming current ≈ Outgoing current
For node 𝑉3, Incoming current = 21.49 + 720.6 = 742.09 𝑚𝐴
Outgoing current = 742.1 𝑚𝐴
∴ Incoming current ≈ Outgoing current
For node 𝑉4, Incoming current = 523.4 𝑚𝐴
Outgoing current = 21.49 + 501.9 = 523.39 𝑚𝐴
∴ Incoming current ≈ Outgoing current

Verifying KVL,
For the Top loop, Voltage drop = 20 × 0.5234 + 10 × 0.02149 = 10.6829 𝑉
Voltage gain = 10 × 0.7206 + 1 × 3.477 = 10.683 𝑉
∴Voltage drop ≈ Voltage gain
For the Middle loop,Voltage drop = 10 × 0.7206 + 20 × 0.7421 = 22.048 𝑉
Voltage gain = 8 × 2.756 = 22.048 𝑉
∴Voltage drop= Voltage gain
For the Left loop, Voltage drop = 1 × 3.477 + 8 × 2.756 = 25.525 𝑉
 Voltage gain = 25.53 𝑉
∴Voltage drop Voltage gain
For the Right loop, Voltage drop = 30 × 0.5019 = 15.057 𝑉
Voltage gain = 10 × 0.02149 + 20 × 0.7421 = 15.0569 𝑉
∴Voltage drop ≈ Voltage gain

Verifying Tellegen’s Theorem,

Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 = 102.1 𝑊 s
Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑 = 12.09 + 5.479 + 60.77 + 5.193 + 0.00462 + 11.01 + 7.557 = 102.1036 𝑊
∴ Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 ≈ Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑
Result:
1. Node Voltages,
𝑉1 = 25.59 𝑉
𝑉2 = 22.05 𝑉
𝑉3 = 14.84 𝑉
𝑉4 = 15.06 𝑉
2. KCL, KVL, Tellegen’s Theorem are verified.
 Assignment (ii)
Circuit diagram:

Fig. 21
The following figure shows the circuit of Fig. 21 drawn using Capture CIS:

Fig. 22

With bias point simulation in PSpice,

2 3
1

Fig. 23
Calculation:
Node Voltages,
𝑉1 = 10 𝑉
𝑉2 = 20 𝑉
𝑉3 = 30 𝑉
Verifying KCL,
For node 1, Incoming current = 5 𝐴
Outgoing current = 2.5 + 2.5 = 5 𝐴
∴ Incoming current = Outgoing current
For node 2, Incoming current = 5 𝐴
Outgoing current = 5 + 10−12 ≈ 5 𝐴
∴ Incoming current ≈ Outgoing current
For node 3, Incoming current = 2.5 𝐴
Outgoing current = 2.5 + 10−12 ≈ 5 𝐴
∴ Incoming current ≈ Outgoing current

Verifying KVL,
For the Top loop, Voltage drop = 2 × 5 + 2 × 10 × 10−12 ≈ 10𝑉
Voltage gain = 10.00 𝑉
∴Voltage drop ≈ Voltage gain
For the Bottom Super loop, Voltage drop = 4 × 2.5 + 2 × 5 + 2 × 10 ≈ 20 𝑉
Voltage gain = 8 × 2.5 = 20 𝑉
∴Voltage drop ≈ Voltage gain

Verifying Tellegen’s Theorem,

Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 = 100.0 + 25.0 = 125.0 𝑊 s
Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑 = 50 + 50 + 25 + (2 × 100 × 10−24) = 125.0 𝑊
∴ Σ𝑃𝑆𝑢𝑝𝑝𝑙𝑦 ≈ Σ𝑃𝐴𝑏𝑠𝑜𝑟𝑏𝑒𝑑

Result:
1. Node Voltages,
𝑉1 = 10 𝑉
𝑉2 = 20 𝑉
𝑉3 = 30 𝑉
2. KCL, KVL, Tellegen’s Theorem are verified.
 Assignment (ii)
Circuit diagram:

Fig. 24

The mesh-current equations for the above circuit can be written as;

170i1− 40i2 – 80i4= 24

−40i1+80i2−30i3−10i4= 0
−30i2+50i3−20i5= −12
−80i1−10i2+90i4= 10
−20i3+80i5= −10
170 −40 0 −80 0 𝑖1 24
⎡⎢𝑖 ⎤⎥ 0
In Matrix equation form: −40
80 −30 −10 0
0 −30 50 0 −20 . 𝑖23 = −12
⎢ ⎥
⎢−80 −10 0 90 0 ⎥ ⎢𝑖4⎥ 10
[ 0 0 −20 0 80 ] [𝑖5] [−10]
This matrix equation can be written as: 𝐴 ∗ 𝑖 = 𝐵
The mesh current vector ‘𝑖’ can be calculated as: 𝑖 = 𝐴−1 ∗ 𝐵

MATLAB Code in Command Window:

Fig.25
Output in Command Window:

Fig.26
Result:
𝑖1 = 0.4423𝐴
𝑖2 = 0.2219𝐴
𝑖3 = −0.1743 𝐴
𝑖4 = 0.5289 𝐴
𝑖5 = −0.1686 𝐴

Discussion:
From the experiments above we have practiced some simple electrical circuits construction and
simulation and also verified some theories through Capture CIS and PSpice. We also got familiar
with another software named MATLAB with which we could determine the current values very
easily.