Number Base Conversions

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Sure! Here's the solution for each of the 2-mark questions visible in the image:

1. Convert the following decimal numbers to the bases indicated.

a. 7562 to octal
→ 756210 = 165328
​ ​

b. 1936 to hexadecimal
→ 193610 ​
= 79016 ​

c. 175 to binary
→ 17510 ​ = 101011112 ​

2. Represent -43 (625) in binary representation using the given answer. Assume the
number is using 2's complement notation. Use 1 bit for sign, 15 bits for the integer
part and 10 bits for the fractional part.

Step 1: Convert +43.625 to binary:

43 in binary = `101011`

0.625 in binary = `.101` → because:

0.625 × 2 = 1.25 → 1
0.25 × 2 = 0.5 → 0
0.5 × 2 = 1.0 → 1
→ So, 43.625 = `101011.101`

Step 2: Normalize using 15 bits for integer and 10 bits for fractional: → `000000000010101.1010000000`
→ For -43.625: take 2's complement of the binary

1. Binary of +43.625 (25-bit format): `0000000000101011010000000`

2. 1’s complement: `1111111111010100101111111`
3. Add 1: `1111111111010100110000000`

Final answer: `1111111111010100110000000`

3. What floating-point representation of the number -5.33. Suppose the system is

using biased exponent with bias 16, 1 bit for sign, 5 bits for exponent, and 10 bits for

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fraction part.

Step 1: Binary of 5.33:

5 = `101`,

0.33 (approx) = `.0101011000`

→ `5.33` ≈ `101.0101011000`

Step 2: Normalize:
→ `1.0101011000 × 2^2`

Exponent = 2 + bias(16) = 18 = `10010`

Sign = 1 (since negative)

→ Final:
`1 10010 0101011000`

4. Determine the 8-bit signed binary number for this binary number 11100001
consisting of (i) Sign magnitude, (ii) 1’s complement and (iii) 2’s complement.

i. Sign magnitude
Sign bit = 1 → negative, magnitude = `1100001` = 97
→ So, = -97
ii. 1’s complement
Invert bits: `11100001` → original; flip to get positive = `00011110` = 30
→ So, = -30

iii. 2’s complement

Invert and add 1: `11100001` → Invert = `00011110` + 1 = `00011111` = 31
→ So, = -31

5. What is the length of the product register for signed multiplication if the length
of the multiplicand is ‘n’ and the length of the multiplier is ‘k’?

Answer:
Length of product register = n + k

6. Perform the arithmetic operations (+42) + (–13) and (–62) – (–13) in binary using
signed 2’s complement representation.

a. (+42) + (–13):

42 = `00101010`

-13 = 2’s complement of `00001101` = `11110011`

→ Add:

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 markdown

` 00101010
+ 11110011
------------
00011101 → 29
`

b. (–62) – (–13):

-62 = 2’s complement of `00111110` = `11000010`

-13 = `11110011`
→ Subtracting –13 = Adding +13 = `00001101`

markdown

` 11000010
+ 00001101
------------
11001111 → -49
`

7. Obtain the 1’s and 2’s complement of:

`10111010`, `10000001`, `10000000`, `00000001`, `00000000`

Let’s compute 1's and 2's complement:

Binary 1's Complement 2's Complement

10111010 01000101 01000110

10000001 01111110 01111111
10000000 01111111 10000000

00000001 11111110 11111111

00000000 11111111 00000000

8. Formulate a hardware procedure for detecting an overflow by comparing the

signs of the numbers being added and the result.

Answer:

Overflow occurs in signed binary addition if the carry into the sign bit ≠ carry out of the sign bit.
Procedure:
If two operands have same sign, but the result has a different sign → Overflow occurred
→ Check:
If (A_sign == B_sign) and (Result_sign ≠ A_sign) → Overflow

Let me know if you want solutions for the 5-mark or 10-mark questions next!

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 answer rest

Great! Let's continue with the remaining 2-mark questions from your image:

9. How many AND and OR gates are used to design the carry generator circuit of 4-
bit carry look ahead adder?

Answer:
In a 4-bit Carry Look-Ahead Adder:

4 AND gates to compute the Generate (G) signals.

4 AND gates to compute the Propagate (P) signals.

10 AND gates and 5 OR gates for the carry look-ahead logic to compute C1 , C2 , C3 , C4 .
​ ​ ​ ​

So, total:

18 AND gates

5 OR gates

10. Represent the Booth’s multiplier representation for the following:

(i) 7

(ii) -5

Using 4-bit Booth's encoding:

(i) 7 = 0111 → Booth's encoding = `0111 0`

(ii) –5 = 1011 → Booth's encoding = `1011 0`
(Booth’s algorithm typically appends an extra 0 as the previous bit)

11. Design a 1-bit full adder.

Answer:
A 1-bit Full Adder has:

Inputs: A, B, Cin
Outputs: Sum, Carry

Equations:

Sum = A ⊕ B ⊕ Cin

Carry = (A · B) + (Cin · (A ⊕ B))

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12. What are the advantages of 2’s complement representation over 1’s complement
representation?

Answer:

1. Only one representation for zero (unlike 1’s complement which has +0 and –0).
2. Simpler arithmetic operations, no need to handle end-around carry.

3. Efficient for hardware implementation (faster and easier to implement subtraction).

4. Better range: It can represent an extra negative number (e.g., –128 to +127 for 8-bit).

Let me know if you want the 5-mark or 10-mark answers next — happy to help!

answer till 20

Sure! Let's continue with the remaining 2-mark questions from your image — covering up to Question
20.

13. Design a 1-bit full adder with minimum time delay.

Answer:
To minimize delay, we can use optimized logic:

Sum = A ⊕ B ⊕ Cin → implemented using 2 XOR gates

Carry = AB + Cin(A ⊕ B) → implemented using AND and OR gates

Use fast logic gates and parallel computation for `A ⊕ B` and `AB`, then compute the carry using
minimal gate levels.

14. How many 2*1 muxes are used to design n-bit carry propagation adder.

Answer:
Each bit in an n-bit carry propagation adder requires:

One 2:1 MUX to choose between sum and carry

So, total:
→ n 2:1 MUXes for an n-bit carry propagation adder.

15. For 4-bit carry look ahead adder, write the formula to derive following:

a. Carry generation
b. Carry propagation
Answer:

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Let Ai , Bi be inputs.
​ ​

Carry Generate: Gi ​ = Ai ⋅ Bi
​ ​

Carry Propagate: Pi ​ = Ai ⊕ Bi
​ ​

16. Distinguish the speed of carry look ahead adder from delay.

Answer:

Carry Look Ahead Adder (CLA):

Uses parallel computation to reduce delay by computing carry bits in advance.

Faster than ripple-carry adder.

Ripple-Carry Adder:
Each bit waits for carry from previous stage.

Slower due to sequential carry propagation.

17. Discuss the disadvantages of two’s complement representation in subtraction.

Answer:

1. Overflow Detection Complexity: Overflow must be manually detected by sign analysis.

2. Limited Range: Asymmetric range (e.g., –128 to 127 for 8-bit).

3. Negative of most negative number not representable (e.g., –(–128) can't be represented in 8-
bit).

4. Sign extension needed when expanding to higher bits.

18. For (–5) × (–6) using Booth’s method, how many steps of addition and subtraction
are needed?

Answer:

Using Booth's algorithm:

Both numbers are negative:

–5 = 1011,
–6 = 1010

Depending on the Booth encoding of the multiplier:

For 4-bit Booth's multiplication, it typically takes at most n steps, where n = 4.

Exact count depends on pattern but likely 2 additions and 1 subtraction, based on bit transitions.

19. Write the rules of Booth’s algorithm and show how it handles +1 and –1.

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Answer:

Rules of Booth’s algorithm:

Look at current bit (Q₀) and previous bit (Q₋₁):

Q₀ Q₋₁ Operation

0 0 No operation
1 1 No operation

1 0 Subtract M
0 1 Add M

+1 → 01 → Add M

–1 → 10 → Subtract M

20. How carry propagation delay affects the performance of adders?

Answer:

In Ripple Carry Adders, carry must propagate from LSB to MSB.

This sequential propagation causes delay, limiting speed.

Larger bit-widths = more delay.

It affects performance especially in real-time and high-speed processors.

Let me know if you'd like help with the 5-mark or 10-mark questions next!

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 solve all without any bok bok

Sure. Here are the 5-mark answers with no extra explanations—just clean, direct solutions.

1. Q3-17. Arithmetic operations using 2’s complement.

(+70) + (+89):
+70 = `01000110`, +89 = `01011001`
→ Sum = `10011111` → Overflow (sign bit incorrect)

(+70) + (–80):
+70 = `01000110`, –80 = `10110000`
→ Sum = `11110110` = –10 → Valid

(–70) + (–89):
–70 = `10111010`, –89 = `10101111`

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 → Sum = `01101001` → Overflow (wrong sign)

2. Q3-20. Represent +46.5 as floating point binary with 8-bit mantissa, 4-bit
exponent.

46.5 in binary = `101110.1` → normalized = `1.011101 × 2^5`

Mantissa = `01110100` (after removing leading 1, padded to 8 bits)

Exponent = 5 + bias(7) = `1100`

Answer: 0 1100 01110100

3. Q3-21. A + B – 1 restores original value. What to do with end carry?

If after A + B, there is a carry-out, discard it (modulo-2^n arithmetic).

This restores original A when A + B is followed by adding 2’s complement of B.

4. Q6-9. Show E ⊕ Cn is overflow indicator using truth table.

A B Cin S Cout Overflow (Cn ⊕ Cn-1)

0 0 0 0 0 0
0 0 1 1 0 0

0 1 0 1 0 0
0 1 1 0 1 0

1 0 0 1 0 0

1 0 1 0 1 0
1 1 0 0 1 1 ← overflow

1 1 1 1 1 0

So, Overflow = Cout ⊕ Cn-1

5. Q10-22. Show no overflow in multiplication.

Multiplying n-bit × n-bit gives 2n-bit result.

So, result fits in 2n bits, thus no overflow occurs in multiplication.

6. Q10-14. Booth’s algorithm for –6 × +5

–6 = `1010`, +5 = `0101`, A = –6, Q = 5, Q-1 = 0

Step-by-step Booth’s:

Step A Q Q-1 Operation

Init 1010 0101 0 Initial setup

1 A–M Shift 1 Sub – Add A

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 Step A Q Q-1 Operation

2 Shift
3 A+M Shift 0 Add – Sub A

4 Shift
Final result in AQ = 1111110110 = –30

7. Q10-15. Flowchart for non-restoring division

If remainder ≥ 0, shift left and subtract divisor.

If remainder < 0, shift left and add divisor.

Repeat for n bits.

Set final remainder and quotient.

8. Q10-16. Base r multiplication product has ≤ 2n digits

True for base-r multiplication.

Two n-digit numbers yield at most 2n-digit product.

This is due to base power max: (rⁿ–1)(rⁿ–1) = r²ⁿ – 2rⁿ + 1

9. Q9. Algorithm to implement A-B if A and B are in 2’s complement

Take 2’s complement of B:

Invert bits

Add 1
Add result to A

Discard overflow

10. Q10. Circuit for binary division (restoring)

Steps:

Initialize remainder = 0

Shift left remainder and bring in quotient bit

Subtract divisor

If result < 0, restore, set quotient bit to 0

Else, set quotient bit to 1

11. Q10-13. Multiplying 6 × (–5) using Booth

6 = `0110`, –5 = `1011`

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 Step A Q Q-1 Operation

Init 0000 1011 0 Initial setup

1 A–M Shift 1 Subtract

2 Shift

3 Add
4 Shift

Result = –30

12. Q12. For restoration, shift must be ≥ 1

Restoration requires shift + correct sign

If less than 1 bit, no room to detect sign and fix remainder.

13. Q13. A = 10001101, B = 11110110. A × B using Booth

A = –115, B = –10
→ Result = 1150

Apply Booth’s step-by-step (not writing every row due to space). Final product: 0000010001111110

14. Q14. Partial product of multiplier stored in accumulator

Yes. Booth’s stores partial product in accumulator (A register).

Combines multiplicand shifts and accumulation efficiently.

15. Q15. 4-bit carry look-ahead adder: C0 to C4

C1 = G0 + P0C0

C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

16. Q16. Justify "To perform –5 × (+3) using Booth’s algorithm, addition done only
once"

Multiplier +3 = `0011` → transitions → one “01”

→ So, only 1 subtraction (once) and shifts.
→ Efficient for sparse bit patterns.

All done. Let me know if you want diagrams or further breakdowns.

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 solve

Here are the answers to the 10-mark questions based on the image. Straightforward, clean, and
complete.

1. Q10-3: Perform signed 2’s complement operations and check overflow

Use 8-bit representation for all calculations:

(a) (+25) + (+40)

25 = `00011001`, 40 = `00101000`
Sum = `00111001` = 65 → No overflow

(b) (+25) + (–40)

–40 = 2’s complement of 40 = `11011000`

Sum = `00011001` + `11011000` = `11110001` = –15 → No overflow
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(c) (–25) + (+40)

–25 = `11100111`, 40 = `00101000`

Sum = `00001111` = 15 → No overflow

(d) (–25) + (–40)

–25 = `11100111`, –40 = `11011000`

Sum = `10111111` = –65 → No overflow

(e) (–39) + (–40)

–39 = `11011001`, –40 = `11011000`

Sum = `10110001` = –79 → Overflow detected (sign flip)

2. Q10-18: Flowchart algorithm for signed number comparison (2's complement)

Method 1: Subtraction

1. Load A and B

2. Compute A – B using 2’s complement

3. If result = 0 → A = B
4. If MSB = 0 → A > B

5. If MSB = 1 → A < B

Method 2: Bitwise scan (MSB to LSB)

1. Scan A and B from MSB to LSB

2. At first differing bit:

If A = 1 and B = 0 → A > B
If A = 0 and B = 1 → A < B

3. If all bits equal → A = B

3. Q6-13: Perform A × B, A = 1001, B = 0001 (unsigned)

A = 9, B = 1

Binary multiplication (unsigned):

yaml

` 1001
× 0001
---------
1001 ← 1001 × 1
---------
1001
`

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Result: `00001001` (8-bit result)

4. Q10-23: Design an AND-array multiplier (4×4)

Steps:

1. Inputs: A (A3–A0), B (B3–B0)

2. Use AND gates to generate 16 partial products: Pi,j = Ai · Bj

3. Arrange partial products in matrix

4. Use binary adders (half & full adders) to add each column of the matrix diagonally

5. Carry propagated to next level

6. Result = 8-bit product (P7–P0)

Diagram layout:

4 rows of partial products

Ripple adder for each stage of summation

5. Q6-17: Booth’s algorithm – Multiply signed 2’s complement numbers

Let’s do each:

(a) A = 00011 (3), B = 10110 (–10)

Apply Booth's method → Result = –30

Binary = `11100010` (8-bit)

(b) A = 11001 (–7), B = 10100 (–12)

Result = 84 → `01010100`

(c) A = 11000 (–8), B = 00011 (3)

Result = –24 → `11101000`

(d) A = 01111 (15), B = 00111 (7)

Result = 105 → `01101001`

6. Q6-10: 16-bit carry-lookahead adder using four 4-bit CLAs

(a) Design Overview:

Use 4 × 4-bit CLAs (e.g., 74182 ICs)

Combine them using a look-ahead carry unit
Each block computes P and G, then pass carry to next

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(b) Logic Expression:

For 4-bit CLA:

C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3...

Total delay = 2 gate levels for carry

(c) Why not 32-bit ripple adder with 2×16-bit CLAs

Delay is linear in ripple adder

Carry delay from LSB to MSB

Using 4×4-bit CLAs allows parallel carry computation → much faster

Let me know if you want clean diagrams or flowcharts for any of these.

solve

Here are the answers for the questions from the image—neatly solved, no extra fluff:

6.5 – Half Adder & Full Adder

(a) Half Adder using two-level AND-OR circuit

Inputs: x, y
Outputs:

Sum (s) = x ⊕ y = (x̅ ·y + x·y̅ )

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 Carry (c) = x·y

So:

Use 2 AND gates: x̅ ·y and x·y̅

1 OR gate to get sum
1 AND gate for carry

(b) Full Adder using two Half Adders

Let inputs be x, y, Cin

1. First Half Adder:

s1 = x ⊕ y
c1 = x · y

2. Second Half Adder:

s = s1 ⊕ Cin
c2 = s1 · Cin

3. Final carry:
Cout = c1 + c2 (use OR gate)

(c) Longest logic delay path

In terms of gate levels:

Half Adder: XOR (2 gates), AND (1 gate)

Full Adder: Two XORs and one OR

So, maximum delay = 2 (XOR) + 2 (XOR + AND + OR) = 4 gate levels

8. Perform (+35) × (–5) using 2’s complement and minimum registers

+35 = `00100011`

–5 = `11111011` (2’s complement of 5)

Use Booth’s algorithm, assume 8-bit registers:

Multiplicand = 00100011

Multiplier = 11111011
Result = –175 → `10110001` (in binary: 2’s comp 8-bit)

Final result: –175

9. Design n-bit optimal carry propagation adder

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Using 2-input gates:

Carry-out equation:
`C_(n) = G_(n–1) + (P_(n–1) · G_(n–2)) + (P_(n–1) · P_(n–2) · G_(n–3)) + … + (P_(n–1) · P_(n–2)
·…· P_0 · C_0)`

Delay T(C_n):
Requires log₂(n) stages for parallel prefix addition (in optimized forms like Brent-Kung, Kogge-
Stone)
Delay T(S_n–1):
S = A ⊕ B ⊕ Cin → Needs 2 XOR stages
So, T(S_n–1) = delay(C_n) + 2

10. Differences

(a) Program Counter vs Memory Address Register

PC: holds address of next instruction

MAR: holds address to access memory (used by CPU)

(b) 1’s complement vs 2’s complement

Feature 1's Complement 2's Complement

Negation Invert bits Invert + add 1

Zeroes Two: +0, –0 Only one zero
Simpler Add/Sub ❌ ✅ preferred
(c) Instruction Register vs Memory Data Register

IR: stores instruction currently being executed

MDR: holds data read from or written to memory

11. Design 4-bit CLA and calculate T(C_n)

Given:

S_i = A_i ⊕ B_i ⊕ C_i

C_(i+1) = ((A_i ⊕ B_i) · C_i) + (A_i · B_i)

Each operation:

XOR = 2 gates

AND/OR = 1 gate

Breakdown:

First XOR: A_i ⊕ B_i → 2 units

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 Second: ⊕ with C_i → +2 units
Carry:

A_i ⊕ B_i = 2
AND with C_i = 1
A_i · B_i = 1

Final OR = 1

Total delay for C_(i+1): 2 (XOR) + 1 (AND) + 1 (AND) + 1 (OR) = 5 units

So, T(C_n) = 5 units

Let me know if you want diagrams or truth tables for visual clarity!

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