Computer Organization and Architecture

Code: SEng3022
Set by :
Molla K.
Computer Organization and Architecture

Chapter One

Introduction Digital Systems

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 Outline
 Basic Concepts of digital systems
 Logic gates
 Boolean Algebra
 Combinational circuit
 Flip Flops
 Sequential circuits

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 Basic Concepts of Digital Systems

 Digital Systems is a system in which signals have a finite number of discrete values.
 Analog system has values from a continuous set and mixed signal system has both Digital
and Analog parts.
 Generally, signals are represented by two methods, i.e., Digital and Analog System.
 Digital systems are designed to store, process, and communicate information in digital
form.
 They are found in a wide range of applications, including process control, communication
systems, digital instruments, and consumer products.

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 Computer Organization Vs Architecture
 Computer Organization : The way the hardware components are
connected to form a computer system.
 Computer Architecture : Structure and behavior of the various functional
units of the computer and their interactions.
 The digital computer is a digital system that performs various computational
tasks.
 A digital implies that the information in the computer represented by the
variables that take a limited number of discrete values.
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 Cont.
 Digital computer use the binary number system which has two digits 0 and 1.
 A binary digit is called a bit.
 Computer design is concerned with the development of hardware for the computer.
 It is concerned with structure and function of computer system.
 It is called computer implementation.

 The computer designer is concerned with structure and function characteristics of

computer system:
 Structure: The way in which the components are interrelated
 Function: The operation of each individual component as part of the structure
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 Cont.
Computers have four main structural Those Computers can perform four basic function:

components:  Data Processing

 Central processing unit (CPU)  Data Storage

 Main memory: Data Movement

 I/O
Control
 System interconnection

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 Cont.
There has two major functional entities of a computer:

1. System Hardware : consists all of the electronic components and electro mechanical devices

that comprises the physical entities of the devices.

 Hardware of the computer is divided in to three major parts:

1. CPU that contains:

 Arithmetic and Logic unit for manipulating data.

 Number of Registers for storing data.

 Control Circuit for fetching and executing instruction.

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 Cont.
2. RAM: it contains storage for instruction and data.

3. Input output processor (IOP): contains electronic circuit for communicating and controlling

transfer of information between the computer and outside world.

2. System Software : consists all instructions and data that the computer manipulate to perform

various data processing task.

 It consists all collection of the program whose purpose is to make effective use of the computer.

 It compensate for the difference between user need and capability of computer hardware.

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Cont.

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 Logic Gates
 Logic Gates
 A logic gate is an electronic device that produces a result based on input values.
 Logic gates are the basic building blocks of a digital computer.
 Binary information in digital computers represented by physical quantities called signal.
 Logic gates are digital circuits that have two or more logic inputs (except for NOT gate)
and produce a single output with a logic level based on the inputs.
 The manipulation of binary information is done by logic circuit called gate.
 Gate is the fundamental building block of hardware that produce signal of binary 1 or 0.
 The basic gates used in digital logic are AND, OR, NOT, NAND, NOR, and XOR.)
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 Cont.
1. AND gate : produce the AND logic function. It concatenate variables.
o The output is 1 if and only if both input A and B are otherwise, the output is 0.
2. OR gate: Produce the inclusive or function.
o The output is 1 if input A or B or both inputs are 1.
o Algebraic symbol is „+‟ similar to Arithmetic addition.
3. Inverter : the inverter circuit inverts the logic sense of a binary signal.
o It produce the NOT or complement function.

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 Cont.
4. NAND gate : Is the complement of AND function, is NOT-AND.

5. NOR gate: Is the complement of OR gate.

6. Exclusive-OR(XOR): Is called odd function.

o The output of XOR is 1 if any input is 1,but exclude the combination when both
inputs are 1.

7. Exclusive-NOR gate: Is called equivalence.

 It is complement of exclusive –or.

 The output is 1only if both input are 1 or both input are 0. 13
Cont.

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 Boolean Algebra
Boolean Algebra : is an algebra that deals with binary variables and logic operations.

 The possible values for a logical variable are either TRUE or FALSE.

 The logical operators of Boolean algebra are AND, OR, and NOT,
which are symbolically represented by dot (∙), plus sign (+), and over
bar (¯).

 Boolean algebra is used to facilitate the analyze and design of digital

circuits. 15
 Cont.
 Boolean Expressions : are made up of Boolean constants 0,1 and the three operations.
 Boolean Variables: are Boolean quantities whose values are not yet known.
 They can take the values 0 or 1 only.
 A Boolean function can be represented by a truth table and a logic diagram.
 A truth table is a table that describes the behavior of a logic gate

Example

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 Cont.
Example, F= x +y’z

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 Cont.
3.Dominance Laws:
1.Idempontency
x+1=1
x+x = x x.0=0

x.x = x 4.Involution Property

(x‟)‟=x
2.Identity Properties:
5.Commutativity
x+0=x x+y=y+x
y.x=x.y
x.1=x 18
 Cont.
9.Absorption
6.Associativity
x+xy=x
(x+y)+z=x+(y+z)=x+y+z
x(x+y)=x
(x.y).z=x.(y.z)=x.y.z
10.Adsorption
7.Complemetation
x+x‟y=x+y
x+x‟=1
x.(x‟+y)=xy
x.x‟=0
11.De Morgan’s laws
8.Distributive property
(x+y)‟=x‟y‟
x.(y+z)=x.y+x.z
(xy)‟=x‟+y‟
x+(y.z)=(x+y).(x+z)
 We always can reduce a Boolean function to its simplest form by using a number of Boolean laws can help us do so. 19
 Logic Expressions, Minimization, SOP, POS
Logic Expression: it is also called Boolean expressions are the result of applying logical (Boolean) operators
to relational or arithmetic expressions.

Example:1. Simplify the logic expression Example 2: show the following logic expression

(x+y) (x+y’) is equal to the simplified value.

A. x’y’+xy+x’y = X’ + xy
=x+xy’+xy+yy’
Exercises
=x(1+y) + xy+0
B. x’y +xy’+xy+x’y’ =1
=x+xy
C. x’+xy+xz’+xy’z’ = x’+xy+xz’
=x(1+y) =x D. A’BC+AB’C’+A’B’C’+AB’C+ABC = BC+B’C’+AB’
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 Sum-of-Products and Product-of-Sums expressions

Sums of Products Form(SOP)

 A Product term is any group of literals appearing either in complemented or
uncomplemented form, that are ANDed together.
 Two or more product terms are ORed together, to form a sum of products
expression.
 Example: F=AB+ACB+AC+BD where AB,ACB,AC and BD are product terms.

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 Sum-of-Products and Product-of-Sums expressions
Canonical Sum of Products
 A SOP expression is referred to as canonical sum of products expression if every product term involves
every literal or its complement.
Example: F=ABC+ABC+ACB+ABC , where ABC,ABC,ACB and ABC are the product terms involves all the
literals A, B and C.
Canonical Product of Sums
 A POS expression is referred to as canonical product of sums expression if every sum term involves every
literal.
Example :F= (A‟ +B ‟ +C ‟ +D ‟ )(A+B+C+D ‟ )
(A ‟ +A‟ B+C+D)(A+B+C‟ +D‟ )
Where (A ‟ +B ‟ +C ‟ +D ‟ );(A+B+C+D ‟ ); (A ‟ +B+C+D);
(A+B+C ‟ +D ‟ ) are sum terms involves all the literals A, B, C and D. 22
 Sum-of-Products and Product-of-Sums expressions

Non-Canonical SOP Form

 As the name suggests, this form is the non-standardized form of SOP expressions.
 The product terms are not the minterms but they are simplified. Let‟s take the above
function in canonical form as an example.
F = A̅B̅C + A̅BC̅ + A̅BC + AB̅C
F = A̅B̅C + A̅B (C̅ + C) + AB̅C
F = A̅B̅C + A̅B (1) + AB̅C
F = A̅B̅C + A̅B + AB̅C
 This expression is still in Sum of Product form but it is non-canonical or non-standardized
form.
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 Sum-of-Products and Product-of-Sums expressions

Minterm :
 A product term which contains each of „n‟ variables as factors in either complemented or in
complemented form is called a Minterm.
 A minterm is a logical expression of n variables that employs only the complement operator
and the product operator.
Maxterm :
o A sum term which contains each of „n‟ variables as factors in either complement form is called
a Maxterm.
o A maxterm is a logical expression of n variables that employs only the complement operator
and the sum operator. 24
 Sum-of-Products and Product-of-Sums expressions

Product of Sums Form (POS)

 A sum term is any group of literals appearing either in complemented or uncomplemented from that are ORed together.

 Two or more sum terms are ANDed together to form a product of sums expression.
Example: f(A,B,C)= (A+B) (A+B+C) (C+B) (B)

o f(A,B,C)= (A+B)(A+B+C)(C+B)(B) where A+B; A+B+C; C+B; and B are sum terms

 To better understand about POS we need to know about Maxterm.

 Maxterm means the term or expression that is true for a maximum number of input combinations or that is
false for only one combination of inputs.
 Since OR gate also gives false for only one input combination.
 So Maxterm is OR of either complemented or non-complemented inputs.
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 Sum-of-Products and Product-of-Sums expressions

Non-Canonical POS Form

 As the name suggests, this form is the non-standardized form of SOP expressions.

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Sum-of-Products and Product-of-Sums expressions

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 Two Types of Logic Circuits
Combinational Logic Circuit [CLC]
 Combinational circuit is an interconnected set of gates whose output at any
time is a function only of the input at that time.

 They serve as a basic building blocks for the construction of more complicated
arithmetic circuits.

 A combinational circuit consists of n- binary inputs and m- binary outputs.

 Common combinational circuit are, Adders (Half Adder, Full Adder & Multiple-
Bit Adder). 28
 Cont.
 Half Adder :A digital arithmetic circuit that carries out the addition of two bits is called a half adder.

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 Cont.
 Full Adder: adds two n-bit numbers along with a carry from a previous bitwise addition (performs addition of three
bits).

 A combination of two half adders creates a full adder.

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 Cont.
 Multiple-Bit Adder: By combining a number of full adders, we can have the necessary
logic to implement a multiple-bit adder.
 The output from each adder depends on the carry from the previous adder.

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 Sequential Logic Circuit [SLC]

 In case of combinational circuits, the value of each output depends on the values of
signals applied to the inputs.
 However, in case of Sequential Circuits, the values of the outputs depend not only on
the present values of the inputs but also on the past behavior of the circuit.
 Such circuits include storage elements that store the values of logic signals.
 A SLC consists of CLC and memory which stores the input data.
E.G. Counter, flip-flops.

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 Flip-flops
 The simplest form of sequential circuit is the flip- flops.
 The flip-flop is a bistable device, i.e. has two stable states.
 It exists in one of two states and, in the absence of input- function as a 1-bit memory.
 There are basically 4 types of flip-flops:

SR Flip-Flop

JK Flip-Flop

D Flip-Flop

T Flip-Flop

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 SR Flip Flop
 This is the most common flip-flop among all.

 This simple flip-flop circuit has a set input (S) and a reset input (R).

 In this system, when you Set “S” as active, the output “Q” would be high, and “ Q‘ ” would
be low.

 Once the outputs are established, the wiring of the circuit is maintained until “S” or “R” go
high, or power is turned off.

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 Cont.
 As shown below, it is the simplest and easiest to understand.

 The two outputs, as shown below, are the inverse of each other.

SR Flip Flop Circuit

 In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you give an active clock
signal. Otherwise, even if the S or R is active, the data will not change.
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 Cont.
AND NOR
A B Out put A B Out put clk S R S’ R’ Q Q’ Out put
0 0 0 0 0 1
0 x x 0 0 0 1 No Change
0 1 0 0 1 0
1 0 0 1 0 0
1 0 0 0 0 0 1 Memory
1 1 1 1 1 0

1 1 0 1 0 1 0 Set Q=1

1 0 1 0 1 0 1 Reset Q=0
S’ R’ Out put
0 0 No change
1 1 1 1 1 0 0 Not Allowed
1 0 Set Q=1
0 1 Rest Q=0
1 1 Not allowed

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 Cont.

 The first input condition in the table is R=0, S=0.

 Since 0 input has no effect on its output, the Flip-Flop retains its previous
state. Hence Q remains unchanged.

 The second input condition R=0, S=1 forces the output of NOR gate2 low.

 This low output will reach NOR gate1 and when both inputs of NOR gates1
is low, its inputs Q will be high.

 Thus, a 1 at the S input will SET the flip-flop and Q will be equal to 1.

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 Cont.
 The third input condition R=1, S=0 will force the output of NOR gate1 to
low.

 This low will reach NOR gate2 and forces its outputs to high. Hence, when
R=1, S=0, then Q=0, Q=1. Thus, the flip-flop is RESET.

 The last input condition in the table R=1, S=1 is forbidden since it forces
both the NOR gates to the low state, means both Q=0, and Q=0 at the
same time, which violets the basic definition of flip-flop that requires Q to
be the complement of Q.

 Hence, this input condition is forbidden and its output is unpredictable.

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Cont.

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 Cont.
Clock Input:
 For synchronization of operation of multiple flip-flop, an additional signal is added to all types of flip-flop
which is called clock signal, generally abbreviated as CLK.

 Addition of CLK signal ensures that, whatever may be the input to the flip-flop, it effects the output only
when CLK signal is given. Fig. 1.16 shows a clocked RS flip-flop.

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 D Flip-flop
 It is a modification of RS flip-flop.

 In RS flip-flop when both the inputs are high i.e., R=1, S=1, the output becomes unpredictable and this
input combination is termed as forbidden.

 To avoid this situation, the RS flip-flop is modified so that both the inputs can not be same at a time.

 The modified flip-flop is called D flip-flop. Fig 1.17 shows a clocked D flip-flop.

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 Cont.
 In D flip-flop both inputs of RS flip-flop are combined together to make it one by a NOT
gate so that inputs can not be same at a time.

 Hence in D flip-flop there is only one input. The truth table is:

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 Cont.

 In a clocked D flip-flop the value of D cannot reach the output Q when the clock pulse
is low. During a low clock, both AND

 Gates are disabled. Therefore, D can change value without affecting the value of Q. On
the other hand, when the clock is high , both AND gates are enabled.

 In this situation, Q is forced to be equal to the value of D.

 In another way we can say that in the D flip-flop above, Q follows the value of D while the
clock is high.

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 JK Flip-Flop
 In RS flip-flop, the input R= S=1 is called
forbidden as it causes an unpredictable
output.

 In JK flip-flop this condition is used by changing

Fig 1.18 shows one way to build a JK flip-flop.
the RS flip-flop in some way.

 In JK flip-flop both input can be high

simultaneously and the corresponding toggle
output makes the JK flip-flop a good choice to
build counter- a circuit that counts the number of
+ve or –ve clock edges.
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 Con’t
clk J K S R Q Q’ Out put
NAND Gate
0 x x 1 1 0 1 No Change
A B out
1 0 0 1 1 0 1 No Change
0 0 1
1 1 0 0 1 1 0 Set Q=1
1 0 1
1 0 1 1 0 0 1 Reset Q=0
0 1 1
1 1 1 1 0 0 1 Toggle
1 1 0

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 Cont.
 The inputs J and K are called control inputs because their combinations decide what the
output of JK flip-flop will be when a +ve clock pulse arrives.

 When J and K are both low, both the AND gates are disabled. Therefore, the CLK pulse
has no effect.

 The first input combination of the truth table shows this and under this case the output Q
retains its last state.

 When J is low, K is high , the upper AND gate is disabled while the lower AND gate is
enabled. Hence the flip-flop cannot be set; instead it is reset, i.e. Q=0. This is shown by the
second entry in the truth table.
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 Cont.
 When J is high, K is low the upper AND gate is enabled while the lower one is disabled. So the flip-flop is set there by

making Q =1.

 When J and K are both high , then the flip-flop is set or reset depending on the previous value of Q.

 If Q is high previously, the lower AND gate sends a RESET trigger to the flip-flop on the next clock pulse.

 Then Q becomes equal to 0. On the other hand, if Q is low previously, the upper AND gate sends a SET trigger on the

flip-flop making Q=1.

 So, when J = K = 1, Q changes its value from 0 to 1 or 1 to 0 on the positive clock pulse. This changing of Q to Q is

called toggle.

 Toggle means to change to the opposite state.

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 Cont.
 Any flip-flop may be driven by +ve as well as –ve clock. As such JK flip-flop can also be
driven by positive clock as well as negative clock. Fig 1.19 shows symbol of positive
clocked and negative clocked JK flip-flop.

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 T Flip-Flop
 A T flip-flop is like a JK flip-flop. These are basically single-input versions of JK flip-flops.

 This modified form of the JK is obtained by connecting inputs J and K together.

 It has only one input along with the clock input.

 These flip-flops are called T flip-flops because of their ability to complement their state i.e. Toggle, hence they
are named Toggle flip-flops.

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 Chapter Summary Examples
Simplify Boolean function
1.

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 Simplify Boolean function

 It is easy to convert a function to sum-of-

products form from its truth table
=> We only interested in the production of the
inputs which yields TRUE (=1).
We first highlight the lines that result in 1.
Then, we group them together with OR.

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3. Convert ABC+A'BC+AB'C+A'B'C+ABC„ to its simplest form

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4. Simplify CLC via Boolean Algebra

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CON…

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5. Simplify the following circuits

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Con….

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 Con….

6. How could Boolean function be used in computer?

7. What stacking logic gate ?

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