SESHADRI RAO GUDLAVALLERU ENGINEERING COLLEGE

(An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)

Seshadri Rao Knowledge Village :: Gudlavalleru -521356

Academics Strengthening & Advancement (AS&A)

Department of Electronics and Communication Engineering

R – 23
II B.Tech. I Semester

DIGITAL LOGIC AND COMPUTER ORGANIZATION

Learning Material

Prepared by: Faculty of ECE

R-23 DIGITAL LOGIC DESIGN AND COMPUTER ORGANIZATION II B.Tech - I Sem
DIGITAL LOGIC & COMPUTER ORGANIZATION
(Common to CSE, IT, AI&DS, CSE(AI&ML))
II Year I Semester
Lecture : 3 Internal Marks : 30
Credits : 3 External Marks : 70
Course Objectives:

The main objectives of the course is to

• provide students with a comprehensive understanding of digital logic design principles and
computer organization fundamentals
• Describe memory hierarchy concepts
• Explain input/output (I/O) systems and their interaction with the CPU, memory, and
peripheral devices

Course Outcomes:

Upon successful completion of the course, the students will be able to

• represent data in Binary form, minimize logical expressions and design logic circuits using
logic gates.
• design combinational and sequential logic circuits
• demonstrate basic structure and functional units of a computer.
• perform arithmetic operations on signed and unsigned numbers
• explain input/output (I/O) systems and their interaction with the CPU, memory, and peripheral
devices

UNIT–I:
Data Representation: Binary Numbers, Fixed Point Representation. Floating Point representation.
Number base conversions, Octal and Hexadecimal Numbers, Complements, Signed binary numbers,
Binary codes
Digital Logic Circuits-I: Basic Logic Functions, Logic gates, universal logic gates, Minimization
of Logic expressions. K-Map Simplifications (up to 4 variables), Combinational Circuits: Decoders,
Multiplexers

UNIT–II:
Digital Logic Circuits-II: Sequential Circuits, Flip-Flops, Registers, Shift Registers: Uni-
directional, Bi-directional, Universal, Binary counters, Ripple counters

Seshadri Rao Gudlavalleru Engineering College Dept. of ECE AS&A A.Y.:2024-25

R-23 DIGITAL LOGIC DESIGN AND COMPUTER ORGANIZATION II B.Tech - I Sem

UNIT–III:
Basic Structure of Computers: Functional units, Basic operational concepts, Bus structures, Multi
processors, Multi computers, Von- Neumann Architecture.
Computer Arithmetic: Addition and Subtraction of Signed Numbers, Design of Full Adders,
Multiplication of Positive Numbers, Signed-operand Multiplication, Integer Division, Floating-
Point Numbers and Operations.

UNIT–IV:
Processor Organization: Fundamental Concepts, Execution of a Complete Instruction, Multiple-Bus
Organization, Hardwired Control and Micro programmed Control.
Memory Organization: Basic Concepts, Semiconductor RAM Memories, Read-Only Memories,
Speed, Size and Cost, Cache Memories, Performance Considerations, Virtual Memories, Memory
Management Requirements, Secondary Storage.

UNIT–V:
Input/Output Organization: Accessing I/O Devices, Interrupts, Processor Examples, Direct
Memory Access, Buses- synchronous bus, asynchronous bus.

Textbooks:
1. Computer Organization, Carl Hamacher, Zvonko Vranesic, Safwat Zaky, 6thedition, McGraw
Hill, 2023.
2. Digital Design, 6thEdition, M. Morris Mano, Pearson Education, 2018.
3. Computer Organization and Architecture, William Stallings, 11thEdition, Pearson, 2022.

Reference Books:
1. Computer Systems Architecture, M. Moris Mano, 3rdEdition, Pearson, 2017.
2. Computer Organization and Design, David A. Paterson, John L. Hennessy, Elsevier, 2004.
3. Fundamentals of Logic Design, Roth, 5thEdition, Thomson, 2003.

Online Learning Resources:

https://nptel.ac.in/courses/106/103/106103068/

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INDEX

Topic Name Page No.

UNIT - I : DATA REPRESENTATION AND DIGITAL CIRCUITS-I

1.1 Binary numbers 3

1.2 Fixed point Representation 3
1.3 Floating point Representation 3
1.4 Number Base Conversions 4
1.5 Octal and Hexadecimal numbers 8
1.6 Complements 9
1.6.1 Radix and Diminished Radix Complement 9
1.6.2 Subtraction with Complements 11
1.7 Signed Binary Numbers 12
1.7.1 Number Representation 12
1.7.2 Arithmetic Addition 13
1.7.3 Arithmetic Subtraction 13
1.8 Binary Codes 15
1.8.1 Binary Coded Decimal Numbers 19
1.8.2 BCD Addition 20
1.8.3 Other Decimal codes 20
1.8.4 Gray Code 21
1.9 Basic Logic Functions 23
1.9.1 Postulates and Theorems 23
1.10 Logic Gates 31
1.10.1 Logic Gates 31
1.10.2 Gates Implementation of Expressions 35
1.11 Universal Logic Gates 35
1.11.1 NAND,NOR 35
1.11.2 Gates Realization using NAND,NOR 38
1.12 Minimization of Logic Expressions 38
1.12.1 Example 39
1.13 K-Map Simplifications 39
1.13.1 2-Variable K Map 40
1.13.2 3-Variable K Map 41
1.13.3 4-Variable K Map 42
1.13.4 Don’t Care Conditions 43
1.14 Combinational Circuits 43
1.14.1 Design Procedure (code conversion) 44
1.14.2 Half Adder, Half Subtractor 47
1.14.3 Half Subtractor, Full Subtractor 79
1.15 Decoders 51
1.15.1 3x8 Decoder 52
1.15.2 4x16 with two 3x8 Decoders 53
1.16 Multiplexers 57

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1.16.1 2x1,4x1 Multiplexers 57
1.16.2 Boolean Function Implementation 59

UNIT II : DIGITAL LOGIC CIRCUITS -II

2 Introduction 78
2.1 Sequential Circuits 79
2.2 Flip-Flops 81
2.2.1 RS Flip-Flop 81
2.2.2 D-Flip-flop 82
2.2.3 JK Flip Flop 83
2.2.4 T Flip-Flop 84
2.2.5 Race around Condition and Solution 85
2.2.6 Flip-Flop Excitation Table 87
2.3 Register 88
2.4 Shift Registers 90
2.4.1 Bidirectional Shift Registers 92
2.4.2 Universal Shift Register 93
2.4.3 Applications of Shift Registers 94
2.5 Binary Counters 94
2.5.1 Types of Binary Counters 95
2.6 Ripple Counter 95
2.6.1 Binary Ripple Counter 96
2.6.2 Design of Asynchronous BCD Counter 98
2.6.3 Design of a Mod-6 asynchronous counter using T FFs 100
2.7 Synchronous Counters 101
2.7.1 Binary Counter 101
2.7.2 Procedure to design synchronous counters 102
2.7.2.1 Design of two-bit synchronous counter using T flip flop 102
2.7.2.2 Design of 4-bit synchronous up counter using T flip
104
flop

UNIT-III: BASIC STRUCTURE OF COMPUTERS

3.1 Functional units 114

3.1.1 Functional units of computer 114
3.1.2 Input unit 115
3.1.3 Memory Unit 115
3.1.4 Arithmetic and Logic Unit 116
3.1.5 Output unit 116
3.1.6 Control Unit 116
3.2 Basic operational concepts 117
3.3 Bus structures 119
3.4 Multiprocessors & multi computers 120
3.5 Von- Neumann Architecture 120
3.6 Addition and Subtraction of Signed Numbers 121

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3.6.1 Logic Specification 122
3.6.2 Addition/subtraction logic unit 123
3.7 Design of Full adders 123
3.7.1 n bit ripple carry adder 124
3.7.2 cascade of k n-bit adders 124
3.8 Multiplication of Positive Numbers 124
3.8.1 Array Multiplication 125
3.8.2 Register configuration 126
3.8.3 Multiplication Example 127
3.9 Signed-operand Multiplication 127
3.9.1 Booth Algorithm with example 128
3.10 Integer Division 130
3.10.1 Circuit arrangement 131
3.10.2 Restoring Division with example 132
3.10.3 Non restoring division 133
3.11 Floating-Point Numbers and Operations 134
3.11.1 IEEE format 135
3.11.2 Special values, Exceptions 136
3.11.3 Arithmetic operation on floating point numbers 137

UNIT -IV: PROCESSOR AND MEMORY ORGANIZATION

4.1 Fundamental Concepts 151

4.1.1 Single Bus organization of Processor 152
4.1.2 Register Transfers 153
4.1.3 Performing an Arithmetic or Logic Operation 154
4.1.4 Fetching a Word from Memory 155
4.1.5 Storing a word in Memory 156
4.2 Execution of a Complete Instruction 156
4.2.1 Executing an Instruction 157
4.2.2 Branch Instruction 158
4.3 Multiple-Bus Organization 159
4.4 Hardwired Control and Micro programmed Control 161
4.4.1 Hardwired Control 161
4.4.2 Micro programmed Control 164
4.5 Basic Concepts 168
4.5.1 Cache and Virtual Memory 170
4.6 Semiconductor RAM Memories 170
4.6.1 Internal Organization of Memory Chips 170
4.6.2 Static Memories 172
4.6.3 Asynchoronous Dynamic RAMs 174
4.6.4 Synchronous DRAMs 177
4.7 Read-Only Memories 179
4.7.1 PROM 180
4.7.2 EPROM 180
4.7.3 EEPROM 181

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4.7.4 Flash Memory 181
4.8 Speed, Size and Cost 182
4.9 Cache Memories 185
4.9.1 Mapping Functions 187
4.9.2 Replacement Algorithms 191
4.10 Performance Considerations 192
4.10.1. Interleaving 192
4.10.2 Hit Rate and Miss Penalty 194
4.11 Virtual Memories 195
4.11.1 Virtual Memory Organization 196
4.11.2 Address Translation 197
4.11.3 Translation Lookaside Buffer 199
4.11.4 Page Faults 200
4.12 Memory Management Requirements 202
4.13 Secondary Storage 203
4.13.1 Magnetic Hard Disks 203
4.13.2 Optical Disks 206
4.13.3 Magentic tape System 208

UNIT-V: INPUT-OUTPUT ORGANIZATION

5.1 Accessing I/O Devices 217

5.1.1 Memory mapped I/O 218
5.1.2 I/O mapped I/O 218
5.1.3 Program Controlled I/O 219
5.1.4 Mechanisms Used For Interfacing I/O Operations 219
5.2 Interrupts 219
5.2.1 Interrupt Hardware 220
5.2.2 Enabling and Disabling Interrupts 221
5.3 Processor Examples 223
5.3.1 ARM Interrupt Structure 223
5.3.1.1 Introduction to ARM 223
5.3.1.2 Sources for Exceptions in ARM 224
5.3.2 68000 Interrupt Structure 226
5.3.2.1 Introduction 226
5.3.2.2 Interrupt structure 228
5.4 Direct Memory Access 229
5.4.1 Modes of DMA Transfer 230
5.4.2 Use of DMA Controller 230
5.4.3 Bus Arbitration 231
5.4.3.1 Centralized Arbitration 231
5.4.3.2 Distributed Arbitration 232
5.5 Buses 233
5.5.1 Synchronous Bus 234
5.5.2 Asynchronous Bus 236

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R-23 DIGITAL LOGIC AND COMPUTER ORGANIZATION II B.TECH I -Sem

UNIT-1
DATA REPRESENTATION AND DIGITAL CIRCUITS-I
Course Objectives:
• To familiarize with the concepts of different number systems and codes.
• To understand the representation and operations on floating-point numbers
• To understand the representation and Arithmetic operations using complements
• To understand the operation of Boolean algebra and logic gates
• To learn K-map method
• To understand various combinational logic circuits.
Course Outcomes:
Students will be able to

• understand various number systems.

• perform the arithmetic operations using complementary methods.
• understand basic theorems and properties of Boolean algebra.
• understand basic logic operations and gates.
• Determine the minimized Boolean function using K-maps
• Design adders and subtractors.
• Understand other combinational circuits like decoder, multiplexer
Syllabus:

1.1 Binary Numbers

1.2 Fixed Point Representation
1.3 Floating Point Representation
1.4 Number Base Conversions
1.5 Octal and Hexadecimal Numbers
1.6 Complements
1.6.1 Radix and Diminished Radix Complement
1.6.2 Subtraction with Complements
1.7 Signed Binary Numbers
1.7.1 Number Representation
1.7.2 Arithmetic Addition
1.7.3 Arithmetic Subtraction

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1.8 Binary Codes

1.8.1 Binary Coded Decimal Numbers
1.8.2 BCD Addition
1.8.3 Other Decimal codes
1.8.4 Gray Code
1.9 Basic Logic Functions
1.9.1 Postulates and Theorems
1.10 Logic Gates
1.10.1 Logic Gates
1.10.2 Gates Implementation of Expressions
1.11 Universal Logic Gates
1.11.1 NAND,NOR
1.11.2 Gates Realization using NAND,NOR
1.12 Minimization of Logic Expressions
1.12.1 Example
1.13 K-Map Simplifications
1.13.1 2-Variable K Map
1.13.2 3-Variable K Map
1.13.3 4-Variable K Map
1.13.4 Don’t Care Conditions
1.14 Combinational Circuits
1.14.1 Design Procedure (code conversion)
1.14.2 Half Adder, Half Subtractor
1.14.3 Half Subtractor, Full Subtractor
1.15 Decoders
1.15.1 3x8 Decoder
1.15.2 4x16 with two 3x8 Decoders
1.16 Multiplexers
1.16.1 2x1,4x1 Multiplexers
1.16.2 Boolean Function Implementation

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1.1Binary Numbers
• According to digital electronics and mathematics, a binary number is defined as a
number that is expressed in the binary system or base 2 numeral system. It describes
numeric values by two separate symbols; 1 (one) and 0 (zero). The base-2 system is the
positional notation with 2 as a radix.
• The binary system is applied internally by almost all latest computers and computer-
based devices because of its direct implementation in electronic circuits using logic
gates. Every digit is referred to as a bit.

• Binary: allowed digits(0, 1), Radix -2

• The number of numerical values the system uses is called the Base or Radix of the
system

1.2 Fixed Point Representation

• A fixed-point binary number will be stored in a given number of bits called the word
length. Some of the bits in the word would be used for the integer part and the rest of
them for the fractional part. In addition, a bit would also be used to signify the sign of
the number.
• Example:Given that a fixed- point positive binary number is stored in eight bits word
length, where the first six bits are used for the integer part and the next two for the
fractional part, how would the number (13.875)10 is stored ?
• We are given (13.875)10.
• 13 is represented as 1101 and 0.875 =.111
• By fixing 6 bits for integer and 2 bits for fractional the answer will be (001101.11)2.
Two zeros are appended for integer part and one bit is truncated from fractional part.

1.3 Floating Point Representation

• A floating point number in computer registers consists of two parts: a mantissa m and an
exponent e.
• The two parts represent a number obtained from multiplying m times a radix r raised to
the value of e.
• m x re
• The mantissa may be a fraction or an integer. The location of the radix point and the
value of the radix r are assumed and are not included in the registers.

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• For e.g., the decimal number +6132.789 is represented in floating point with a fraction
and exponent as follows:
Fraction Exponent
+0.6132789 +04
• The above representation is equivalent to scientific notation +0.6132789 X 104
• A floating point binary number is represented in a similar manner to floating point
decimal number except that it uses base 2 for exponent.
• For e.g., the binary number +1001.11 is represented as 8-bit fraction and 6-bit exponent
as follows:
Fraction Exponent
01001110 000100

1.4 Conversion of numbers from one radix to another radix

• To convert among different number systems. We use decimal numbers every day.
Computers understand only binary numbers, which are lengthy and inconvenient to
human beings. Octal and Hexadecimal numbers are introduced to make both happy:
they are easier to be converted to binary numbers and also easier for us to handle.

Fig 1.1 Classification of numbers

Unsigned Numbers
Radices and Characters:
• Binary : 0, 1
• Decimal : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
• Octal : 0, 1, 2, 3, 4, 5, 6, 7
• Hexadecimal : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

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Structure of a number:

Note: If no fractional part, the radix point can be omitted!

Positional Notation or representation of numbers:

N = d n −1 r n −1 + d n − 2 r n − 2 +  + d 1 r 1 + d 0 r 0 + d −1 r −1 + d − 2 r −2 +  + d − m r − m
where d i  0,1,2, r − 1, i  n − 1, n − 2,  2,1,0,−1,−2,  − m, and r is the radix.

The number of numerical values the system uses is called the Base or Radix of the system
Table 1.1 Allowable digits in different number systems

Conversion from given base to Decimal:

• Write the number using the positional notation and then perform decimal arithmetic to
compute the result, which is the decimal number.
• Example: Given the positional notations of the following numbers: (1101.1)2, (724)8,
and (BCD)16.

• (4021.2)5 = 4 x 53 + 0 x 52 + 2 x 51 + 1 x 50 + 2 x 5-1 = (511.4)10

4 x 125 + 0 + 10 + 1 + 2 x (1/5)
500 + 11 + .4

• (B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160 = (46687)10

11 x 4096 + 6 x 256 + 5 x 16 + 15
45056 + 1536 + 80 + 15
• (1010.011) 2 = 23 + 21 + 2-2 + 2-3 = (10.375) 10
• (630.4) 8 = 6 x 82 + 3 x 81 + 0 x 80 + 4 x 8-1 = (408.5) 10

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Conversion from Decimal to given base:

• Integer part: Divide the decimal number by the base to which we want to convert and
cast out the reminders.
• Fractional part: Multiply the decimal number by the base to which we want to convert
and cast out the integer part.
• Rationale: Based on the positional notation.
• The conversion of decimal numbers with both integers and fraction parts is done by
converting the integer and fraction separately and then combining the two answers.
• Example 1: Convert (210)10 to binary and to hexadecimal (Radix 16).
• (210)10 = 1 x 27 + 1 x 26 + 0 x 25 + 1 x 24 + 0 x 23 + 0 x 22+ 1 x 21 + 0 x 20
= 128 + 64 + 0 + 16 + 0 + 0 + 1 + 0
= (11010010)2
• (210)10 = 13 x 161 + 2 x 160
= 208 + 2 = 210 = (D2)16
• Example 2: Conversion from Decimal 41 to Binary:
Integer quotient Remainder Coefficient
41/2 = 20 + 1 a0 = 1
20/2 = 10 + 0 a1 = 0
10/2 = 5 + 0 a2 = 0
5/2 = 2 + 1 a3 = 1
2/2 = 1 + 0 a4 = 0
1/2 = 0 + 1 a5 = 1
• So (41)10 =(101001)2
• The conversion from decimal integers to any base-r system is similar to the example, except that
division is done by r instead of 2.
• Conversion from Decimal 153 to Octal:
Integer quotient Remainder Coefficient
153/8 = 19 + 1 a0 = 1
19/8 = 2 + 3 a1 = 3
2/8 = 0 + 2 a2 = 2
• So (153)8=(231)8
• Conversion from Decimal fraction (0.6875) 10 to Binary:

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Integer Fraction Coefficient

0.6875 x 2 = 1 + 0.3750 a-1 = 1
0.3750 x 2 = 0 + 0.7500 a-2 = 0
0.7500 x 2 = 1 + 0.5000 a-3 = 1
0.5000 x 2 = 1 + 0.0000 a-4 = 1
• So (0.6875)10=(1011)2
• The conversion from decimal fraction to any base-r system is similar to the example.
Multiplication is by r instead of 2, and the coefficients found from the integers may range
in value from 0 to r-1 instead of 0 and 1.
• Conversion from Decimal fraction (0.513) 10 to Octal:
0.513 x 8 = 4.104
0.104 x 8 = 0.832
0.832 x 8 = 6.656
0.656 x 8 = 5.248
0.248 x 8 = 1.984
0.984 x 8 = 7.872
(0.513) 10 = (0.406517…) 8
Binary to/from Octal and Hexadecimal:
• Starting at the binary point, cast off three (four) bits at a time and convert each group to
its octal (hexadecimal) equivalent. Padding 0’s to the left for the integer part and to the
right for the fractional part only when required so that groups of 3 or 4 can be formed.
• The conversion from and to binary, octal and hexadecimal plays an important part in
digital computers. Since 23 = 8 and 24 = 16, each octal digit corresponds to three binary
digits and each hexadecimal digit corresponds to four binary digits.
• Conversion from binary to Octal:
(10 110 001 101 011. 111 100 000 110) 2 = (26153.7406) 8

• Conversion from binary to Hexadecimal:

(10 1100 0110 1011. 1111 0000 0110) 2 = (2C6B.F06) 16

• Conversion from Octal to binary:

(673.124) 8 = (110 111 011. 001 010 100) 2

• Conversion from Hexadecimal to binary:

(306.D) 16 = (0011 0000 0110. 1101) 2

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• Conversion from Hexadecimal to Octal:

It is a two-step process. First convert given Hexadecimal to binary and then binary to
octal.
(37B) 16= (0011 0111 1011)2
Now converting Binary to octal by dividing in to groups of 3 and substituting by
equivalent octal number
(0011 0111 1011)2 = (001 101 111 011)2 =(1573)8

• Conversion from Octal to Hexadecimal:

It is a two-step process. First convert given Octal to binary and then binary to
Hexadecimal.
(371) 8= (011 111 001)2
Now converting Binary to octal by dividing in to groups of 3 and substituting by
equivalent octal number.
(011 111 001)2 = (0000 1111 1001)2 =(0F9)16

1.5 Octal and Hexadecimal numbers:

Octal numbers
• A number system with its base as ‘eight’ is known as an Octal number system and uses
numbers from 0 to 7 i.e., 0, 1, 2, 3, 4, 5, 6, and 7. Three binary bits together can be
represented as a single octal number. Octal numbers will be simpler to use than lengthy
binary codes.
Table 1.2 Binary Representation of Octal Numbers

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HexaDecimal numbers
• A number system with its base as ‘sixteen’ is known as an Hexadecimal number system
and uses numbers from 0 to 9,(A-F) i.e., 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
(A=10,B=11,C=12,D=13,E=14,F=15). Four binary bits together can be represented as a
single Hexadecimal number. Hexadecimal numbers will be simpler to use than lengthy
binary codes.

Table 1.3 Binary Representation of Hexa Decimal Numbers

1.6 Complements:
1.6.1 r-1’s complement and r’s complement of unsigned numbers :
9’s & 10’s Complements for decimal numbers

• The Subtraction of decimal numbers can be accomplished by the 9‘s & 10‘s compliment
methods similar to the 1‘s & 2‘s compliment methods of binary numbers.

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• The 9‘s compliment (diminished radixcomplement) of a decimal number is obtained by

subtracting each digit of that decimal number from 9.
• The 10‘s compliment(radixcomplement) of a decimal number is obtained by adding a 1 to
its 9‘s compliment.
Example:
9‘s compliment of 3465and 782.54 is

10‘s complement of 4069 is

9 9 9 9
- 4 0 6 9
5 9 3 0
+ 1
5 9 3 1
1‘s & 2’s compliment form for binary numbers:

• The 1‘s complement of a binary number is defined as the value obtained by inverting all
the bits in the binary representation of the number (swapping 0s for 1s and vice versa).
Example:
For X = 1010, the 1's complement is given by 0101.
• The 2's complement of a binary number X is obtained by following three methods
1. The expression 2n – X, where n is the number of bits of X.
2. All the bits are inverted (1’s complement) and a 1 is added in the least significant
place.
3. The lowest order 1 in X is sensed, and all succeeding higher digits are inverted.
Example:
For X = 1010, the 2's complement is given by:
1. 24 – 1010 = 10000 – 1010 = 0110.
2. 1’s complement of 1010 is 0101 and 0101 + 1 = 0110.

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3. The low order 1 in 1010 is at 1st bit position and after that the higher digits are
inverted and the result is 0110.
1.6.2 r-1’s and r’s complement of unsigned numbers subtraction:
9’s compliment method of subtraction:
• To perform this, obtain the 9‘s compliment of the subtrahend and to it, add the minuend,
now call this number as intermediate result. If there is a carry to the LSD of this result to
get the answer called end around carry. If there is no carry, it indicates that the answer
is negative & the intermediate result is its 9‘s compliment.
Example: Subtract using 9‘s complement

(1) 745.81- 436.62 (2) 436.62 - 745.82

745.81 (normal subtraction) 436.62

-436.62 -745.81
---------- ----------
309.19 -309.19
----------- ---------
745.81 436.62
+563.37 9‘s compliment of 436.62 +254.18
---------- ------------
1309.18 (end around carry) 690.80 (no carry)
+1 ------------
----------- 9‘s complement of 690.80
+309.19 = - 309.19

• If there is no carry indicating that answer is negative. so take 9‘s complement of

intermediate result & put minus sign (-) then the result should be -309.19.
• If there is a carry indicates that the answer is positive +309.19. Then there is no need of
taking 9‘s complement.

10’s compliment method of subtraction:

• To perform this, obtain the 10‘s compliment of the subtrahend & add it to the minuend. If
there is a carry ignore it.
• The presence of the carry indicates that the answer is positive, the result is the answer.
• If there is no carry, it indicates that the answer is negative & the result is its 10‘s
compliment.
• Obtain the 10‘s compliment of the result & place negative sign infront to get the answer.
Example:

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(a) 2928.54 - 416.73 (b) 416.73 - 2928.54

2928.54 (normal subtraction) 0416.73 (normal

-0416.73 -2928.54 Subtraction)
---------- -------------
2511.81 -2511.81
----------- --------------

2928.54 0416.73
+9583.27 10‘s compliment of 416.73 +7071.46 10’s compliment
---------- ------------- of 2928.53
12511.81 ignore the carry 7488.19 No carry
------------ ------------ 10’s compliment
+2511.81 -2511.81 of 7488.19

1.7 Signed binary numbers

1.7 .1 Signed binary numbers Representation:
• Two ways of representation of signed numbers
1. Sign Magnitude form
2. Complemented form
1. Sign Magnitude form:
• In sign magnitude form, an additional bit called the sign bit is placed in front of the
number.
• If the sign bit is 0, the number is positive, and if it is a 1, then the number is negative.
Example:

0 1 0 1 0 0 1
↓
Sign bit =+41 magnitude
↑
1 1 0 1 0 0 1

= - 41 magnitude
2. Complemented form:
• If the number is positive, the magnitude is represented in its true binary form & a sign bit
0 is placed in front of the MSB.
• If the no is negative, the magnitude is represented in its 2‘s or 1‘s compliment form &a
sign bit 1 is placed in front of the MSB.
Example:

1 0 0 1 1 0 1 =-51 In sign 2’s complement form

1 0 0 1 1 0 0 =-51 In sign 1’s complement form

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Table 1.4 Finding Binary numbers equivalent in Sign- Magnitude form, 1’s and 2’s
complement form

Given no. Sign magnitude form 2‘s complement form 1‘s complement form
01101 +13 +13 +13
010111 +23 +23 +23
10111 -7 -9 -8
1101010 -42 -22 -21

Special case in 2’s complement representation:

• Whenever a signed no. has a 1 in the sign bit & all 0‘s for the magnitude bits, the
decimal equivalent is -2n, where n is the no of bits in the magnitude.
Example:
1000= -8 & 10000=-16
1.7.2 Signed binary numbers Addition:
• The numbers to be added are represented in signed magnitude format and binary
addition will be performed.
Example: Add 75 to +26 using 8-bit 2‘s complement arithmetic

+75 = 01001011

+26 =00011010
___ ____________
101 01100101 No carry
No carry and MSB is 0. So the result is positive and is in true form. The magnitude is = 101

1.7.3 Signed binary numbers Subtraction:

2’s compliment Arithmetic:
• The 2‘s complement system is used to represent positive numbers using modulus
arithmetic.
• The word length of a computer is fixed. i.e., if a 4-bit number is added to another 4-bit
number, the result will be only of 4 bits.
• Carry if any, from the fourth bit will overflow called the Modulus arithmetic.
Example:1100+1111=1011
• In the 2‘s complement subtraction, add the 2‘s complement of the subtrahend to the
minuend.

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• If there is a carry out, ignore it and look at the sign bit i.e., MSB of the sum term.
• If the MSB is a 0, the result is positive and it is in true binary form.
• If the MSB is a 1 (carry in or no carry at all) the result is negative and is in its 2‘s
complement form. Take its 2‘s complement to find its magnitude in binary.
Example 1:
Subtract 14 from 46 using 8-bit 2‘s complement arithmetic:

+14 = 00001110
-14 =11110010 2‘s complement of 14

+46 = 00101110
-14 =+11110010 2‘s complement form of 14
___ ____________
-32 (1)00100000 ignore carry
Ignore carry and the MSB is 0. So, the result is positive and is in normal binary form.
So the result is +00100000=+32.
Example 2:
Add -75 to +26 using 8-bit 2‘s complement arithmetic

+75 = 01001011
-75 =10110101 2‘s complement of 75

+26 =00011010
-75 =+10110101
___ ____________
-49 11001111 No carry
No carry and MSB is 1. So the result is negative and is in 2‘s complement form. The
magnitude is 2‘s complement of 11001111.i.e., 00110001 = 49. So result is -49.
1’s compliment arithmetic:
• In 1‘s complement subtraction, add the 1‘s complement of the subtrahend to the minuend.
• If there is a carryout, bring the carry around & add it to the LSB called the end around
carry.
• Look at the sign bit (MSB). If this is a 0, the result is positive and a true binary number.
• If the MSB is a 1 (carry or no carry), the result is negative and in complement form. Take
its 1‘s complement to get the magnitude in binary.
Example: Using 8-bit 1‘s complement

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Subtract 14 from 25 ADD -25 to +14

25 =00011001 +14 =00001110
-14 =11110001 -25 =+11100110
__ __________ ___ ___________
+11 (1)00001010 -11 11110100
+1
____________ No carry and MSB =1
00001011 Result is negative and in 1’s complement form
MSB is a 0 so result is positive (true binary)

Compliment Arithmetic Advantage:

• Subtractionis also performed by addition. Instead of subtracting one number from other
the compliment of the subtrahend is added to minuend.

1.8 Binary Codes

• The digital data is represented, stored and transmitted as group of binary bits. This group
is also called as binary code. The binary code is represented by the number as well as
alphanumeric letter.
Advantages of Binary Code
Following is the list of advantages that binary code offers.
• Binary codes are suitable for the computer applications.
• Binary codes are suitable for the digital communications.
• Binary codes make analysis and design of digital circuits .
• Since only 0 & 1 are being used, implementation becomes easy.

Fig 1.2 Classification of Binary Codes

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• The codes are broadly categorized into following four categories.

• Weighted Codes
• Non-Weighted Codes
• Binary Coded Decimal Code
• Alphanumeric Codes
• Error Detecting Codes
• Error Correcting Codes
Weighted Codes
• Weighted binary codes are those binary codes which obey the positional weight principle.
Each position of the number represents a specific weight. Several systems of the codes
are used to express the decimal digits 0 through 9. In these codes each decimal digit is
represented by a group of four bits.

Non-Weighted Codes
• In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes
are Excess-3 code and Gray code.

Excess-3 code
• The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express
decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words
adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as
follows –

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Table 1.5 Representing Decimal numbers in BCD and Excess-3 format

Gray Code
• It is the non-weighted code and it is not arithmetic codes. That means there are no
specific weights assigned to the bit position.
• It has a very special feature that, only one bit will change each time the decimal number is
incremented as shown in fig. As only one bit changes at a time, the gray code is called as
a unit distance code. The gray code is a cyclic code. Gray code cannot be used for
arithmetic operation.
Table 1.6 Representing Decimal numbers in BCD and Gray format

Application of Gray code

• Gray code is popularly used in the shaft position encoders.
• A shaft position encoder produces a code word which represents the angular position of

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the shaft.
Binary Coded Decimal (BCD) code
• In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to
express each of the decimal digits with a binary code. In the BCD, with four bits we can
represent sixteen numbers (0000 to 1111).
• But in BCD code only first ten of these are used (0000 to 1001). The remaining six code
combinations i.e. 1010 to 1111 are invalid in BCD.
Table 1.7 Representing Decimal numbers in BCD format

Advantages of BCD Codes

• It is very similar to decimal system.
• We need to remember binary equivalent of decimal numbers 0 to 9 only.
Disadvantages of BCD Codes
• The addition and subtraction of BCD have different rules.
• The BCD arithmetic is little more complicated.
• BCD needs more number of bits than binary to represent the decimal number. So BCD is
less efficient than binary.
Alphanumeric codes
• A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But
this is not enough for communication between two computers because there we need
many more symbols for communication.
• These symbols are required to represent 26 alphabets with capital and small letters,
numbers from 0 to 9, punctuation marks and other symbols.
• The alphanumeric codes are the codes that represent numbers and alphabetic characters.
• Mostly such codes also represent other characters such as symbol and various instructions
necessary for conveying information.
• An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e.
total 36 items.
• The following three alphanumeric codes are very commonly used for the data
representation.

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• American Standard Code for Information Interchange (ASCII).

• Extended Binary Coded Decimal Interchange Code (EBCDIC).
• Five bit BCD Code.
ASCII code:
• ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. ASCII code is more
commonly used worldwide while EBCDIC is used primarily in large IBM computers.
Sequential Code:
• These are those codes in which each succeeding code is 1 binary number greater than the
preceding code.
• This property is used for mathematical manipulation of data. For ex:- BCD And Excess-3
Code.
Self-complementary Code:
• A code is said to be self-complementary if the code for 9’s complement of N i.e. 9-N can
be obtained by interchanging all 0s and 1s.
• Decimal 9 is the complement of code for 0, 8 for 1, 7 for 2 and so on.
• For a code to be self-complementing, the sum of all its weights must be 9. Digit.8421 and
5421 codes are not self-complementing codes whereas 5211,2421,3321, 4321 are self-
complementing.
• In general, a code is self-complementary if we produce a code by taking the first
complement of the digit which is same as 9’s complement of the number.
Cyclic codes:
• Cyclic codes are those in which each successive code word differs from the preceding one
in only one bit position.
• They are also called unit distance codes
• Example: gray code Reflective Code: Example : Gray code
1.8.1 Binary Coded Decimal (BCD) code
• In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to
express each of the decimal digits with a binary code. In the BCD, with four bits we can
represent sixteen numbers (0000 to 1111).
• But in BCD code only first ten of these are used (0000 to 1001). The remaining six code
combinations i.e. 1010 to 1111 are invalid in BCD.
Advantages of BCD Codes
• It is very similar to decimal system.

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• We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes

• The addition and subtraction of BCD have different rules.
• The BCD arithmetic is little more complicated.

• BCD needs more number of bits than binary to represent the decimal number. So
BCD is less efficient than binary.

Table 1.8 Representing Decimal numbers in BCD format

1.8.2 BCD Addition

• It isindividually adding the corresponding digits of the decimal numbers expressed in
4 bit binary groups starting from the LSD.
• If there is no carry & the sum term is not an illegal code , no correction isneeded
• .If there is a carry out of one group to the next group or ifthe sum term isan illegal
codethen610(0100)isadded to thesum term of that group&theresulting carry is added
to the next group.
Example :PerformBCD addition for 25+13
InBCD 25 =0010 0101
InBCD +13= +0001 0011
Result +38 = 0011 1000
• No carry generated, No invalid code generated. So valid answer

1.8.3 Other Decimal Codes:

Excess-3 code
• The Excess-3 code is also called as XS-3 code. It is non-weighted code used to
express decimal numbers.
• The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2
or (3)10 to each code word in 8421. The excess-3 codes are obtained as follows −

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Table 1.9 Representing Decimal numbers in BCD and Excess-3 format

1.8.4 Gray Code:

• It is the non-weighted code and it is not arithmetic codes. That means there are no
specific weights assigned to the bit position.
• It has a very special feature that, only one bit will change each time the decimal number is
incremented as shown in fig. As only one bit changes at a time, the gray code is called as
a unit distance code.
• The gray code is a cyclic code. Gray code cannot be used for arithmetic operation.
Table 1.10 Representing Decimal numbers in BCD and Gray format

Application of Gray code

• Gray code is popularly used in the shaft position encoders.
• A shaft position encoder produces a code word which represents the angular position of
the shaft.
Binary–Gray Code Conversion:
• A given binary number can be converted into its Gray code equivalent by going through

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the following steps:

• Begin with the most significant bit (MSB) of the binary number. The MSB of the
Gray code equivalent is the same as the MSB of the given binary number.
• The second most significant bit, adjacent to the MSB, in the Gray code number is
obtained by adding the MSB and the second MSB of the binary number and ignoring
the carry, if any. That is, if the MSB and the bit adjacent to it are both ‘1’, then the
corresponding Gray code bit would be a ‘0’.
• The third most significant bit, adjacent to the second MSB, in the Gray code number
is obtained by adding the second MSB and the third MSB in the binary number and
ignoring the carry, if any.
• The process continues until we obtain the LSB of the Gray code number by the
addition of the LSB and the next higher adjacent bit of the binary number.
• The conversion process is further illustrated with the help of an example showing step-
by-step conversion of binary code 1011 into its Gray code equivalent:
• Gray code 1- - - Binary 1011
• Gray code 11- - Binary 1011
• Gray code 111- Binary 1011
• Gray code 1110
Gray–Binary Code Conversion:
• A given Gray code can be converted into its binary equivalent by going through the
following steps:
• Begin with the most significant bit (MSB) of the Gray number. The MSB of the
binary number is equivalent to the MSB of the given Gray number.
• The second most significant bit, adjacent to the MSB, in the binary code number is
obtained by performing XOR operation between the MSB of Binary number and the
second MSB of the Gray number.
• The third most significant bit, adjacent to the second MSB, in the binary code number
is obtained by performing XOR operation between the second MSB of Binary number
and the third MSB of the Gray number.
• The process continues until we obtain the LSB of the binary number .
• The conversion process is further illustrated with the help of an example showing step-
by-step conversion of gray code 1110 into its binary code equivalent:
• Binary code 1- - - Gray 1011

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• Binary code 10-- - Gray 1011

• Gray code 1011- Gray 1011
• Gray code 1011

1.9 Basic Logic Functions:

• A Boolean function contains Binary variables, Binary operators OR and AND, Unary
operator NOT and Parentheses
1.9.1Postulates and theorems
• Switching circuits called Logic circuits, gate circuits & digital circuits. Switching algebra
called Boolean Algebra. Boolean algebra is a system of mathematical logic. It is an
algebraic system consisting of the set of element (0,1) two binary operators called OR &
AND & One unary operator NOT.
• A+A=A ,A.A=A because variable has only a logicvalue.

Complementation Laws:
• Complement means invert(0’ as 1 & 1’ as 0)
• Law1:0’=1
• Law2:1’=0
• Law3:If A=0 then A’ =1
• Law4:If A=1 then A’ =0
• Law5: (A’)’ =A(double complementation law)

AND laws:
• Law 1: A.0=0(Null law)
• Law 2:A.1=A(Identity law)
• Law 3:A.A=A
• Law 4:A.A’ =0

OR laws:
• Law 1: A+0=A(Null law)
• Law 2:A+1=1
• Law 3:A+A=A
• Law 4:A+ =0

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Commutative laws:
• Allows change in position of AND or OR variables.2 commutative laws
• Law 1: A+B=B+A
• Law 2: A.B=B.A

Table 1.11 Truth table Representation of commutative law1 and 2

A B A+B = B A B+A A.B B.A
0 0 0 0 0 0 0 0
0 1 1 0 1 1 0 0
1 0 1 1 0 1 0 0
1 1 1 1 1 1 1 1

Fig 1.3 Logical representation of Commutative Law 1 and 2

Associative laws:
• This allows grouping of variables. It has 2 laws.
• Law 1: (A+B)+C=A+(B+C) =A OR B ORed with C
• This law can be extended to any no. of variables
(A+B+C)+D=(A+B+C)+D=(A+B)+(C+D)

Fig 1.4 Logical representation of Associative Law 1

• Law 2: (A.B).C=A.(B.C)

Fig 1.5 Logical representation of Associative Law 2

• This law can be extended to any no. of variables (A.B.C).D=(A.B.C).D

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Table 1.12 Truth table Representation of Associative law1

AB C A+B (A+B)+C AB C B+C A+(B+C)

0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 1 1
0 1 0 1 1 0 1 0 1 1
0 1 1 1 1 0 1 1 1 1
1 0 0 1 1 = 1 0 0 0 1
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1

Table 1.13 Truth table Representation of Associative law2

AB C AB (AB)C AB C BC A(BC)
0 0 0 0 0 0 0 0 0 0
0 01 0 0 = 0 01 0 0
0 1 0 0 0 0 1 0 0 0
0 1 1 0 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 1 0 1 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

Distributive Laws:
• This has 2 laws
• Law 1.A(B+C)=AB+AC
• This law applies to single variables.
• Ex: ABC(D+E)=ABCD+ABCE
• AB(CD+EF)=ABCD+ABEF

Fig 1.6 Logical representation of Distributive Law 1

• Law 2.A+BC=(A+B)(A+C) RHF=(A+B)(A+C)

=AA+AC+BA+BC
=A+AC+AB+BC
=A(1+C+B)+BC
=A.1+BC

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=A+BC LHF

Table 1.14 Truth table Representation of Distributive law1

AB C B+C A(B+C) AB C AB AC AB+AC

0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 = 0 1 1 0 0 0
1 0 0 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1
1 1 0 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1

Table 1.15 Truth table Representation of Distributive law2

AB C BC A+BC A B C (A+B) (A+C) (A+B)(A+C)

0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 1 0
0 1 0 0 0 = 0 1 0 1 0 0
0 1 1 1 1 0 1 1 1 1 1
1 0 0 0 1 1 0 0 1 1 1
1 0 1 0 1 1 0 1 1 1 1
1 1 0 0 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1

Fig 1.7 Logical representation of Distributive Law 2

Redundant Literal Rule(RLR):

• Law 1: A+ A’B=A+B

LHF = (A+A’)(A+B)
=1.(A+B)
=A+B RHF
• Performing OR operation of a variable with the AND of the compliment of that variable
with another variable, is equal to the Performing OR operation of the two variables.

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Fig 1.8 Logical representation of Redundant Literal Law 1

Table 1.16 Truth table Representation of Redundant Literal Law 1

AB B A+ B A B A+B
0 0 0 0 0 0 0
0 1 1 1 = 0 1 1
1 0 0 1 1 1 1
1 1 0 1 1 1 1

• Law 2: A (A’+B) = AB
LHF = A.A’ + AB
= 0+AB
=AB RHF
• Performing AND operation of a variable with the OR of the complement of that variable
with another variable, is equal to the performing AND operation of the two variables.

Fig 1.9 Logical representation of Redundant Literal Law 2

Table 1.16 Truth table representation of Redundant Literal Law 2

A B A’ A’+B A(A’+B) A B AB
0 0 1 1 0 0 0 0
0 1 1 1 0 = 0 1 0
1 0 0 0 0 1 0 0
1 1 0 1 1 1 1 1

Idempotent Law:
• Idempotent means same value. It has 2 laws.
• Law 1=A.A=A
• This law states performing AND operation of a variable with itself is equal to itself .
If A=0, then A.A=0.0=0=A
If A=1, then A.A=1.1=1=A

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Fig 1.10 Logical representation of Idempotent Law 1

• Law 2=A+A=A
• This law states performing OR operation of a variable with itself is equal to that
variable
If A=0, then A+A=0+0=0=A
If A=1, then A+A=1+1=1=A

Fig 1.11 Logical representation of Idempotent Law 2

Absorption Laws:
• Law 1=A+A.B=A
• A+AB =A(1+B)=A.1=A

Fig 1.12 Logical representation of Absorption Law 1

Table 1.17 Truth table representation of Absorption Law 1

• Law 2=A(A+B)=A
• A(A+B)=A.A+A.B
=A+AB
=A(1+B)
=A.1=A

Fig 1.13 Logical representation of Absorption Law 2

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Table 1.18 Truth table representation of Absorption Law 2

Transposition Theorem:

• AB+ A‘C= (A+C)(A‘+B)

• RHS = (A+C)(A‘ +B)

=AA‘ +CA‘ +AB+CB

=0+ A‘C+AB+CB
= A‘C+AB+CB(A+A‘)
= A’C(1+B)+AB(1+C)
=A’C+AB=LHS

DeMorgan’s Theorem:
• It represents two of the most powerful laws in Boolean algebra
• Law 1: (A+B)‘ = A‘.B‘
• This law states that the compliment of a sum of variables is equal to the product of their
individual complements.

LHS

RHS

Fig 1.14 Logical representation of DeMorgan’s Law 1

• NOR gate= Bubbled AND gate

• This can be extended to any variables. (A+B+C+D+-----) ‘=A‘B‘C‘D‘----
• Law 2: (AB)‘=A‘+B‘
• Complement of the product of variables is equal to the sum of their individual
components.

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Duality:
• In a positive Logic system the more positive of the two voltage levels is represented by a
1 & the more negative by a 0.
• In a negative logic system the more positive of the two voltage levels is represented by a
0 & more negative by a 1.
• This distinction between positive &negative logic systems is important because an OR
gate in the positive logic system becomes an AND gate in the negative logic system
&vice versa.
• Positive & Negative logics give a basic duality in Boolean identities. Procedure dual
identity by changing all + (OR) to. (AND) & complementing all 0‘s &1‘s.
• Once a theorem or statement is proved, the dual also thus stands proved called Principle
of duality.
• Relations between complement
(A+B+C+….) ‘= A’. B’.C’ ….
(A.B.C.….) ‘= A’ + B’ + C’ + ….

Duals:
Table 1.19 Table representing different expressions and their Duals

Expression Dual
0=1 1=0
0.1=0 1+0=1
0.0=0 1+1=1
1.1=1 0+0=0
A.0=0 A+1=1
A.1=A A+0=A
A.A=A A+A=A
A.A’ =0 A+A’ =1
A.B=B.A A+B=B+A
A.(B.C)=(A.B).C A+(B+C)=(A+B)+C
A.(B+C)=(AB+AC) A+BC=(A+B)(A+C)
A(A+B)=A A+AB=A
A.(A.B)=A.B A+A+B=A+B
(A+B)(A’+C)(B+C)=(A+B)( AB+ A'C+BC=AB+
A’+C) A'C

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1.10 Logic Gates:

1.10.1 Logic Gates
• Logic gates are fundamental building blocks of digital systems. Logic gate produces one
output level when some combinations of input levels are present and a different output
level when other combination of input levels is present. Based on the axioms there 3 basic
types of logic gates were available which are indicated by AND, OR, NOT.
• The interconnection of gates to perform a variety of logical operation is called Logic
Design. Inputs & outputs of logic gates can occur only in two levels i.e., 1,0 or High, Low
or True ,False or On , Off.
• A table which lists all the possible combinations of input variables & the corresponding
outputs is called a Truth Table. It shows how the logic circuits output responds to various
combinations of logic levels at the inputs.
• Level Logic, a logic in which the voltage levels represent logic 1 & logic 0.Level logic
may be Positive Logic or Negative Logic.
• In Positive Logic the higher of two voltage levels represent logic 1 & Lower of two
voltage levels represent logic 0.In Negative Logic the lower of two voltage levels
represent logic 1 & higher of two voltage levels represent logic 0.
• Ex:In TTL (Transistor-Transistor Logic) Logic family voltage levels are +5V and
0V.Logic 1 represent +5Vand Logic 0 represent 0V.

AND Gate:
• It is represented by “.”(dot) It has two or more inputs but only one output.
• The output assume the logic 1 state only when each one of its inputs is at logic 1 state.
• The output assumes the logic 0 state even if one of its inputs is at logic 0 state.
• The AND gate is also called an All or Nothing gate.
• Boolean Expression: A AND B, Y=A.B
Table 1.20 Truth table of AND gate

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Fig 1.15 Logic Symbol of AND gate

OR Gate:
• It is represented by “+”(plus). It has two or more inputs but only one output.
• The output assumes the logic 1 state only when one of its inputs is at logic 1 state.
• The output assumes the logic 0 state even if each one of its inputs is at logic 0 state.
• The OR gate is also called an any or All gate.
• Also called an inclusive OR gate because it includes the condition both the inputs can be
present.
Table 1.21 Truth table of OR gate

Fig 1.16 Logic Symbol of OR gate

NOT Gate:

• It is represented by “-“(bar).It is also called an Inverter or Buffer.

• It has only one input and one output. Whose output always the compliment of its input.
• The output assumes logic 1 when input is logic 0 & output assume logic 0 when input is
logic 1.

Fig 1.17 Logic Symbol of NOT gate

Table 1.22 Truth table of NOT gate

A X
1 0
0 1

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• Logic circuits of any complexity can be realized using only AND, OR, NOT gates. Using
these 3 called AND-OR-INVERT i.e., AOI Logic circuits.

NAND Gate:
• It is combination of AND gate followed by NOT gate
• ̅̅̅̅̅̅̅̅
Boolean Expression: 𝑌 = (𝐴. 𝐵)
• NAND assumes Logic 0 when each of inputs assumes logic 1.

Fig 1.18 Logic Symbol of NAND gate

Table 1.23 Truth table of NAND gate

• Bubbled OR gate: The output of this is same as NAND gate.

• Bubbled OR gate is OR gate with inverted inputs.
• 𝑌 = 𝐴̅ + 𝐵̅ = (𝐴𝐵)
NOR Gate:
• NOR gate is NOT gate with OR gate. i.e., OR gate is inverted.
• Boolean expression:𝑌 = ̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵)
• Logic symbol with OR and NOT

Fig 1.19 Logic Symbol of NOR gate

Table 1.24 Truth table of NOR gate

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

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The Exclusive OR (X-OR) gate:

• It has 2 inputs& only 1 output.
• It assumes output as 1 when input is not equal called anti-coincidence gate or inequality
detector.

Fig 1.20 Logic Symbol of X-OR gate

Table 1.25 Truth table of X-OR gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

• The high outputs are generated only when odd number of high inputs is present. This is
why x-or function also known as odd function.
The EX-NOR Gate:

• It is X-OR gate with a NOT gate. It has two inputs & one output logic circuit.
• It assumes output as 0 when one if inputs are 0 and other 1.
• It can be used as an equality detector because it outputs a 1 only when its inputs are equal.
• Proof: A ʘ B = (AB)’
= (AB’+A’B)’
= (A’+B).(A+B’)
= AA’+A’B’+AB+BB’
= AB+A’B’

Table 1.26 Truth table of X-NOR gate

Fig 1.21 Logic Symbol of X-NOR gate

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1.10.2 Gates implementation of expressions:

• Any function can be simply realized using basic gates (AND, OR, NOT).This
implementation is also known as AOI Logic.
• Example: Consider the functionF1 =x+ y’z
Here an OR gate is required with two inputs (x and y’z). An inverter is required for y’ and an
AND gate is required for y’z. The implementation is as follows.

Fig 1.22 AOI Representation of the function F1 = x+ y’z

1.11. Universal Logic Gates:

1.11. 1 NAND and NOR Gates:
• The universal gates are NAND, NOR.
• These gates are called universal gates because any Boolean logic function including basic
operations (AND, OR, INVERT) can be implemented using NAND and NOR gates.
• More over AOI logic can be easily converted to NAND logic or NOR logic.

1.11.2 Gate Realization using NAND and NOR:

Gate Realization using NAND:
NAND gate as an Inverter:

• All its input terminals together & applying the signal to be inverted to the common
terminal by connecting all input terminals except one to logic 1 & applying the signal to
be inverted to the remaining terminal.
• It is also called Controlled Inverter.

Fig 1.23 NAND gate as an Inverter

NAND gate as an OR gate:

• Bubbled NAND Gate: The output of bubbled NAND gate is same as OR gate

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Fig 1.24 NAND gate as an OR gate

NAND gate as an AND gate:

• To obtain an AND gate from NAND gates, we first feed the inputs A and B into the
NAND gates.
• When, the output says Y is fed into another NAND gate with the two inputs joined
together to obtain an output, say Z which is NOT (NAND Y).

Fig 1.25 NAND gate as an AND gate

NAND gate as an XOR gate:

• To convert the expression into NAND form perform the following:
• Apply double complement: [(A’.B + A.B’)’]’
• Operate internal complement: [ (A’.B)’ . (A.B’)’ ]’
• Now, expression is obtained in NAND form.

Fig 1.26 NAND gate as an XOR gate

NAND gate as an X-NOR gate:

• The first four gates is the same logic for XOR gate as discussed above. Then an inverter
is used to get XNOR gate.

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Fig 1.27 NAND gate as an X-NOR gate

Gate Realization using NOR:

NOR gate as an inverter:
• It is tying all input terminals together & applying the signal to be inverted to the common
terminals or all inputs set as logic 0 except one & applying signal to be inverted to the
remaining terminal.

Fig 1.28 NOR gate as an Inverter

NOR gate as an OR gate:
• To obtain an OR gate from NOR gates, we first feed the inputs A and B into the
NOrgates. Then output is fed into another NOR gate with the two inputs joined together
to obtain an output, say Y.

Fig 1.29 NOR gate as an OR gate

NOR gate as an AND gate:

• Bubbled NOR Gate: The output of bubbled NOR gate is same as AND gate

Fig 1.30 NOR gate as an AND gate

NOR gate as an XOR gate:

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• First, we will connect both the inputs in NOR gate resulting in (A + B)’.
• Then, after we have another two NOR gates with the inputs A, (A + B)’ and B, (A + B)’
respectively with outputs [A + (A + B)’]’ and [B + (A + B)’]’.
• Again, connect outputs of the above NOR gates to next NOR gate resulting in the output
[A’B + AB’]’.
• Now, the result is generated in complement form so, we connect the result as the input
for last NOR gate which gives the output AB’ + A’B.
• The resultant of the last NOR gate gives us XOR gate.

Fig 1.31 NOR gate as an XOR gate

NOR gate as an X-NOR gate:

• First, we connect both the inputs in NOR gate resulting in (A + B)’.
• Then, after we have another two NOR gates with the inputs A, (A + B)’ and B, (A + B)’
respectively with outputs [A + (A + B)’]’ and [B + (A + B)’]’.
• Again, the connect outputs of the above NOR gates to next NOR gate resulting in the
output [A’B + AB’]’.

Fig 1.32 NOR gate as an X-NOR gate

1.12. Minimization of Logic Expressions:

• When a Boolean expression is implemented with logic gates, each term requires a gate
and each variable within the term designates an input to the gate.
• By reducing the number of terms, it is possible to obtain a simpler circuit.
• Functions up to 5-variables can be simplified by the K- map method easily.

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• For complex Boolean functions, digital designers use computer minimization programs.
• The only manual method available for complex functions is employing the basic relations
and other manipulations techniques .
1.12.1.Example 2.1:
• Simplify the following Boolean functions to a minimum number of literals
1) X(X'+Y)=X.X'+X.Y=0+XY=XY
2) X+X’Y=(X+X’)(X+Y)=(1)(X+Y)=X+Y
3) (X+Y)(X+Y’)=(X.X)+(X.Y’)+(Y.X)+(Y.Y’)
=(X)+(XY’)+(XY)
=X(1+Y’+Y)=X(1)=X
4) XY+X’Z+YZ=XY+X’Z+YZ(X+X’)
=XY+X’Z+XYZ+X’YZ
= XY(1+Z)+X’Z(1+Y)
=XY+X’Z
5) (X+Y)(X’+Z)(Y+Z)=(X+Y)(X’+Z)(Y+Z+X.X’)
=(X+Y)(X’+Z)(X+Y+Z)(X’+Y+Z)
Let (X+Y) =P,(X’+Z)=Q
= (P)(Q)(P+Z)(Q+Z)=(P)(P+Z)(Q)(Q+Z)
=(P.P+P.Z)(Q.Q+Q.Z)
= (P+PZ)(Q+QZ)=(P(1+Z))(Q(1+Z))=P.Q
Now substituting p and q values we get
=(X+Y)(X’+Z)

1.13. K(Karnaugh) -map Simplifications:

• The K-map is a diagram made up of squares.

• Each square represents one minterm. Since any function can be expressed as a sum of
minterms, it follows that a Boolean function can be recognized from a map by the area
enclosed by those squares, whose minterms are included in the operation.
• By various patterns, we can derive alternative algebraic expression for the same
operation, from which we can select the simplest one. (One that has minimum number of
literals).
• Construct the K-map as discussed above. Enter 1 in those squares corresponding to the

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• minterms for which function value is 1. Leave empty the remaining squares. Now in
following steps the square means the square with a value 1.
• Examine the map for squares that cannot be combined with any other squares and form
group of such single squares.
• Now, look for squares which are adjacent to only one other square and form groups
containing only two squares and which are not part of any group of 4 or 8 squares. A
group of two squares is called a pair.
• Next, group the squares which result in groups of 4 squares but are not part of an 8-
squares group. A group of 4 squares is called a quad.
• Group the squares which result in groups of 8 squares. A group of 8 squares is called
octet.
• Form more pairs, quads and outlets to include those squares that have not yet been
grouped, and use only a minimum no. of groups. There can be overlapping of groups if
they include common squares.
• Omit any redundant group.
• Form the logical sum of all the terms generated by each group.
• Using Logic Adjacency Theorem we can conclude that,
• a group of two squares eliminates one variable,
• a group of four squares eliminates two variable and a group of eight squares
eliminates three variables.

• There are two, three and four variable K maps.

1.13.1 Two Variable K-Map:

• For two variables there are four minterms and these can be conveniently placed on a 'map'
as shown in figure below

Fig 1.33 2-Variable K-Map Representation

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• The map consists of a square divided into four cells, one for each of the minterms.
• The possible values of the variable A are written down the left hand side of the map,
labeling the corresponding rows of the map, while the possible values of the variable B
are written along the top of the map, labeling the corresponding columns of the map.
• Hence, the top left-hand cell represents the minterm where A=0 and B=0, i.e. the minterm
AB.
• The bottom right-hand cell represents the minterm AB where A=1and B=1.
• The process of simplifying a Boolean function with the aid of a K-map is simplya process
of finding adjacencies on the function plot.
• This is best explained with the aidof a very simple example.
• Suppose that it is required to simplify the Boolean function f = A'B‘+ AB' + AB.
• Using Boolean algebra alone, it can be readily found that F=B(A' + A) + AB = AB + B'
• However, suppose that F is plotted on a 2-variable K-map, as in Figure below.

Fig 1.34 Cell grouping in 2 Variable K-Map

• The next stage of the simplification process is to group together adjacent cells containing
1's. (In this context, note carefully that 'adjacent' means 'horizontally or vertically', not
'diagonally'.)
• Therefore, the bottom two cells, corresponding to A alone, may be grouped together.
• Similarly, the two left-hand cells, corresponding to B alone, may also be grouped
together, as indicated in the figure above.
• The final stage is to write down the final simplified expression for the function obtained
from the groupings thus identified. In this case, therefore, f = A + B’.
1.13.2 Three Variable K-Map:
• If the following Boolean function F (A, B, C) = Σ (3, 4, 6, 7).Then it is represented in k-
map as shown in figure below:
• Step 1.m3 is adjacent to m7. It forms a group of two squares and is not a part of any
group of 4 or 8 squares. Similarly m6 is adjacent to m7. So this is second group (pair) that
is not a part of any group of 4 or 8 squares. Now according to new definition of adjacency

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m4 and m6 are also adjacent and form a pair. Moreover, this pair (group) is not a part of
any group of 4 or 8 squares.
• Step 2.All the 1's have already been grouped.
• Step 3.The pair formed by m6 m7 is redundant because m6 is already covered in pairm4
m6 and m7 in pair m3 m7. Therefore, the pair m6 m7 is discarded.
• Step 4.The terms generated by the remaining two groups are ‘OR' operated togetherto
obtain the expression for F as follows:

Fig 1.35 Cell grouping in 3 Variable K-Map

1.13.3 Four Variable K-Map:

• If the following Boolean functionF(w, x y, z) = Σ (0, 2, 3, 6, 7, 8, 10, 11, 12, 15), then the
K-map is given in the figure below

Fig 1.36 Cell grouping in 4 Variable K-Map

• Minterm 8 and 12. From a pair. It can be expressed as wy’z’

• Minterms 0, 2, 8 and 10 form I quad. It can be expressed as x’z’
• Minterms 3, 7, 11, 15 form II quad. It can be expressed as yz

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• Minterms 2, 3, 6, 7 form III quad. It can be expressed as w’y

• Therefore the final minimized expression is given by F=wy’z’+x’z’+yz+w’y
1.13.4 Don't care conditions:
• The occurrence of particularinput combinations will have no effect onthe output, then
those inputs are known as don't cares.
• That is a d or a × (cross) is entered into each square to signify “don'tcare” MIN/MAX
terms.
• Simplify following Boolean function. F (A, B, C, D) = Σ (0, 1, 2, 10, 11, 14)&d (5, 8, 9)

Fig 1.37 Cell grouping in 4 Variable K-Map with Don’t care conditions

• As shown in K-map in Figure above, by combining 1’s and d’s(Xs), three quads can be
obtained.
• The X in square 5 is left free since it does not contribute in increasing the size of any
group. Therefore, the
• I Quad covers minterms 0, 2, 10 and d8
• II Quad covers minterms 10, 11 and d8, d9.
• III Quad covers minterms 0, 1 and d8, d9.
• A pair covers minterms 10 and 14.
• Therefore the final expression is

1.14. Combinational circuits:

1.14.1 Combinational circuits:

• Combinational circuit consists of logic gates whose outputs at any time are determined
directly from the present combination of inputs without regard to previous inputs.

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• Combinational circuit is a combination of different gates. For example: encoder, decoder,

multiplexer and de-multiplexer etc. are some combinational circuits.
• Some of the characteristics of combinational circuits are following:
• The output of combinational circuit at any instant of time depends only on the levels
present at input terminals.
• The combinational circuit does not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
• A combinational circuit can have a n number of inputs and m number of outputs.

Fig 1.38 Block Diagram Representation of Combinational Circuit

Fig 1.39 Classification of Combinational Logic Circuits

1.14.2 Design Procedure:

• Design procedure of combinational Logic circuit:
• The problem is stated
• The number of available input variables and required output variables is determined
• The input and output variables are assigned letter symbols
• The truth table that defines the required relationship between inputs and outputs is
derived
• The simplified Boolean function for each output is obtained

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• The logic diagram is drawn.

Code converter:
• Code Converters are the digital circuits or algorithms that are designed to translate data
representation from one format to the other format.
Binary to Gray Code Converter:
• The binary-to-Gray code converter takes binary input and translates it to its
corresponding gray code representation.
• The number of input variables is 4; the number of output variables required is also 4.
• Let the input variables be b3,b2,b1,b0 and output variables be g3,g2,g1,g0.
• Then a Truth table is developed for binary to gray code conversion.
• Next 4 variable k-maps are used to obtain expressions for gray code g3,g2,g1,g0.
• Finally circuit is designed from the equations obtained.
Table 1.27 Truth table for binary to gray code conversion

b3b2b1b0 g3g2g1g0
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000

Fig 1.40 K-map for g0

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Fig 1.41 K-map for g1

Fig 1.42 K-map for g2

Fig 1.43 K-map for g3

• Expressions for gray code in terms of binary

• g0=b0b1′+b1b0′=b0 XOR b1
• g1=b2b1′+b1b2′=b1 XOR b2

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• g2=b2b3′+b3b2′=b2 XOR b3
• g3=b3

Fig 1.44 Circuit Diagram for binary to gray code conversion

1.14.3 Half Adder, Full Adder :

Adders:
• Digital computers perform various arithmetic operations. The most basic arithmetic
operation is the addition of two binary digits.
• Different types of adders are discussed below:
Half Adder
• Half adder is a combinational logic circuit that performs the addition of two bits.
• Half adder circuit needs two binary inputs and two binary outputs.
• The input variables designate the augend and addend bits, the output variables produce
the sum and carry.
A Sum(S)

B Carry(c)

Half adder

Fig 1.45 Block diagram for Half Adder

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Table 1.28 Truth table for Half Adder

Inputs Outputs
A B Sum(s) Carry(c)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Fig 1.46 Circuit diagram for Half Adder

• Logic Equations:
• Sum(s)= A⊕B; Carry(c)=AB;

Full Adder
• The combinational circuit that performs the addition of three bits (two significant bits and
previous carry) is called full adder. It consists of three inputs and two outputs.
• Two significant bits represented as A and B and the third input Cin represents the carry
from the previous lower significant position. The two outputs are Sum (s) and Carry(c).

A Sum(s)

B Full Adder Carry(c )

Cin

Fig 1.47 Block diagram for Full Adder

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Table 1.29 Truth table for Full Adder

Inputs outputs
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Fig 1.48 Circuit diagram for Full Adder

• Logic Equations:
• Sum(s)=A XOR B XOR Cin
• Carry(c)=AB + BCin + ACin

1.14.4 Half Subtractor, Full Subtractor :

Half Subtractor
• A Half subtractor is a combinational circuit that subtracts two bits and produces their
difference.
• It produces the difference between the two binary bits at the input and also produces an
output Borrow to indicate if a1 has been borrowed.
• In the subtraction A−B, A is called as Minuend bit and B is called as Subtrahend bit.

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A Difference(D)

B Borrow(B)

Half Subtractor
Fig 1.49 Block diagram for Half Subtractor

Table 1.30 Truth table for Half Subtractor

Inputs Outputs
A B Difference(D) Borrow(B)
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Fig 1.50 Circuitdiagram for Half Subtractor

• Logic Equations:

• Difference(D)= A⊕B; Borrow(B)=A1B;

Full Subtractor:
• The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is
a combinational circuit with three inputs A, B, Bin and two output D and Bout.
• A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D
is the difference output and B is the borrow output.

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A Difference(D)

B Full Subtractor Borrow(Bout)

Bin

Fig 1.51 Block diagram for Full Subtractor

Table 1.31 Truth table for Full Subtractor

Inputs Outputs
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Fig 1.52 Circuit diagram for Full Subtractor

• Logic Equations:
• Difference(D)= A ⊕B⊕Bin, borrow = A1B + A1Bin +BBin

1.15 Decoders:
• A decoder is a combinational circuit. It has n input and to a maximum= 2n outputs.
• Decoder is identical to a demultiplexer without any data input. It performs operations

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which are exactly opposite to those of an encoder.

Fig 1.53 Block diagram of Decoder

1.15.1 3x8 Decoder:

• In 3 to 8 line decoder, it includes three inputs and eight outputs.
• Here the inputs are represented through A, B & C whereas the outputs are represented
through D0, D1, D2…D7.
• The selection of 8 outputs can be done based on the three inputs. So, the truth table of this
3 line to 8 line decoder is shown below.
• From the following truth table, we can observe that simply one of 8 outputs from DO –
D7 can be selected depending on 3 select inputs.
Table 1.32 Truth table for 3x8 Decoder

A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

• From the above truth table of 3 lines to 8 line decoder, the logic expression can be defined
as

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• Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Fig 1.54 Block diagram of 3x8 Decoder

Fig 1.55 Circuit diagram of 3x8 Decoder

1.15.2 4X16 Decoder with two 3x8 Decoders:

• In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……, Y16 and
four inputs, i.e., A0, A1, A2, and A3.
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• The 3 to 16 line decoder can be constructed using either 2 to 4 decoder or 3 to 8 decoder.

• There is the following formula used to find the required number of lower-order decoders.
• Required number of lower order decoders=m2/m1.m1 =8 ,m2 = 16

Required number of 3 to 8 decoders= =2

Fig 1.56 Block diagram of 4x16 Decoder using two 3x8 Decoders

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Table 1.33 Truth table for 4X16 Decoder

• The logical expression of the term A0, A1, A2,…, A15 are as follows:
• Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3

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Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Fig 1.57 Circuit diagram of 4x16 Decoder using two 3x8 Decoders

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1.16 Multiplexers:
• A digital multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• Normally there are 2n input lines and a selection lines whose bit combinations determine
which input is selected.
• E is called the strobe or enables input which is useful for the cascading.
• It is generally an active low terminal that means it will perform the required operation
when it is low.

Fig 1.58 Block diagram for Multiplexer

• Multiplexers come in multiple variations

• 2:1 multiplexer
• 4:1 multiplexer
• 16:1 multiplexer
• 32:1 multiplexer

1.16.1 2X1 Multiplexer, 4X1 Multiplexer:

2X1 Multiplexer:
• A 2 to 1 line multiplexer consists of 2 input lines and one select line and single output
line.

Fig 1.59 Block diagram for 2x1Multiplexer

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Table 1.34 Truth table for 2x1 Multiplexer

• The logical expression of the term Y is Y=S0'.A0+S0.A1

Fig 1.60 Circuit diagram for 2x1Multiplexer

4X1 Multiplexer:
• In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection
lines, i.e., S0 and S1 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection lines S0 and S1,
one of these 4 inputs are connected to the output.

Fig 1.61 Block diagram for 4x1Multiplexer

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Table 1.35 Truth table for 4x1 Multiplexer

• The logical expression of the term Y is Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Fig 1.62 Circuit diagram for 4x1Multiplexer

1.16.2 Boolean Function Implementation using Multiplexer:

• Given a SOP function and a multiplexer is also given. We will need to implement the
given SOP function using the given MUX. There are certain steps involved in it:
• Step 1: Draw the truth table for the given number of variable function.
• Step 2: Consider one variable as input and remaining variables as select lines.
• Step 3: Form a matrix where input lines of MUX are columns and input variable and its
complement are rows.
• Step 4: Find AND between both rows on the basis of the truth table.
• Step 5: Hence whatever is found is considered as input of MUX. We will illustrate it
with an example:
• Example: Given SOP function f(A, B, C) = m(0, 1, 4, 6, 7) and MUX is 4x1
• For 3 variable function, the truth table is

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Table 1.36 Truth table for the function f(A, B, C) = m(0, 1, 4, 6, 7)

• Let A and B are the select lines and C be the input,

Fig 1.63 Finding inputs for realizing function using mux

• Thus, for the implementation of given logical function, required is one 4×1 MUX and
inverter.

Fig 1.64 4x1 mux implementing function f(A, B, C) = m(0, 1, 4, 6, 7)

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1.1 Binary Numbers

Objective Questions
1. What is the radix of Binary number system [ ]
a) 2
b) 4
c) 3
d) 1
2. What are the possible Values in Binary number system [ ]
a) 0,1
b) 1,2
c) 0,1,2
d) 0,2
1.2 Fixed Point Representation
Objective Questions
1. What is the fixed point representation of a binary number 0101.101 for a length of
8 bits where six reserved for integer and two for fraction? [ ]
a) 00101.101
b) 00101.10
c) 0101.1010
d) 101.10100
1.3 Floating Point Representation
Objective Questions

1. The parts of a floating point number are [ ]

a) Exponent, Mantissa
b) Exponent, Radix
c) Mantissa, Radix
d) Power, Exponent
1.4 Number Base Conversions
Objective Questions

1. Let (A2C) 16 = (X) 8. Solve value of X [ ]

a) 7054
b) 6054

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c) 5154
d) 5054
2. The (128)10 = (1003) b, calculate the possible base b is [ ]
a) 3
b) 4
c) 5
d) 6
3. Convert decimal number 227 to hexadecimal number [ ]
a) A3
b) E3
c) CC
d) C3
4. The binary number 10110.11 is expressed in decimal format is [ ]
a) 16.75
b) 20.75
c) 16.50
d) 22.75

Descriptive Questions

S.No Questions BL
Describe the conversion of decimal number to hexadecimal number with an
1 example. L2
2 Express the following decimal numbers in octal format : a)4796 b) 8957.75 L2

Represent the following numbers with the given radix in decimal format
3 i) (334)5 ii) (12345)7 iii) (768)9 L2
Compute the following
4 i) (AD012)16 = (X)5 ii) (5.204)10 = (X)3 L2
Compute the following
5 a) (137.64)10 = ( )6 = ( )2 b)(1111.1011)2= ( )8=( )16 L2

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1.5 Octal and Hexadecimal Numbers

Objective Questions

1. What is the radix of Octal number system [ ]

a) 7
b) 8
c) 9
d) 10
2. What is the radix of Hexadecimal number system [ ]
a) 6
b) 10
c) 16
d) 8
3. Which of the following is a valid Octal number [ ]
a) 789
b) 3567
c) 5678
d) 987
4. Which of the following is a valid Hexadecimal number [ ]
a) FACE.DEAF
b) HEAD
c) 98GH
d) 87FG
1.6 Complements
Objective Questions

1. 4-bit 2’s complement representation of a decimal number is 1000. The number is

expressed as [ ]
a) +8
b) 0
c) -7
d) -8
2. The 2’s complement representation of -17 is [ ]
a) 101110
b) 101111

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c) 111110
d) 110001
3. 11001, 1001 and 111001 correspond to the 2's complement representation of which
one of the following sets of number? [ ]
a) 25,9 and 57 respectively
b) -6, -6 and -6 respectively
c) -7, -7 and -7 respectively
d) -25, -9 and -57 respectively
4. An equivalent 2's complement representation of the 2’s complement number is 1101
is [ ]
a) 110100
b) 001101
c) 110111
d) 111101
5. 2's complement representation of a 16 bit number (one sign bit and 15 magnitude bits)
is FFFF, Its magnitude in decimal representation is [ ]
a) 0
b) 1
c) 32,767
d) 65,535
Descriptive Questions
S.No Questions BL
Compute Subtraction of (0001.1110)2 from (0011.1001)2 using 2’s
1 complement method. L3
2 If A = -57 and B = +38, then represent A and B in 8-bit 2’s
complement. L3
3 Calculate the following operations using r-1’s complement
arithmetic: L3
i) (+43)10 − (−53)10. ii) (+346.56)10 − (+456.78)10.

1.7 Signed Binary Numbers

1. The range of .signed decimal numbers that can be represented by 6 bit 1’s
complement form is [ ]

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a) -31 to +31
b) -63 to +64
c) -64 to +63
d) -32 to+31
2. The range of signed decimal numbers that can be represented by 6-bit 2’s
complement number is [ ]
a) -31 to +31
b) -63 to +63
c) -64 to +63
d) -32 to +31
3. The two numbers represented in signed 2’s complement form are P = 11101101, Q =
11100110. Then P - Q, in signed 2’s complement form is [ ]
a) 100000111
b) 00000111
c) 11111001
d) 111111001
Descriptive Questions

S.No Questions BL
1 If A = -57 and B = +38, then represent A and B in 8-bit Signed 2’s
complement. Compute (i) A + B (ii) A - B L3
2 Describe how numbers are represented in signed binary form. L1

1.8 Binary Codes

Objective Questions

1. Decimal 43 in Hexadecimal and BCD number system is expressed as [ ]

a) B2, 0100 011
b) 2B, 0100 0011
c) 2B, 0011 0100
d) B2, 0100 0100
2. Tell how many bits are in an ASCII character? [ ]
a) 16
b) 8
c) 7
d) 14

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3. Decimal 11 in BCD is expressed as ________ [ ]

a) 00001011
b) 00001100
c) 00010001
d) 00010010
4. Recognize which of the following is an invalid BCD code? [ ]
a) 0011
b) 1101
c) 0101
d) 1001
5. The binary-coded decimal (BCD) system can be used to represent each of the 10
decimal digits as an [ ]
a) 4-bit binary code
b) 8-bit binary code
c) 16-bit binary code
d) ASCII code
6. The decimal number 874 is expressed in BCD code as : [ ]
a) (100001110100) BCD
b) (010001111000) BCD
c) (100001000111) BCD
d) (011110000100) BCD

Descriptive Questions

S.No Questions BL
1 Express the equivalent (743)10 in BCD, 2421 and 6421 codes. L2
2 What are the different types of non-weighted codes and explain them with L2
examples.
3 Explain the conversion of (1101) binary code to gray code with detailed steps? L2
4 Represent the unsigned decimal numbers 351 and 986 in BCD, and then L2
show the steps necessary to form their sum.
5 Represent numeric digits 0 to 9 at least in any two self-complementing codes. L2
1.9 Basic Logic Functions
Objective Questions

1. The Boolean expression A+BC in reduced form is expressed as [ ]

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a) AB+BC
b) (A+B)(A+C)
c) (A+C)B
d) AB
2. Solve A+AB+ABC+ABCD+ABCDE+---- = [ ]
a) 1
b) A
c) A+AB
d) AB

Descriptive Questions

S.No Questions BL
1 Apply De-Morgan’s theorem, convert the following Boolean expression to L3
equivalent expression that have only OR and complement operations
F=𝑥̅ 𝑦̅ + 𝑥̅ 𝑧 + 𝑦̅𝑧
2 State and prove Demorgan’s theorem. L1
3 Given AB’+ A’B=C, then Solve AC’+A’C=B. L3

1.10 Logic Gates

Objective Questions

1. Boolean expression for the output of XNOR logic gate with inputs A and B is
described as [ ]
a) AB’ + A’B
b) (AB)’ + AB
c) (A’ + B)(A + B’)
d) (A’ + B’)(A + B)
2. Describe the Boolean expression for the logic circuit shown below. [ ]

a) C(A+B)DE
b) [C(A+B)D+E’]

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c) [C(A+B)D]E’
d) ABCDE
3. For the circuit shown below, the output F is expressed by [ ]

a) 1
b) 0
c) x
d) x’
4. For the logic circuit shown in the figure the required input(A,B,C) condition to
describe the output(X) = 1 is [ ]

a) (1,0,1)
b) (0,0,1)
c) (1,1,1)
d) (0,1,1)
5. For the circuit shown below the output is expressed as [ ]

a) (PR OR Q)XOR R
b) (PR AND Q)XOR R
c) (PR NOR Q)XOR R
d) (PR XOR Q) XOR R
6. The output of the combinational circuit given below is represented as [ ]

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a) A+B+C
b) A(B+C)
c) B(B+A)
d) C(A+B)

Descriptive Questions

S.No Questions BL
1 Show that the dual of the exclusive-OR is equal to its complement L2
2 Discuss about Logic gates with their truth tables, Logic symbols, waveforms L2

1.11Universal Logic Gates

Objective Questions

1. If and only if all of the inputs are on, the output will be off. The gate is [ ]
a) NAND
b) NOR
c) X-OR
d) OR
2. The number of NAND gates required to realize AND,XOR,OR gates are [ ]
a) 2,4,3
b) 3,4,2
c) 1,4,3
d) 2,5,3
3. The number of NAND gates required to realize X-NOR,NOR gates are [ ]
a) 5,4
b) 4,5
c) 4,3
d) 3,4
4. The number of NOR gates required to realize AND,XOR,OR gates are [ ]
a) 2,5,3
b) 3,5,2
c) 1,5,3
d) 2,4,3
5. The number of NOR gates required to realize X-NOR,NAND gates are [ ]

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a) 4,4
b) 5,5
c) 4,5
d) 5,4

Descriptive Questions

S.No Questions BL
1 Realize Logic gates using NOR gate L3
2 Realize Logic gates using NAND gate L3

1.12 Minimization of Logic Expressions

Objective Questions

1. Convert The following Boolean expression Y=

to its minimized form [ ]
a)
b)
c)
d)

Descriptive Questions

S.No Questions BL
1 Express the following Boolean expressions to a minimum number of literals L2
𝑖)𝑥̅ 𝑦̅ + 𝑥𝑦 + 𝑥̅ 𝑦 ii) (𝑥 + 𝑦) + (𝑥 + 𝑦̅) ii) 𝑥̅ 𝑦 + 𝑥𝑦̅ + 𝑥𝑦 + 𝑥̅ 𝑦̅

2 Given the following Boolean expression, reduce it to minimum number of L2

literals
F= 𝑥𝑦𝑧̅̅̅ + 𝑥̅ 𝑦̅𝑧 + 𝑤
̅𝑥𝑦 + 𝑤𝑥̅ 𝑦 + 𝑤𝑥𝑦

1.13 K-map Simplifications

Objective Questions

1. If f(A,B,C,D)=1 then identify the number of logic 1’s present in K-map [ ]

a) 4
b) 8

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c) 16
d) 32

2. The K – map for a Boolean function is shown in the figure. Identify the number of
essential prime implicants for this function is [ ]

a) 4
b) 5
c) 6
d) 7

3. The number of product terms in the minimized sum of product expression obtained
after computing the following through karnaugh map (where d indicates don't care
conditions). [ ]

1 0 0 1

0 D 0 0

0 0 D 1

0 0 0 1

a) 2
b) 3
c) 4
d) 5

Descriptive Questions

S.No Questions BL
1 Minimize the function f(a,b) =∑m(0,1,2) using 2-variable k-map L2
2 Minimize the function f(a,b) =∑m(0,1,3) using 2-variable k-map L2

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3 Minimize the function f(a,b) =πM(0,2) using 2-variable k-map L2

4 Minimize the function f(a,b) =πM(0,3) using 2-variable k-map L2
5 Minimize the function f(a,b,c) =∑m(0,1,2,7) using 3-variable k-map L2
6 Minimize the function f(a,b,c) =∑m(0,1,3,5,6) using 3-variable k-map L2
7 Minimize the function f(a,b,c) =πM(0,2,4,5) using 3-variable k-map L2
8 Minimize the function f(a,b,c) =πM(0,1,3,7) using 3-variable k-map L2
9 Minimize the function f(a,b,c,d) =∑m(0,1,2,7,8,10,13,15) using 4-variable k- L2
map
10 Minimize the function f(a,b,c,d) =∑m(0,1,3,4,6,9,11) using 4-variable k-map L2
11 Minimize the function f(a,b,c,d) =πM(0,2,6,10,14,15) using 4-variable k-map L2
12 Minimize the function f(a,b,c,d) =πM(0,3,4,7,8,11,12,14) using 4-variable k- L2
map
13 Minimize the function f(a,b) =∑m(0,1)+d(2) using 2-variable k-map L2
14 Minimize the function f(a,b,c) =∑m(0,1,3,5,6)+d(1,4) using 3-variable k-map L2
15 Minimize the function f(a,b,c,d) =∑m (0,2,4,8,9,13)+d(1,6) using 4-variable k- L2
map
16 Minimize the function f(a,b,c,d) =πM(0,3,5,6,9,14).d(1,8,10) using 4-variable L2
k-map

1.14 Combinational Circuits

Objective Questions

1. Sum of Full Adder can be described using [ ]

a) Sum= A XOR B XOR Cin
b) Sum= A XNOR B XNOR Cin
c) Sum= A XOR B XNOR Cin
d) Sum= A XNOR B XOR Cin

2. Sum of Half Adder can be described using [ ]

a) Sum= A XOR B
b) Sum= A XNOR B
c) Sum= A AND B
d) Sum= A XOR Cin

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3. Carry of Half Adder can be described using [ ]

a) Carry = (A .B)
b) Carry = (A +B)
c) Carry = (A .B)’
d) Carry = (A +B)’

4. Carry of Full Adder can be described using [ ]

a) Carry = (A .B) +(B.Cin)+(Cin.A)
b) Carry = (A +B) .(B+Cin).(Cin+.A)
c) Carry = (A .B)’ +(B.Cin)’+(Cin.A)’
d) Carry = (A +B)’ .(B+.Cin)’.(Cin+A)’

5. Difference of Full Subtractor can be described using [ ]

a) Difference= A XOR B XOR Bin
b) Difference= A XNOR B XNOR Bin
c) Difference = A XOR B XNOR Bin
d) Difference= A XNOR B XOR Bin

6. Difference of Half Subtractor can be described using [ ]

a) Difference= A XOR B
b) Difference = A XNOR B
c) Difference = A AND B
d) Difference = A XOR Cin

7. Borrow of Half Subtractor can be described using [ ]

a) Borrow = (A’ .B)
b) Borrow = (A’ +B)
c) Borrow = (A’.B)’
d) Borrow = (A’+B)’

8. Carry of Full Adder can be described using [ ]

a) Borrow = (A’.B) +(B.Bin)+(Bin.A’)
b) Borrow = (A +B) .(B+Bin).(Bin+.A’)
c) Borrow = (A .B)’ +(B.Bin)’+(Bin.A)’
d) Borrow = (A +B)’ .(B+.Bin)’.(Bin+A)’

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Descriptive Questions

S.No Questions BL
1 Define combinational logic? Explain the design procedure for combinational L2
circuits
2 Explain the operation of half subtractor with truth table? Construct half L2
subtractor using logic gates.
3 Explain the operation of full subtractor with truth table? Construct full L2
subtractor using logic gates.
4 Explain the operation of half adder with truth table? Construct half adder L2
using logic gates.
5 Explain the operation of full adder with truth table? Construct full adder L2
using logic gates.

1.15 Decoders
Objective Questions

1. State number of outputs on a 3 x 8 decoder? [ ]

a) 4
b) 16
c) 8
d) 10

2. A decoder is described as a circuit which converts ________. [ ]

a) Non coded information into coded form
b) Coded information into non coded form
c) HIGHs to LOWs
d) LOWs to HIGHs

3. State number of inputs on a 4 X16 decoder? [ ]

a) 4
b) 16
c) 8
d) 10

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Descriptive Questions

S.No Questions BL
1 What is decoder? Draw the logic diagram of 3 to 8 line decoder and L2
explain its operation.
2 Construct 4 to 16 line decoder using 3 to 8 line decoder and explain its L2
operation.

1.16 Multiplexers
Objective Questions

1. A multiplexer is also named as [ ]

a) data accumulator
b) data restorer
c) data selector
d) data distributor

2. Identify The logic function implemented by the circuit below is (ground implies a
logic “0”) [ ]

a) F= AND (P, Q)
b) F= OR (P, Q)
c) F= XNOR (P, Q)
d) F= XOR (P, Q)

Descriptive Questions

S.No Questions BL
1 What is Multiplexer? Draw the logic diagram of 4 to 1 line Multiplexer and L2
explain its operation.

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2 Develop the logic expression given below using a (i) 8:1 MUX (ii) 4:1 MUX L2
f=∑ m (0,1,3,4.5)
3 Draw the logic diagram of 8 to 1 line Multiplexer and explain its operation. L2

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UNIT II
DIGITAL LOGIC CIRCUITS -II

Course Objectives

• To familiarize with the concepts of different sequential circuits.

Course Outcomes
Students can able to
• understand the functionality of different latches and flip-flops..
• distinguish the working of latch and flip-flop.
• convert from one flip-flop to another flip-flop.
• classify various types of registers.
• design synchronous and asynchronous counters.
Syllabus
2.0 Introduction

2.1 Sequential Circuits

2.2 Flip-Flops

2.2.1 RS Flip-Flop

2.2.2 D-Flip-flop

2.2.3 JK Flip Flop

2.2.4 2.2.4 T Flip-Flop

2.2.5 Race around Condition and Solution

2.2.6 Flip-Flop Excitation Table

2.3 Register

2.4 Shift Registers

2.4.1 Bidirectional Shift Registers

2.4.2 Universal Shift Register

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2.4.3 Applications of Shift Registers

2.5 Binary Counters

2.5.1 Types of Binary Counters

2.6 Ripple Counter

2.6.1 Binary Ripple Counter

2.6.2 Design of Asynchronous BCD Counter

2.6.3 Design of a Mod-6 asynchronous counter using T FFs

2.7 Synchronous Counters

2.7.1 Binary Counter

2.7.2 Procedure to design synchronous counters

2.7.2.1 Design of two-bit synchronous counter using T flip flop

2.7.2.2 Design of 4-bit synchronous up counter using T flip flop

2.0 Introduction
• Combinational circuits are those whose output at any instant of time is entirely dependent on the
input present at that time.

• On the other hand Sequential circuits are those in which output at any given time is not only
dependent on the present input but also on previous outputs. Naturally, such circuits must record
the previous outputs which give rise to memory.

• Often, there are requirements of digital circuits whose output remain unchanged, once set, even if
the inputs are removed. Such devices are referred as “memory elements”, each of which can hold

1-bit of information. These binary bits can be retained in the memory indefinitely (as long as
power is delivered) or until new information is feeded to the circuit.

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Fig 2.1: Block diagram of a sequential circuit

• Block diagram of a sequential circuit, whichcan be regarded as a collection of memory elements

and combinational circuit as shown in above Fig.2.1.

• A feedback path is formed by using memory elements, input to which is the output of
combinational circuit.

• The binary information stored in memory element at any given time is defined as the state of
sequential circuit at that time. Present contents of memory elements are referred as the present
state.

• The combinational circuit receives the signals from external input and from the memory output
and determines the external output.

• They also determine the condition and binary values to change the state of memory. The new
contents of the memory elements are referred as next state and depend upon the external input and
present state.

• Hence, a sequential circuit can be completely specified by a time sequence of inputs, outputs and
the internal states. In general, clock is used to control the operation. The clock frequency
determines the speed of operation of a sequential circuit.

2.1 Sequential Circuits:

There exist two main categories of sequential circuits, namely synchronous and asynchronous
sequential circuits.

2.1. 1 Asynchronous Sequential Circuits:

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• Sequential circuits whose behavior depends upon the sequence, in which the inputs are applied,
are called Asynchronous Sequential Circuits.

• In these circuits, outputs are affected whenever a change in inputs is detected. Memory elements
used in asynchronous circuits mostly are time delay devices.

• The memory capability of time delay devices is due to the propagation delay of the devices.
Propagation delay produced by the logic gates is sufficient for this purpose.

• Hence “An Synchronous sequential circuit can be regarded as a combinational circuit with
feedback”. However feedback among logic gates makes the asynchronous sequential circuits,
often susceptible to instability.

• As a result they may become unstable. This makes the design of asynchronous circuits very
tedious and difficult.

2.1.2 Synchronous Sequential Circuit:

• It may be defined as a sequential circuit, whose state can be affected only at the discrete instants
of time.

• The synchronization is achieved by using a timing device, termed as System Clock Generator,
which generates a periodic train of clock pulses.

• The clock pulses are feed to entire system in such a way that internal states (i.e. memory contents)
are affected only when the clock pulses hit the circuit.

2.1.3 Storage Elements:

Latches

• A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states.

• The major differences among various types of storage elements are in the number of inputs they
possess and in the manner in which the inputs affect the binary state.

• Storage elements that operate with signal levels (rather than signal transitions) are referred to as
latches; those controlled by a clock transition are flip-flops. Latches are said to be level sensitive
devices; flip-flops are edge sensitive devices.

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2.2 Flip - Flops

• The synchronous sequential circuit which uses clock at the input of memory elementis referred as
Clocked Sequential circuit and the memory element in this circuit known as Flip-Flop that can
store 1-bit of information, and thus forms a 1-bit memory cell.

• These circuits have two outputs, one giving the value of binary bit stored in it and the other gives the
complemented value.

• The real differences among various flip-flops are the number of inputs and the manner in which
binary information can be entered into it

• The flip-flops are 1-bit memory cells that can maintain the stored bit for desired period of time which
consists of two stable stages so it is called as Bi-stable device and states are 0V and + 5V
corresponding to Logic 0 and Logic 1 respectively

2.2.1 RS Flip-Flop

• A flip-flop circuit can be constructed either by using two 2-input OR gate or NAND gates. These
circuits consists of a cross coupled connection from output of one gate to the input of the other gate
constitutes a feedback path. Each flip-flop has two outputs, Q and Q’, and two inputs, set, reset.

• The operation of basic flip-flop can be modified by proving an additional control input that
determines when the state of the circuit is to be changed.

• An RS flip-flop with a clock pulse (CP) input, which consists of a basic flip-flop circuit and two
additional NAND gates, is as shown in Fig. 2.2.

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Fig.2.2 RS flip-flop with NAND gates

2.2.2 D-Flip-flop

• The SR latch, which has two inputs S and R. At any time to store a bit, must activate both the inputs
simultaneously. This may be troubling in some applications. Use of only one data line is convenient
in such applications.

• Moreover the forbidden input combination S = R = 1 may occur unintentionally, thus leading the flip-
flop to indeterminate state. In order to deal such issues, SR flip-flop is further modified as shown in
Fig 2. 3.

• The resultant is referred as D flip-flop which has only one input labelled D (called as Data input). An
external NAND gate (connected as inverter) is used to ensure that S and R inputs are always
complement to each other. Thus to store information in this latch, only one signal has to be
generated.

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Fig 2. 3. D flip-flop or D latch

• Operation of this flip-flop is straight forward. At any instant of time the output Q is same as D (i.e. Q
2..1.1 = D). Since output is exactly same as the input, the latch may be viewed as a delay unit.

• The flip-flop always takes some time to produce output, after the input is applied. This is called
propagation delay.

• Thus it is said that the information present at point D (i.e. at input) will take a time equal to the
propagation delay to reach to Q. Hence the information is delayed. For this reason it is often called as
Delay (D) Flip-Flop.

2.2.3 JK Flip Flop

• A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined
in the JK type.

• Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the
letter J is for set and the letter K is for clear).

• When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its
complement state, ie., if Q=1, it switches to Q=0 and vice versa. A clocked JK flip-flop is shown in
Fig. 2.4.

• Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if
Q was previously 1.

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• Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only
if Q' was previously 1.

Fig 2.4 JK Flip-flop

2.3 Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while
J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions
of the outputs.

2.4 To avoid this, the clock pulses must have a time duration less than the propagation delay through
theflip-flop.

2.5 The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction.
The same reasoning also applies to the T flip-flop presented next.

2.2.4 T Flip-Flop

• The T flip-flop is a single input version of the JK flip-flop which is shown, in Fig 2.5 and it is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with
each clock pulse.

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Fig 2. 5 Clocked T flip-flop

2.2.5 Race around Condition and Solution

• Whenever the width of the trigger pulse is greater than the propagation time of the flip-flop, then flip-
flop continues to toggle 1-0-1-0 until the pulse turns 0.

• When the pulse turns 0, unpredictable output may result i.e. the state and output not known. This is
called race around condition.

• In level-triggered flip-flop circuits, the circuit is always active when the clock signal is high, and
consequently unpredictable output may result. For example, during this active clock period, the output
of a T-FF may toggle continuously.

• The output at the end of the active period is therefore unpredictable. To overcome this problem, edge
triggered circuits can be used whose output is determined by the edge, instead of the level, of the clock
signal, for example, the rising (or trailing) edge.

• Another way to resolve the problem is the Master-Slave circuit shown in Fig 2. 6.

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Fig 2. 6 Master slave circuit

The operation of a Master-Slave FF has two phases as shown in Fig 2.6

• During the high period of the clock, the master FF is active, taking both inputs and feedback from the
slave FF. The slave FF is de-activated during this period by the negation of the clock so that the
new output of the master FF won’t affect it.

• During the low period of the clock, the master FF is deactivated while the slave FF is active. The output
of the master FF can now trigger the slave FF to properly set its output. However, this output will
notaffect the master FF through the feedback as it is not active.

Fig 2. 7 Master slave operation

• It is seen that the trailing edge of the clock signal will trigger the change of the output of the Master -
Slave FF. The master-slave combination can be constructed for any type of flip-flop by adding a
clocked RS flip-flop with an inverted clock to form the slave. A master-slave JK flip-flop
constructed with NAND gates is shown in Fig 2.8.

• It consists of two flip-flops; gates1 through 4 form the master flip-flop, and gates 5 through 8 form the
slave flip-flop. The information presented at the J and K inputs is transmitted to the master flip-flop
on the positive edge of the clock pulse and is held there until the negative edge of the clock pulse
occurs, after which it is allowed to pass through to the slave flip-flop.

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• The clock input is normally 0, which keeps the outputs of gates 1 and 2 at the 1 level. This prevents
the J and K inputs from affecting the master flip-flop.

• The slave flip-flop is a clocked RS type, with the master flip-flop supplying the inputs and the clock
input being inverted by gate 9. When the clock is 0, the output of gate 9 is 1, so that output Q is
equalto Y, and Q’ is equal to Y’.

• When the positive edge of a clock pulse occurs, the master flip-flop is affected and may switch states.
The slave flip-flop is isolated as long as the clock is at the level1, because the output of gate 9
provides a 1 to both inputs of the NAND basic flip-flop of gates 7 and 8.

• When the clock input returns to 0, the master flip-flop is isolated from J and K inputs and the slave
flip-flop goes to the same state as the master flip-flop.

Fig 2.8 Clocked master-slave JK flip-flop

2.2.6 Flip-Flop Excitation Table

• The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop
inputs is known and if the value of the flip-flop output Q after the rising edge of the clock signal.
As with any other truth table, the map method is used to derive the characteristic equation for each
flip-flop.

• During the design process the transition from present state to the next state s usually known and flip -
flop input conditions are found that will cause the required transition. For this reason a table that
lists the required inputs for a given change of state is needed. Such a list is called the excitation
table.

• There are four possible transitions from present state to the next state. The required input conditions
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are derived from the information available in the characteristic table.

• The symbol X in the table represents a “don’t care” condition, thatis, it does not matter whether the
input is 1 or 0.

• The different types of flip flops (RS, JK, D, T) can also be described by their excitation, table 1 as
shown. The left side shows the desired transition from Qn to Qn+1, the right side gives the
triggering signals of various types of FFs needed for the transitions.

Table 2.1: Excitation table

2.3 Register
• A clocked sequential circuit consists of a group of flip‐flops and combinational gates. The flip‐flops
are essential because, in their absence, the circuit reduces to a purely combinational circuit
(providedthat there is no feedback among the gates).

• A circuit with flip‐flops is considered a sequential circuit even in the absence of combinational gates.
Circuits that include flip‐flops are usually classified by the function they perform rather than by the
name of the sequential circuit. Two such circuits are registers and counters.

• A register is a group of flip‐flops, each one of which shares a common clock and is capable of storing
one bit of information. An n ‐bit register consists of a group of n flip‐flops capable of storing n bits
ofbinary information.

• In addition to the flip‐flops, a register may have combinational gates that perform certain data‐
processing tasks. In its broadest definition, a register consists of a group of flip‐flops together with
gates that affect their operation.
• The flip‐flops hold the binary information, and the gates determine how the information is transferred
into the register.
• A counter is essentially a register that goes through a predetermined sequence of binary states. The

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gates in the counter are connected in such a way as to produce the prescribed sequence of states.
• Although counters are a special type of register, it is common to differentiate them by giving them a
different name.
• Various types of registers are available commercially. The simplest register is one that consists of only
flip‐flops, without any gates.

• A register constructed with four D ‐type flip‐flops to form a four‐bit data storage register is shown in
figure 2.9.

Fig 2.9 4 –Bit Register

• The common clock input triggers all flip‐flops on the positive edge of each pulse, and the binary data
available at the four inputs are transferred into the register.

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• The value of ( I 3 , I 2 , I 1 , I 0 ) immediately before the clock edge determines the value of ( A 3 , A
2 , A 1 , A 0 ) after the clock edge.

• The four outputs can be sampled at any time to obtain the binary information stored in the register.

• The input Clear_b goes to the active‐low R (reset) input of all four flip‐flops. When this input goes to
0, all flip‐flops are reset asynchronously.

• The Clear_b input is useful for clearing the register to all 0’s prior to its clocked operation. The R
inputs must be maintained at logic 1 (i.e., de-asserted) during normal clocked operation.

• Note that, depending on the flip‐flop, either Clear, Clear_b, reset, or reset_b can be used to indicate
the transfer of the register to an all 0’s state.

2.4 Shift Registers:

• A register capable of shifting the binary information held in each cell to its neighboring cell, in a
selected direction, is called a shift register.

• The logical configuration of a shift register consists of a chain of flip‐flops in cascade, with the output
of one flip‐flop connected to the input of the next flip‐flop.
• All flip‐flops receive common clock pulses, which activate the shift of data from one stage to the next.
The simplest possible shift register is one that uses only flip‐flops, as shown in Fig 2.10

• The output of a given flip‐flop is connected to the D input of the flip‐flop at its right. This shift register
is unidirectional (left‐to‐right).

• Each clock pulse shifts the contents of the register one bit position to the right. The configuration does
not support a left shift.

• The serial input determines what goes into the leftmost flip‐flop during the shift. The serial output is

taken from the output of the rightmost flip‐flop.

• Sometimes it is necessary to control the shift so that it occurs only with certain pulses, but not with
others. As with the data register discussed in the previous section, the clock’s signal can be suppressed
by gating the clock signal to prevent the register from shifting.

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Fig 2. 10: Four bit Shift register

• A preferred alternative in high speed circuits is to suppress the clock action, rather than gate the clock
signal, by leaving the clock path unchanged, but recirculating the output of each register cell back
through a two‐channel mux whose output is connected to the input of the cell.

• When the clock action is not suppressed, the other channel of the mux provides a data path to the cell.

• Shift registers have found considerable application in arithmetic operations. Since, moving a binary
number one bit to the left is equivalent to multiplying the number by 2 and moving the number one
bitposition to the right amounts to dividing the number by 2.

• Thus, multiplications and divisions can be accomplished by shifting data bits. Shift registers find
considerable application in generating a sequence of control pulses.

Fig 2. 11: Data Transmission in Shift Register

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2.4.1 Bidirectional Shift Registers

• The registers discussed so far involved only right shift operations. Each right shift operation has the
effect of successively dividing the binary number by two.

• If the operation is reversed (left shift), this has the effect of multiplying the number by two.
With suitable gating arrangement a serial shift register can perform both operations.

• A bi-directional, or reversible shift register is one in which the data can be shift either left or
right. Afour-bit bi-directional shift register using D-flip-flops is shown in Fig 2.12.
• Here a set of NAND gates are configured as OR gates to select data inputs from the right or left
adjacentbistables, as selected by the LEFT_/RIGHT control line.

Fig 2.12 4 Bit Bidirectional Shift Register

2.4.2 Universal Shift Register:

A Universal Shift register can shift the data directional along with the parallel load operation. The
following are the functions done by a Universal Shift register.
• A clear control to clear the register to 0.

• A CP input for clock pulse to synchronize all operations

• A shift-right control to enable the shift-right operation and the serial input and output lines
associated with the shift right.

• A shift-left control to enable the shift-left operation and the serial input and output lines associated
with the shift left.

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• A parallel-load control to enable a parallel transfer and n input lines associated with the parallel
transfer.

• N parallel output lines.

• A control state that leaves the information in the register unchanged even though clock pulses are
continuously applied.

Fig 2. 13: 4- Bit Universal Shift Register

• The Universal Shift Register that is shown in Fig.2.13 has all the capabilities that are listed above.
It consists f four D-flip-flops and four multiplexers which has two selection lines. The S1 and S0
inputscontrol the mode of operation of the register which is specified in Table.2

• When S1 S0=00, the present value of the register is applied to the D-inputs of the flip-flops which
forms a path from output of each flip-flop into the input of the same flip-flop. So no change of state
occurs.

• When S1 S0=01, terminal 1 of the multiplexer inputs have a path to the D inputs of the flip-flops which
causes a shift-right operation.

• When S1 S0=10, a shift-left operation results, with the other serial input going into flip-flop A1.
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• Finally, when S1 S0=11, the binary information on the parallel input lines is transferred into the
register simultaneously during next clock pulse.

Table.2: Functional Table for Universal Shift Register

Mode Control
S1 S0 Register Operation

0 0 No change

0 1 Shift right

1 0 Shift left

1 1 Parallel Load

2.4.3 Applications Of Shift Registers

Shift registers can be found in many applications. Here is a list of a few.
• To Produce Time Delay
• To Simplify Combinational Logic
• To Convert Serial Data to Parallel Data

2.5 Binary Counters

• In digital electronics, a binary counter is a type of sequential logic circuit which is able to count in
binary numbers. A binary counter can counter from 0 to 2(n-1), where n is the total number of bits in
the counter.

• Basically, a binary counter is a type of digital circuit which counts the number of clock pulses that
occur over a time period.

• The binary counters are built up of flip flops, where a flip flop is a most elementary memory element
that can store 1-bit of information. In a binary counter, each flip flop represents one bit of the binary
number. The counter increases its count by one whenever a clock pulse occurs.

• For example, a 3-bit binary counter can count from 000 (0) to 111 (7) before wrapping around to 000
again. We can design a binary counter to count up or down. Also, a binary counter has more advanced

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features such as ability to reset the count to zero, to load a specific count, etc.

2.5.1 Types of Binary Counters

There are many types of binary counters present. Some common types of binary counters are defined
as follows −

• Asynchronous Counter − The type of binary counter in which the flip flops do not receive the same
clock pulse at the same time is called an asynchronous counter. The asynchronous counter is also
known as ripple counter. It is the simplest type of binary counter. In the case of asynchronous binary
counter, each flip flop is triggered by the output of the previous flip flop. Therefore, the asynchronous
counters suffer from propagation delay.

• Synchronous Counter − The type of binary counter in which all the flip flops receive the same clock
pulse at the same time is known as a synchronous counter. Since, all the flip flops of the synchronous
counter are triggered by the same clock pulse, therefore, their outputs change simultaneously. This
will result in the no propagation delay between the flip flops.

• Up Counter − The type of binary counter that counts upwards from zero to its maximum count value
is known as up counter. In the case of up counter, the count is increased by one on each clock pulse.

• Down Counter − The type of binary counter that counts downwards from its maximum count value
to zero is known as a down counter. In the down counter, the count value of the counter is decreased
by one on each clock pulse.

• Up/Down Counter − The type of binary counter that can count in both upward and downward
directions is known as a up/down counter. In the up/down counter, the direction of count is determined
by a control input signal.

2.6 Ripple Counter

• A register that goes through a prescribed sequence of states upon the application of input pulses is
called a counter.

• The input pulses may be clock pulses, or they may originate from some external source and may occur
at a fixed interval of time or at random.

• The sequence of states may follow the binary number sequence or any other sequence of states.

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• A counter that follows the binary number sequence is called a binary counter. An n ‐bit binary counter
consists of n flip‐flops and can count in binary from 0 through 2n - 1.

• Counters are available in two categories: ripple counters and synchronous counters.

• In a ripple counter, a flip‐flop output transition serves as a source for triggering other flip‐flops. In
other words, the C (clock)input of some or all flip‐flops are triggered, not by the common clock pulses,
but rather by the transition that occurs in other flip‐flop outputs.

• In a synchronous counter, the C inputs of all flip‐flops receive the common clock.

2.6.1 Binary Ripple Counter

• A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external
clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.

• Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it
way through the flip-flops.

• The MOD of the ripple counter or asynchronous counter is 2 n

if n flip-flops are used. For a 4-bit
counter, the range of the count is 0000 to 1111.

• A counter may count up or count down or count up and down depending on the input control. The
count sequence usually repeats itself. When counting up, the count sequence goes from 0000, 0001,
0010, ... 1110 , 1111 , 0000, 0001, ... etc.

• When counting down the count sequence goes in the opposite manner: 1111, 1110, ... 0010, 0001,
0000, 1111, 1110, ... etc.

• The complement of the count sequence counts in reverse direction. If the uncomplemented output
counts up, the complemented output counts down. If the uncomplemented output counts down, the
complemented output counts up.

• There are many ways to implement the ripple counter depending on the characteristics of the flip flops
used and the requirements of the count sequence.

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▪ Clock Trigger: Positive edged or Negative edged

▪ JK or D flip-flops

▪ Count Direction: Up, Down, or Up/Down

• Asynchronous counters are slower than synchronous counters because of the delay in the transmission
of the pulses from flip-flop to flip-flop.

• With a synchronous circuit, all the bits in the count change synchronously with the assertion of the
clock. Examples of synchronous counters are the Ring and Johnson counter.

• It can be implemented using D-type flip-flops or JK-type flip-flops. The circuit below uses 2 D flip-
flops to implement a divide-by-4 ripple counter (2n = 22 = 4). It counts down.

Fig. 2. 14: Two bit Ripple Conter

• Click on CLK (Red) switch and observe the changes in the outputs of the flip flops. The CLK
switch is a momentary switch (similar to a door bell switch - normally off).
• PR and CLR are both connected to VCC (set to 1)
• The D flip flop clock has a rising edge CLK input. For example Q0 behaves as follows
• The D input value just before the CLK rising edge is noted (Q00).
• When CLK rising edge occurs, Q0 is assigned the previously noted D value (Q00).

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• Thus, whenever a rising edge appears at the CLK of the D flip flop, the output Q
changes state (or toggles).
• The MOD or number of unique states of this 2 flip flop ripple counter is 4 (22).
• Simulate and Breadboard the Ripple Counter circuit.
• A Truncated Ripple Counter is used if a MOD of less than 2n is required. For example, if
you want to change the sequence from 3,2,1,0,3,2,1,0 ... to 3,2,0,3,2,0 ...

2.6.2 Design of Asynchronous BCD Counter

• A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9. Such a counter
must have at least four flip‐flops to represent each decimal digit, since a decimal digit is
represented by a binary code with at least four bits.

• The sequence of states in a decimal counter is dictated by the binary code used to represent a decimal
digit. If BCD is used, the sequence of states is as shown in the state diagram of Fig 2.15. A decimal
counter is similar to a binary counter, except that the state after 1001 (the code for decimal digit 9)
is0000 (the code for decimal digit 0).

Fig 2.15 State Diagram of BCD counter

• The logic diagram of a BCD ripple counter using JK flip‐flops is shown in Fig 2.16, the four outputs are
designated by the letter symbol Q, with a numeric subscript equal to the binary weight of the
corresponding bit in the BCD code.

• Note that the output of Q1 is applied to the C inputs of both Q2 and Q8 and the output of Q2 is applied
to the C input of Q4. The J and K inputs are connected either to a permanent 1 signal or to outputs
ofother flip‐flops.

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• A ripple counter is an asynchronous sequential circuit. Signals that affect the flip‐flop transition depend
on the way they change from 1 to 0. The operation of the counter can be explained by a list of conditions
for flip‐flop transitions. These conditions are derived from the logic diagram and from knowledge
ofhow a JK flip‐flop operates.

• Remember that when the C input goes from 1 to 0, the flip‐flop is set if J = 1, is cleared if K = 1, is
complemented if J = K = 1, and is left unchanged if J = K = 0.

Fig. 2. 16 BCD counter

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2.6.3 Design of a Mod-6 asynchronous counter using T FFs

• A mod-6 counter has six stable states 000, 001, 010, 011, 100, and 101. When the sixth clock
pulse is applied, the counter temporarily goes to 110 state, but immediately resets to 000 because
of the feedback provided.

• It requires three FFs, because the smallest value of n satisfying the conditionN≤2n is n=3; three
FFs can have 8 possible states, out of which only six are utilized and the remaining two states
110and 111, are invalid. If initially the counter is in 000 state, then after the sixth clock pulse, it
goes to 001, after the second clock pulse, it goes to 010, and so on.

• After sixth clock pulse it goes to 000. For the design, write the truth table with present state outputs
Q3, Q2 and Q1 as the variables, and reset R as the output and obtain an expression for R in terms of
Q3, Q2, and Q1 that decides the feedback into be provided.

• From the truth table, R=Q3Q2. For active-low Reset, R‘ is used. The reset pulse is of very short
duration, of the order of nanoseconds and it is equal to the propagation delay time of the NAND gate
used. The expression for R can also be determined as follows.

• Therefore, R=0 for 000 to 101, R=1 for 110, and R=X=for111 R=Q3Q2Q1‘+Q3Q2Q1=Q3Q2

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2.7 Synchronous Counters

• Synchronous counters are different from ripple counters in that clock pulses are applied to the inputs
of all flip‐flops. A common clock triggers all flip‐flops simultaneously, rather than one at a time in
succession as in a ripple counter.

• The decision whether a flip‐flop is to be complemented is determined from the values of the data
inputs, such as T or J and K at the timeof the clock edge. If T = 0 or J = K = 0, the flip‐flop does
not change state. If T = 1 or J = K = 1,the flip‐flop complements.

2.7.1 Binary Counter

• The design of a synchronous binary counter is so simple that there is no need to go through a sequential
logic design process. In a synchronous binary counter, the flip‐flop in the least significant position
iscomplemented with every pulse.

• A flip-flop in any other position iscomplemented when all the bits in the lower significant positions
are equal to 1. For example, if the present state of a four‐bit counter is A3A2A1A0 = 0011, the next
count is 0100. A0 is always complemented.

• A1 is complemented because the present state of A0 = 1. A2 is complemented because the present

state of A1A0 = 11. However, A3 is not complemented, because the present state of A2A1A0 =
011,which does not give an all‐1’s condition.

• Synchronous binary counters have a regular pattern and can be constructed with complementing flip‐
flops and gates. The regular pattern can be seen from the four‐bit counter depicted in Fig. 16 below.

• The C inputs of all flip‐flops are connected to a common clock. The counter is enabled by Count
Enable. If the enable input is 0, all J and K inputs are equal to 0 and the clock does not change the
stateof the counter.

• The first stage, A0, has its J and K equal to 1 if the counter is enabled. The other J and K inputs are
equal to 1 if all previous least significant stages are equal to 1 and the count is enabled.

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• The chain of AND gates generates the required logic for the J and K inputs in each stage. The counter
can be extended to any number of stages, with each stage having an additional flip‐flop and an
AND gate that gives an output of 1 if all previous flip‐flop outputs are 1.

Fig 2.17 Four Bit Synchrounous Binary Counter

2.7.2 Procedure to design synchronous counters.

1. Identify the number of flip-flops required based on the number of bits of sequence.
2. Draw the state diagram
3. Write the excitation table of the chosen flip-flop.
4. Obtain the excitation table for the complete circuit.
5. simplify the excitation equations using K-map.
6. Draw the logic diagram.

2.7.2.1 Design of two-bit synchronous counter using T flip flop

1. No. of flip-flops is required =2, two-bit counter – sequence is 00, 01, 10 and 11.

2. State diagram

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3. Excitation table of T-flip-flop

States Excitations
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0

4. Excitation table for complete circuit

5. K-map simplification

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6. Logic diagram

2.7.2.2 Design of 4-bit synchronous up counter using T flip flop

1. No. of Flip-flops required=04.
2. State diagram

3. Excitation table of T-flip-flop

States Excitations
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0

4. Excitation table for complete circuit

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5. K-Map Simplification

6. Logic Diagram

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2.1 Sequential Circuits

Objective Questions:

1. A sequential logic circuit [ ]

A) Must contain flip-flops B) may contain flip-flops

C) does not contain flip-flops D) contain latches

2. Which of the following best describes a sequential circuit? [ ]

A) Output depends only on current inputs

B) Output depends on current inputs and previous outputs

C) Does not have memory elements

D) Operates without a clock signal

3. A sequential circuit does not use clock pulses. It is [ ]

A) an asynchronous sequential circuit B) a synchronous sequential circuit

C) a counter D) a shift register

Descriptive questions

S.No Questions BL

1 How are sequential circuits classified? L2

2 Distinguish between combinational and sequential circuits. L2

2.2 Flip-Flops
Objective Questions:

3. A flip-flop can store [ ]

A) one bit of data B) two bits of data
C) tree bits of data D) any number of bits of data
4. The characteristic equation of a J-K flip-flop is___ .

5. The characteristic equation of a D flip-flop is__ .

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6. The transparent flip-flop is [ ]

A) an S-R flip-flop B) a D flip-flop
C) a T flip-flop D) a J-K flip flop

7. What is the main disadvantage of the JK flip-flop? [ ]

A) It cannot toggle B) It has a race around condition
C) It requires more components D) It is not edge-triggered

8. The excitation table for a flip-flop is used to [ ]

A) Determine the output state
B) Define the input conditions for state transitions
C) Simplify logic equations
D) Design combinational circuits

9. The output Qn of a J-K flip-flop is 1. It changes to 0 when a clock pulse is d. Then the inputs Jn and Kn
are respectively [ ]
A) 0 and X B) 1 and X C) X and 1 D) 0 and X

10. The output Qn of a S-R flip-flop is 0.It changes to 1 when a clock pulse is applied. Then the inputs
Sn and Rn are respectively [ ]
A) X and 1 B) 0 and 1 C) X and 0 D) X and 1

11. In the figure shown is A=1 and B=1, the input B is now replaced with a sequence 101010…., the output
X and Y will be

A) Fixed at 0 and 1 respectively B) X=1010…. While Y=0101…

C) X=1010…. and Y=1010…. D) Fixed at 1 and 0 respectively

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Descriptive questions

S.No Questions BL

1 Find the characteristic equation for JK flip-flop. L2

2 What is the function of an RS flip-flop? L2

3 How does a D flip-flop differ from a JK flip-flop? L3

4 What is a flip-flop excitation table, and why is it important? L2

5 What is the purpose of a T flip-flop in digital circuits? L2

2.3, 2.4 Registers and Shift Registers

Objective Questions:
12. A register is primarily used to [ ]
A) Store data temporarily B) Perform arithmetic operations
C) Generate clock signals D) Control input/output devices
13. A universal register [ ]
A) accepts serial input B) accepts parallel input
C) gives serial and parallel D) all of the above
14. Which type of register can shift data in both directions? [ ]
A) Universal Shift Register B) Serial Register
C) Bidirectional Shift Register D) Parallel Register

15. A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip flop as

follows.
The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the
Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D
flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following
is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the
flip-flops are connected to a free-running common clock? Assume that J= K = 1 is the toggle mode
and J = K = 0 is the state-holding mode of the JK flip- flop. Both the flip-flops have non-zero
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propagation delays.

A) 0110110… B)0100100… C) 011101110… D) 011001100…

16. The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0,. The sequence

generated at Q1 upon application of clock signal is [ ]

A) 01110… B)01010…
C) 00110… D) 01100…

17. When the output Y in the circuit below is ‘1’. It implies that data has [ ]

A) Changed from ‘0’ to ‘1’ B) Changed from ‘1’ to ‘0’

B) Changed in either direction D) Not changed

Descriptive questions
S.No Questions BL

1 How do shift registers operate, and what are their L2

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applications?

2 What distinguishes a bidirectional shift register from a L2

universal shift Register

3 Explain the functionality of a Bi directional shift Register L2

with neat diagram.

4 Differentiate Register and Shift Register L2

5 Explain different types of shift registers with neat diagrams L2

2.5, 2.6, 2.7 Counters

18. A 4-bit binary ripple counter uses flip-flops with propagation delay time of 25ns each. The
maximum possible time required for change of state will be [ ]
a. 25ns B) 50ns C) 75ns D) 100ns
19. A mod-2 counter followed by a mod-5 counter is [ ]
a. the same as a mod-5 counter followed by a mod-2 counter
b. a decade counter C) a mod-7 counter D) none of above
20. A sequential circuit with ten states will have [ ]
a. 10 flip-flops B) 5 flop-flops C) 4 flip-flops D) 0 flip-flops
21. The minimum number of flop-flops required for a mod-12 ripple counter is
A) 3 B) 4 C) 6 D) 12

22. A synchronous counter counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number

of J-K flip-flops required to implement this counter is

A) 1 B) 2 C) 4 D) 5

23. Assuming that the all flip-flops are in reset condition initially, the count sequence observed at QA in
the circuit shown is

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A) 0010111…. B) 0001011….
C) 0101111…. D) 0110100….

24. For the circuit shown, the counter state (Q1Q0) follows the sequences

A) 00,01,10,11,00,…… B) 00,01,10,00,01,……
C) 00,01,11,00,01,…… D) 00,10,11,00,10,……

Descriptive questions

S.No Questions BL

1 Design a 3 bit synchronous up/down counter using JK flip- L3

flop

2 Design a mod 7 asynchronous counter using JK flip-flop. L3

3 Design a mod 12 synchronous counter using T flip-flop. L3

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UNIT-III

Basic Structure of Computers

Course objectives:

• To comprehend the different functional units of a computer and their roles in

executing instructions.
• To learn about different bus structures and their significance in computer architecture.
• To learn the methods of performing arithmetic operations on signed and unsigned
numbers.
• To understand and apply techniques for multiplying signed operands.
• To learn the methods for dividing integers
• To understand the representation and operations on floating-point numbers.

Course Outcomes:

Students will be able to

• articulate the roles and interactions of the input unit, output unit, storage unit, ALU,
and control unit.
• understand the data, address, and control buses and their importance in the
functioning of computer systems.
• adept at performing and explaining the arithmetic operations on signed and unsigned
numbers.
• knowledgeable about floating-point number representation and proficient in
performing floating-point arithmetic operations.

Syllabus
3.1 Functional units
3.1.1 Functional units of computer
3.1.2 Input unit
3.1.3 Memory Unit
3.1.4 Arithmetic and Logic Unit
3.1.5 Output unit
3.1.6 Control Unit

3.2 Basic operational concepts

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3.3 Bus structures

3.4 multiprocessors & multi computers

3.5 Von- Neumann Architecture

3.6 Addition and Subtraction of Signed Numbers

3.6.1 Logic Specification

3.6.2 Addition/subtraction logic unit

3.7 Design of Full adders

3.7.1 n bit ripple carry adder

3.7.2 cascade of k n-bit adders

3.8 Multiplication of Positive Numbers

3.8.1 Array Multiplication

3.8.2 Register configuration

3.8.3 Multiplication Example

3.9 Signed-operand Multiplication

3.9.1 Booth Algorithm with example

3.10 Integer Division

3.10.1 Circuit arrangement

3.10.2 Restoring Division with example

3.10.3 Non restoring division

3.11 Floating-Point Numbers and Operations

3.11.1 IEEE format

3.11.2 Special values, Exceptions

3.11.3 Arithmetic operation on floating point numbers

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3.11.4 Implementing Floating Point numbers

3.1 Functional Units

3.1.1 Functional units of computer

• A computer consists of five functionally independent main parts: input, memory,

arithmetic and logic, output, and control units, as shown in Figure. The input unit
accepts coded information from human operators using devices such as keyboards, or
from other computers over digital communication lines.
• The information received is stored in the computer’s memory, either for later use or to
be processed immediately by the arithmetic and logic unit. The processing steps are
specified by a program that is also stored in the memory. Finally, the results are sent
back to the outside world through the output unit. All of these actions are coordinated
by the control unit.

Fig. 3.1 Basic functional units of a computer

• The information handled by a computer is categorized as instructions or data.

• Instructions, or machine instructions, are explicit commands that
✓ Govern the transfer of information within a computer as well as between the
computer and its I/O devices
✓ Specify the arithmetic and logic operations to be performed
• A program is a list of instructions which performs a task. Programs are stored in the
memory. The processor fetches the program instructions from the memory, one after
another, and performs the desired operations. The computer is controlled by the stored
program, except or possible external interruption by an operator or by I/O devices
connected to it.

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• Data are numbers and characters that are used as operands by the instructions. Data are also
stored in the memory.
3.1.2 Input Unit
• Computers accept coded information through input units. The most common input device
is the keyboard. Whenever a key is pressed, the corresponding letter or digit is
automatically translated into its corresponding binary code and transmitted to the processor.
• Many other kinds of input devices for human-computer interaction are available, including
the touchpad, mouse, joystick, and trackball. These are often used as graphic input devices
in conjunction with displays. Microphones can be used to capture audio input which is then
sampled and converted into digital codes for storage and processing.
3.1.3 Memory Unit

• The function of the memory unit is to store programs and data. There are two classes
of storage, called primary and secondary.
• Primary Memory
• Primary memory, also called main memory, is a fast memory that operates at electronic
• speeds. Programs must be stored in this memory while they are being executed. The
memory consists of a large number of semiconductor storage cells, each capable of
storing one bit of information.
• These cells are rarely read or written individually. Instead, they are handled in groups
of fixed size called words. The memory is organized so that one word can be stored or
retrieved in one basic operation. The number of bits in each word is referred to as the
word length of the computer, typically 16, 32, or 64 bits.
• To provide easy access to any word in the memory, a distinct address is associated with
each word location. Addresses are consecutive numbers, starting from 0, that identify
successive locations. A particular word is accessed by specifying its address and issuing
a control command to the memory that starts the storage or retrieval process.
• Cache Memory
• As an adjunct to the main memory, a smaller, faster RAM unit, called a cache, is used
to hold sections of a program that are currently being executed, along with any
associated data.
• The cache is tightly coupled with the processor and is usually contained on the same
integrated circuit chip. The purpose of the cache is to facilitate high instruction
execution rates.
• At the start of program execution, the cache is empty. All program instructions and any

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required data are stored in the main memory. As execution proceeds, instructions are
fetched into the processor chip, and a copy of each is placed in the cache. When the
execution of an instruction requires data located in the main memory, the data are
fetched and copies are also placed in the cache.
• Secondary Storage
• Although primary memory is essential, it tends to be expensive and does not retain
information when power is turned off. Thus additional, less expensive, permanent
secondary storage is used when large amounts of data and many programs have to be
stored, particularly for information that is accessed infrequently.
• Access times for secondary storage are longer than for primary memory. A wide
selection of secondary storage devices is available, including magnetic disks, optical
disks (DVD and CD), and flash memory devices.
3.1.4 Arithmetic and Logic Unit
• Most computer operations are executed in the arithmetic and logic unit (ALU) of the
processor. Any arithmetic or logic operation, such as addition, subtraction, multiplication,
division, or comparison of numbers, is initiated by bringing the required operands into the
processor, where the operation is performed by the ALU. For example, if two numbers
located in the memory are to be added, they are brought into the processor, and the
addition is carried out by the ALU. The sum may then be stored in the memory or retained
in the processor for immediate use.
• When operands are brought into the processor, they are stored in high-speed storage
elements called registers. Each register can store one word of data. Access times to
registers are even shorter than access times to the cache unit on the processor chip.
3.1.5 Output unit
• The output unit is the counterpart of the input unit. Its function is to send processed results
to the outside world.
• A familiar example of such a device is a printer. Most printers employ either
photocopying techniques, as in laser printers, or ink jet streams. Such printers may
generate output at speeds of 20 or more pages per minute. However, printers are
mechanical devices, and as such are quite slow compared to the electronic speed of a
processor.
• Some units, such as graphic displays, provide both an output function, showing text and
graphics, and an input function, through touchscreen capability. The dual role of such
units is the reason for using the single name input/output (I/O) unit in many cases.
3.1.6 Control Unit

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• The memory, arithmetic and logic, and I/O units store and process information and perform
input and output operations. The operation of these units must be coordinated in some way.
This is the responsibility of the control unit.
• The control unit is effectively the nerve center that sends control signals to other units and
senses their states. I/O transfers, consisting of input and output operations, are controlled
by program instructions that identify the devices involved and the information to be
transferred.
• Control circuits are responsible for generating the timing signals that govern the transfers
and determine when a given action is to take place. Data transfers between the processor
and the memory are also managed by the control unit through timing signals.

3.2 Basic operational concepts

• To perform a given task, an appropriate program consisting of a list of instructions is
stored in the memory. Individual instructions are brought from the memory into the
processor, which executes the specified operations. Data to be used as instruction
operands are also stored in the memory. A typical instruction might be
Add LOCA, R0
• This instruction adds the operand at memory location LOCA to the operand in a register
in the processor R0 and places the sum into register R0. The original contents of
location LOCA are preserved, whereas those of register R0 are overwritten.
• This instruction requires the performance of several steps,

1. First the instruction is fetched from the memory into the processor.

2. The operand at LOCA is fetched and added to the contents of R0

3. Finally the resulting sum is stored in the register R0

• The preceding add instruction combines a memory access operation with an ALU
Operations. In some other type of computers, these two types of operations are
performed by separate instructions for performance reasons.
Load LOCA, R1
Add R1 , R0
• Transfers between the memory and the processor are started by sending the address of
the memory location to be accessed to the memory unit and issuing the appropriate
control signals. The data are then transferred to or from the memory.

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• The fig. 3.2 shows how memory & the processor can be connected. In addition to the
ALU & the control circuitry, the processor contains a number of registers used for
several different purposes.

Fig 3.2 Connection between the processor and the main memory
• The Instruction register (IR) holds the instruction that is currently being executed. Its
output is available to the control circuits, which generate the timing signals that control
the various processing elements involved in executing the instruction.
• The Program Counter (PC) is another specialized register. It contains the memory
address of the next instruction to be fetched and executed. During the execution of an
instruction, the contents of the PC are updated to correspond to the address of the next
instruction to be executed. It is customary to say that the PC points to the next
instruction that is to be fetched from the memory.
• In addition to the IR and PC, Figure shows general-purpose registers R0 through Rn−1,
often called processor registers. They serve a variety of functions, including holding
operands that have been loaded from the memory for processing.
• The other two registers which facilitate communication with memory are: -
1. MAR – (Memory Address Register):- It holds the address of the location to be
accessed.
2. MDR – (Memory Data Register):- It contains the data to be written into or read out
of the address location.
Operating steps are

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1. Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first instruction of
the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the
memory.
4. After the time required to access the memory elapses, the address word is read out of
the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to be
decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain the
required operands.
7. An operand in the memory is fetched by sending its address to MAR & Initiating a
read cycle.
8. When the operand has been read from the memory to the MDR, it is transferred from
MDR to the ALU.
9. After one or two such repeated cycles, the ALU can perform the desired operation.
10. If the result of this operation is to be stored in the memory, the result is sent to
MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle is
initiated.
12. The contents of PC are incremented so that PC points to the next instruction that is
to be executed.
• Normal execution of a program may be preempted (temporarily interrupted) if some
devices require urgent servicing, to do this one device raises an Interrupt signal.
• An interrupt is a request signal from an I/O device for service by the processor. The
processor provides the requested service by executing an appropriate interrupt service
routine.
• The Diversion may change the internal stage of the processor its state must be saved in
the memory location before interruption. When the interrupt-routine service is
completed the state of the processor is restored so that the interrupted program may
continue.
3.3 Bus structures
• To achieve a reasonable speed of operation, a computer must be organized so that all
its units can handle one full word of data at a given time.

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• A group of lines that serve as a connecting port for several devices is called a bus. In
addition to the lines that carry the data, the bus must have lines for address and control
purpose.
• The simplest way to interconnect is to use the single bus as shown in fig 3.3

Fig 3.3 Single Bus Structure

• The bus can be used for only one transfer at a time, only two units can actively use the
bus at any given time. Bus control lines are used to arbitrate multiple requests for use
of the bus.
• The main virtue of a single bus structure is its low cost and its flexibility for attaching
peripheral devices. Systems that contain multiple buses achieve more concurrency in
operations by allowing two or more transfers to be carried out at the same time.

3.4 Multiprocessors & Multi computers

• Large computers that contain a number of processor units are called multiprocessor
system. These systems either execute a number of different application tasks in parallel
or execute subtasks of a single large task in parallel.
• All processors usually have access to all memory locations in such systems & hence
they are called shared memory multiprocessor systems. The high performance of these
systems comes with much increased complexity and cost.
• In contrast to multiprocessor systems, it is also possible to use an interconnected group
of complete computers to achieve high total computational power. These computers
normally have access to their own memory units when the tasks they are executing need
to communicate data they do so by exchanging messages over a communication
network. This property distinguishes them from shared memory multiprocessors,
leading to name message-passing multi computer.

3.5 Von- Neumann Architecture

• Von Neumann architecture is a computer design model where the processing,

memory, input, and output components are interlinked through a single central

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system bus. On the other hand, Harvard architecture is a computer architecture

where the storage and handling of data and instructions are distinct, with separate
buses and memory units.

Fig 3.4 Basic Structure of Von Neumann Architecture

• computer and is having three basic units:
• The Central Processing Unit (CPU)
• The Main Memory Unit
• The Input/Output Device

3.6 Addition and Subtraction of Signed Numbers

• The truth table for the sum and carry-out functions for adding equally weighted bits xi
and yi in two numbers X and Y.
• The figure 3.5 also shows logic expressions for these functions, along with an example
of addition of the 4-bit unsigned numbers 7 and 6. Note that each stage of the addition
process must accommodate a carry-in bit. We use ci to represent the carry-in to stage i,
which is the same as the carry-out from stage (i − 1).

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Fig. 3.5 Logic specification for a stage of binary addition

• The logic expression for si can be implemented with a 3-input XOR gate, used as part
of the logic required for a single stage of binary addition. The carry-out function, ci+1,
is implemented with an AND-OR circuit, as shown in figure 3.6

Fig. 3.6 Logic for a single stage

• A cascaded connection of n full-adder blocks can be used to add two n-bit numbers, as
shown in Figure 3.7. Since the carries must propagate, or ripple, through this cascade,
the configuration is called a ripple-carry adder.

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Fig. 3.7 An n-bit ripple-carry adder

3.6.1 Addition/subtraction logic unit

• The n-bit adder in Figure 3.7can be used to add 2’s-complement numbers X and Y,
where the xn−1 and yn−1 bits are the sign bits. The carry-out bit cn is not part of the
answer.
• Overflow occurs when the signs of the two operands are the same, but the sign of the
result is different. Therefore, a circuit to detect overflow can be added to the n-bit adder
by implementing the logic expression

• It can also be shown that overflow occurs when the carry bits cn and cn−1 are different.
Therefore, a simpler circuit for detecting overflow can be obtained by Implementing the
expression cn⊕cn−1 with an XOR gate.
• In order to perform the subtraction operation X−Y on 2’s-complement numbers X And
Y , form the 2’s-complement of Y and addition X. The logic circuit shown in Figure
3.8 can be used to perform either addition or subtraction based on the value applied to
the Add/Sub input control line.
• This line is set to 0 for addition, applying Y unchanged to one of the adder inputs along
with a carry-in signal, c0, of 0.
• When the Add/Sub control line is set to 1, the Y number is1’s-complemented (that is, bit-
complemented) by the XOR gates and c0 is set to 1to complete the2’s-complementation
of Y.
• 2’s-complementing a Negative number is done in exactly the same manner as for a
positive number. An XOR gate can be added to Figure3.8 to detect the overflow condition
cn⊕cn−1.

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Fig. 3.8 Binary addition/subtraction logic circuit.

3.7 Design of Full adders

• The carry-in, c0, into the least-significant-bit (LSB) position provides a convenient
means of adding 1 to a number. For instance, forming the 2’s-complement of a number
involves adding 1 to the 1’s-complement of the number. The carry signals are also
useful for interconnecting k adders to form an adder capable of handling input
numbers that are kn bits long, as shown in Figure 3.9

Fig. 3.9 Cascade of kn-bit adders

3.8 Multiplication of Positive Numbers

• The usual algorithm for multiplying integers by hand is illustrated in Figure 3.10 for
the binary system. The product of two, unsigned, n-digit numbers can be
accommodated in 2n digits, so the product of the two 4-bit numbers in this example
is accommodated in 8 bits, as shown.

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Fig. 3.10 Manual multiplication algorithm

3.8.1 Array Multiplication

• Binary multiplication of unsigned operands can be implemented in a combinational,

two dimensional, logic array, as shown in Figure 3.11 for the 4-bit operand case.
• The main component in each cell is a full adder, FA. The AND gate in each cell
determines whether a multiplicand bit, mj, is added to the incoming partial-product
bit, based on the value of the multiplier bit, qi. Each row i, where 0 ≤ i ≤ 3, adds the
multiplicand (appropriately shifted) to the incoming partial product, PPi, to generate
the outgoing partial product, PP(i + 1), if qi = 1. If qi = 0, PPi is passed vertically
downward unchanged.
• PP0 is all 0s, and PP4 is the desired product. The multiplicand is shifted left one
position per row by the diagonal signal path. We note that the row-by-row addition
done in the array circuit differs from the usual hand addition described previously,
which is done column-by-column.

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Fig. 3.11 Array implementation

3.8.2 Register configuration

• The block diagram in Figure 3.12 shows the hardware arrangement for sequential
multiplication. This circuit performs multiplication by using a single n-bit adder n times
to implement the spatial addition performed by the n rows of ripple-carry adders.
• Registers A and Q are shift registers, concatenated as shown. Together, they hold partial
product PPi while multiplier bit qi generates the signal Add/Noadd. This signal causes
the multiplexer MUX to select 0 when qi = 0, or to select the multiplicand M when qi =
1, to be added to PPi to generate PP(i + 1). The product is computed in n cycles.
• The partial product grows in length by one bit per cycle from the initial vector, PP0, of n
0s in register A. The carry-out from the adder is stored in flip-flop C, shown at the left
end of register A. At the start, the multiplier is loaded into register Q, the multiplicand
into register M, and C and A are cleared to 0. At the end of each cycle, C, A, and Q are
shifted right one bit position to allow for growth of the partial product as the multiplier
is shifted out of register Q. Because of this shifting, multiplier bit qi appears at the LSB
position of Q to generate the Add/Noadd signal at the correct time, starting with q0 during
the first cycle, q1 during the second cycle, and so on.
• After they are used, the multiplier bits are discarded by the right-shift operation. Note
that the carry-out from the adder is the leftmost bit of PP(i + 1), and it must be held in
the C flip-flop to be shifted right with the contents of A and Q. After n cycles, the high-
order half of the product is held in register A and the low-order half is in register Q.

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Fig. 3.12 Register Configuration

3.8.3 Multiplication Example

M=1101 , Q=1011

Product =AQ= 10001111

3.9 Signed-operand Multiplication

• First, consider the case of a positive multiplier and a negative multiplicand. When we
add a negative multiplicand to a partial product, we must extend the sign-bit value of
the multiplicand to the left as far as the product will extend.
• Figure 3.12 shows an example in which a 5-bit signed operand, −13, is the
multiplicand. It is multiplied by +11 to get the 10-bit product, −143.

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Fig. 3.13 Sign extension of Negative Multiplicand

• For a negative multiplier, a straight forward solution is to form the 2’s-complement

of both the multiplier and the multiplicand and proceed as in the case of a positive
multiplier. This is possible because complementation of both operands does not
change the value or the sign of the product.

3.9.1 Booth Algorithm with example

• The Booth algorithm generates a 2n-bit product and treats both positive and
negative2’s complement n-bit operands uniformly.
• To understand the basis of this algorithm, consider a multiplication operation in
which the multiplier is positive and has a single block of 1s, for example, 0011110.
To derive the product, we could add four appropriately shifted versions of the
multiplicand, as in the standard procedure. For convenience, we can describe the
sequence of required operations by recoding the preceding multiplier as 0+1000−10.
• In general, in the Booth algorithm, −1 times the shifted multiplicand is selected when
Moving from 0 to 1, and +1 times the shifted multiplicand is selected when moving
from 1 to 0, as the multiplier is scanned from right to left.
• Figure 3.14 illustrates the normal and the Booth algorithms for a example. The Booth
algorithm clearly extends to any number of blocks of 1s in a multiplier, including
the situation in which a single 1 is considered a block.

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Fig. 3.14 Normal and Booth multiplication schemes

• The following is another example of recoding a multiplier. The case when the least
significant bit of the multiplier is 1 is handled by assuming that an implied 0 lies to
its right.

• The Booth algorithm can also be used directly for negative multipliers, as shown in
Figure 3.15.

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Fig. 3.15 Booth multiplication with a negative multiplier.

• A 16-bit worst-case multiplier, an ordinary multiplier, and a good multiplier are

shown in Figure 3.16

Fig. 3.15 Booth recoded multipliers.

• The Booth algorithm has two attractive features.

➢ First, It handles both positive and negative multipliers uniformly.
➢ Second, it achieves some efficiency in the number of additions required
when the multiplier has a few large blocks of 1s.

3.10 Integer Division

• Figure 3.16 shows examples of decimal division and binary division of the same
values.
• A circuit that implements division by this method operates as follows:

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• It positions the divisor appropriately with respect to the dividend and performs a
subtraction.
• If the remainder is zero or positive, a quotient bit of 1isdetermined, the remainder
is extended by another bit of the dividend, the divisor is repositioned, and another
subtraction is performed.
• If the remainder is negative, a quotient bit of 0 is determined, the dividend is restored
by adding back the divisor, and the divisor is repositioned for another subtraction.
This is called the restoring division algorithm.

Fig. 3.16 Division Examples.

Restoring Division

• Figure 3.17 shows a logic circuit arrangement that implements the restoring
division algorithm.

Fig. 3.16 Circuit arrangement for binary division

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• An n-bit positive divisor is loaded into register M and an n-bit positive dividend is
loaded into register Q at the start of the operation. Register A is set to 0. After the
division is complete, the n-bit quotient is in register Q and the remainder is in register
A.
• The required subtractions are facilitated by using 2’s-complement arithmetic.
• The extra bit position at the left end of both A and M accommodates the sign bit
during subtractions. The following algorithm performs restoring division.
• Do the following three steps n times:
1. Shift A and Q left one bit position.
2. Subtract M from A, and place the answer back in A.
3. If the sign of A is 1, set q0 to 0 and add M back to A(that is, restore A);
otherwise, set q0 to 1.
• Figure 3.17 shows a 4-bit example as it would be processed by the circuit in Figure
3.16.

Fig. 3.17 A restoring division example

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Non restoring Division

• The restoring division algorithm can be improved by avoiding the need for restoring
A after an unsuccessful subtraction. Subtraction is said to be unsuccessful if the
result is negative.
• Consider the sequence of operations that takes place after the subtraction
operation in the preceding algorithm. If A is positive, we shift left and subtract
M, that is, we perform 2A−M.
• If A is negative, we restore it by performing A+ M, and then we shift it left and
subtract M. This is equivalent to performing 2A+ M.
• The q0 bit is appropriately set to 0 or 1 after the correct operation has been
performed. We can summarize this in the following algorithm for non-restoring
division.
• Stage 1: Do the following two steps n times:
1. If the sign of Ais 0, shift A and Q left one bit position and subtract M from
A;
otherwise, shift A and Q left and add M to A.
2. Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
• Stage 2: If the sign of Ais 1, add M to A.
Stage 2 is needed to leave the proper positive remainder in A after the n cycles
of Stage 1.
• The logic circuitry in Figure 3.16 can also be used to perform this algorithm,
except that the Restore operations are no longer needed. One Add or Subtract
operation is performed in each of the n cycles of stage 1, plus a possible final
addition in Stage 2.
• Figure 3.18 shows how the division example in Figure 3.17 is executed by the
non-restoring division algorithm.
• There are no simple algorithms for directly performing division on signed
operands that are comparable to the algorithms for signed multiplication.
• In division, the operands can be pre processed to change them into positive
values. After using one of the algorithms just discussed, the signs of the quotient
and the remainder are adjusted as necessary.

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Fig. 3.18 A Non restoring division example

3.11 Floating-Point Numbers and Operations

• A binary floating-point number can be represented by

▪ A sign for the number
▪ Some significant bits
▪ A signed scale factor exponent for an implied base of 2

3.11.1 IEEE format

• The basic IEEE format is a 32-bit representation, shown in Figure 3.19a.

• The leftmost bit represents the sign, S, for the number.
• The next 8 bits, E, represent the exponent of the scale factor (to the base of 2). Instead
of the signed exponent, E, the value actually stored in the exponent field is an unsigned
integer El=E+127. This is called excess-127 format. Thus El is in the range 0 ≤ El≤ 255.
• The last 23 bits represent the mantissa. Since the binary normalization is used, the most
significant bit of mantissa is always equal to1. This bit is not explicitly represented. It
is assumed to be to the immediate left of the binary point.

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Fig. 3.19 IEEE standard floating-point formats.

• If a number is not normalized, it can be put in normalized form by shifting

the binary point and adjusting the exponent. Figure 3.20 shows an
unnormalized value, 0.0010110...× 29, and its normalized version, 1.0110...×
26.
• Since the scale factor is in the form 2i, shifting the mantissa right or left by
one bit position is compensated by an increase or a decrease of 1 in the
exponent, respectively. Second, as computations proceed, a number that does
not fall in the representable range of normal numbers might be generated.
• In single precision, this means that its normalized representation requires an
exponent less than −126 or greater than +127.
• In the first case, we say that underflow has occurred, and in the second case,
we say that overflow has occurred.

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Fig. 3.20 Floating-point normalization in IEEE single-precision format

3.11.2 Special values, Exceptions

• The end values 0 and 255 of the excess-127 exponent E are used to represent special
values. When E= 0 and the mantissa fraction M is zero, the value 0 is represented.
• When E=255 and M =0, the value ∞ is represented, where ∞ is the result of dividing a
normal number by zero. The sign bit is still used in these representations, so there are
representations for ±0 and ±∞.
• When E=0 and M=0, denormal numbers are represented. Their value is ±0.M × 2−126.
Therefore, they are smaller than the smallest normal number. There is no implied one
to the left of the binary point, and M is any nonzero 23-bit fraction.
• The purpose of introducing denormal numbers is to allow for gradual underflow,
providing an extension of the range of normal representable numbers.
• This is useful in dealing with very small numbers, which may be needed in certain
situations. When E= 255andM= 0, the value represented is called Not a Number (NaN).
A NaN is the result performing an invalid operation such as 0/0 or √−1.
• A processor must set exception flags if any of the following conditions arise when
performing operations: underflow, overflow, divide by zero, inexact, invalid.
• Inexact is the name for a result that requires rounding in order to be represented in one
of the normal formats. An invalid exception occurs if operations such as 0/0 or √−1 are
attempted. When an exception occurs, the result is set to one of the special values.

3.11.3 Arithmetic operation on floating point numbers

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• The general procedures for addition, subtraction, multiplication, and division of

floating-point numbers is given below.
• The rules given below apply to the single-precision IEEE standard format. These rules
specify only the major steps needed to perform the four operations; for example, the
possibility that overflow or underflow might occur is not discussed.
• When adding or subtracting floating-point numbers, their mantissas must be shifted
with respect to each other if their exponents differ. Consider a decimal example in
which we wish to add 2.9400 ×102 to 4.3100 ×104. We rewrite 2.9400 × 102 as 0.0294
× 104 and then perform addition of the mantissas to get 4.3394 × 104. The rule for
addition and subtraction can be stated as follows:
• Add/Subtract Rule
1. Choose the number with the smaller exponent and shift its mantissa right a
number of steps equal to the difference in exponents.
2. Set the exponent of the result equal to the larger exponent.
3. Perform addition/subtraction on the mantissas and determine the sign of the result.
4. Normalize the resulting value, if necessary.
• Multiplication and division are somewhat easier than addition and subtraction, in that
no alignment of mantissas is needed.
• Multiply Rule
1. Add the exponents and subtract 127 to maintain the excess-127 representation.
2. Multiply the mantissas and determine the sign of the result.
3. Normalize the resulting value, if necessary
• Divide Rule
1. Subtract the exponents and add 127 to maintain the excess-127 representation.
2. Divide the mantissas and determine the sign of the result.
3. Normalize the resulting value, if necessary.

3.11.4 Implementing Floating point numbers

• The hardware implementation of floating-point operations involves a considerable

amount of logic circuitry.
• An example of the implementation of floating-point operations is shown in Figure3.21.
• This is a block diagram of a hardware implementation for the addition and subtraction
of 32-bit floating-point operands.

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• The first step is to compare exponents to determine how far to shift the mantissa of the
number with the smaller exponent.
• The shift-count value, n, is determined by the 8-bit subtractor circuit in the upper left
corner of the figure. The magnitude of the difference E1A – E1B, or n, is sent to the
SHIFTER unit.
• If n is larger than the number of significant bits of the operands, then the answer is
essentially the larger operand (except for guard and sticky-bit considerations in
rounding), and shortcuts can be taken in deriving the result.

Fig. 3.21 Floating-point addition-subtraction unit.

• The sign of the difference that results from comparing exponents determines which
mantissa is to be shifted. Therefore, in step 1, the sign is sent to the SWAP network in
the upper right corner of Figure 3.21.
• If the sign is 0, then ElA ≥ ElB and the mantissas MA and MB are sent straight through
the SWAP network. This results in MB being sent to the SHIFTER, to be shifted n

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positions to the right. The other mantissa, MA, is sent directly to the mantissa
adder/subtractor. If the sign is 1, then ElA < ElB and the mantissas are swapped
before they are sent to the SHIFTER.
• Step 2 is performed by the two-way multiplexer, MUX, near the bottom left corner of
the figure. The exponent of the result, El, is tentatively determined as ElA if ElA ≥ ElB,
or ElB if ElA < ElB, based on the sign of the difference resulting from comparing
exponents in step 1.
• Step 3 involves the major component, the mantissa adder/subtractor in the middle of
the figure. The CONTROL logic determines whether the mantissas are to be added or
• subtracted. This is decided by the signs of the operands (SA and SB) and the operation
(Add or Subtract) that is to be performed on the operands. The CONTROL logic also
determines the sign of the result, SR.
• For example, if A is negative (SA = 1), B is positive (SB = 0), and the operation is A −
B, then the mantissas are added and the sign of the result is negative (SR = 1).
• On the other hand, if A and B are both positive and the operation is A − B, then the
Mantissas are subtracted. The sign of the result, SR, now depends on the mantissa
subtraction operation. For instance, if EA > EB, then M = MA − (shifted MB) and the
resulting number is positive. But if EB > EA, then M = MB −(shifted MA) and the result
is negative.
• This example shows that the sign from the exponent comparison is also required as an
input to the CONTROL network. When EA = EB and the mantissas are subtracted, the
sign of the mantissa adder/subtractor output determines the sign of the result.
• Step 4 of the Add/Subtract rule consists of normalizing the result of step 3 by shifting
M to the right or to the left, as appropriate.
• The number of leading zeros in M determines the number of bit shifts, X, to be applied
to M. The normalized value is rounded to generate the 24-bit mantissa, MR, of the
result. The value X is also subtracted from the tentative result exponent E to generate
the true result exponent, ER. Note that only a single right shift might be needed to
normalize the result.

3.1. Functional Units of Computers

Objective Questions:

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1. What is the primary function of the Arithmetic and Logic Unit (ALU)? [ ]
a) Control data flow b) Perform arithmetic and logical operations
c) Store data d) Manage input and output devices
2. Which of the following is NOT a functional unit of a computer? [ ]
a) Input Unit b) Output Unit
c) Control Unit d) Network Unit
3. Which unit is responsible for coordinating the operations of the other functional units in a
computer? [ ]
a) Input Unit b) Output Unit
c) Control Unit d) Memory Unit
4. What type of information is primarily stored in the memory unit of a computer? [ ]
a) Only instructions b) Both instructions and data
c) Only data d) Only control signals

Descriptive questions
S.No Questions BL

1 Define the term "bus" in the context of computer architecture L1

2 Explain the role of the input unit in a computer system L2

3 Describe about functional units of computer with neat diagram L2

3.2 Basic operational concepts

Objective Questions

1. What is the purpose of the Program Counter (PC) in a processor? [ ]

a) To hold the current instruction being executed

b) To point to the next instruction to be fetched and executed

c) To store operands from memory

d) To hold the address of the memory location to be accessed

2. Which register holds the instruction that is currently being executed? [ ]

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a) Memory Address Register (MAR) b) Memory Data Register (MDR)

c) Instruction Register (IR) d) Program Counter (PC)

3. In the instruction Add LOCA, R0, what happens to the original contents of the memory

location LOCA? [ ]

a) They are overwritten b) They are moved to another location

c) They are preserved d) They are deleted

4. Which of the following is the correct sequence of steps for fetching an operand from

memory during instruction execution? [ ]

a) MAR -> MDR -> IR b) PC -> MAR -> MDR -> IR

c) MAR -> ALU -> MDR d) PC -> MAR -> ALU -> MDR

5. What is the purpose of the Memory Data Register (MDR)? [ ]

a) To hold the memory address to be accessed

b) To hold data to be written into or read from the memory

c) To execute arithmetic operations

d) To point to the next instruction

Descriptive questions
S.No Questions BL

1 Explain the sequence of steps involved in executing the L2

instruction Add LOCA, R0.
2 Describe the role of the Program Counter (PC) and how it L2
interacts with other components during program execution.
3 Compare and contrast the operations of Add LOCA, R0 with L3
the sequence of Load LOCA, R1 and Add R1, R0.

3.3 Bus structures

Objective Questions

1. What is the primary advantage of using a single bus structure in a computer system? [ ]

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a) High speed b) Low cost and flexibility

c) Ability to perform multiple transfers simultaneously d) Increased security

2. In a single bus structure, how many units can actively use the bus at any given time? [ ]

a) One b) Two c) Three d) Four

3. What is the primary function of a bus in a computer system? [ ]

a) To increase the processing speed of the CPU

b) To connect and transfer data between various components of the computer

c) To manage the power supply to peripheral devices

d) To store frequently used instructions and data

4. What is the role of bus control lines in a single bus structure? [ ]

a) To increase the data transfer rate

b) To control the power supply to devices

c) To arbitrate and manage multiple requests for bus access

d) To store data temporarily

5. Why might a computer system with multiple buses be preferred over a single bus system?

a) It is less expensive [ ]

b) It allows for more concurrent operations, improving performance

c) It reduces the number of peripheral devices that can be connected

d) It simplifies the computer’s architecture

Descriptive questions
S.No Questions BL

1 Explain the purpose and function of a bus in computer L2

architecture.
2 Describe the advantages and disadvantages of a single bus L2
structure.

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3 How do bus control lines manage data transfers in a single bus L2

structure?

3.4 Multiprocessors & multi computers

Objective Questions

1. What defines a multiprocessor system? [ ]

a) A single processor executing multiple tasks

b) Multiple processors sharing access to a common memory

c) Multiple independent computers connected by a network

d) A single computer with multiple memory units.

2. What is the primary characteristic that differentiates a multiprocessor system from a multi-

computer system? [ ]

a) Multiprocessors use message-passing for communication.

b) Multi-computers have shared memory access.

c) Multiprocessors share a common memory, while multi-computers communicate via

message-passing over a network.

d) Multi-computers can execute tasks in parallel

Descriptive questions
S.No Questions BL

1 Explain the key differences between a multiprocessor system L2

and a multi-computer system.

3.5 Von- Neumann Architecture

Objective Questions

1. What is the key characteristic of the Von Neumann architecture? [ ]

a) Separate buses and memory units for data and instructions

b) A single bus for both data and instructions

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c) Separate processing units for each task

d) Multiple CPUs sharing the same memory

Descriptive questions
S.No Questions BL

1 Describe the key components of the Von Neumann L2

architecture and their roles.
2 Explain the differences between Von Neumann and Harvard L2
architectures.

3.6 Addition and Subtraction of Signed Numbers

Objective Questions

1. What is the primary function of the ripple-carry adder? [ ]

a) To subtract two n-bit numbers b) To multiply two n-bit numbers

c) To add two n-bit numbers d) To detect overflow in binary addition

2. What is the primary function of the ripple-carry adder? [ ]

a) To subtract two n-bit numbers b) To multiply two n-bit numbers

c) To add two n-bit numbers d) To detect overflow in binary addition

3. Which of the following is used to detect overflow in an n-bit adder? [ ]

a) AND gate b) OR gate c) XOR gate d) NOR gate

Descriptive questions
S.No Questions BL

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1 Explain how a ripple-carry adder works and describe its L2

primary disadvantage.
2 Describe how overflow is detected in an n-bit adder and L2
explain the significance of the XOR gate in this process.
3 How does the binary addition/subtraction logic circuit perform L2
subtraction using 2’s-complement numbers?

3.8 Multiplication of Positive Numbers

Objective Questions

1. What is the size of the product when multiplying two unsigned 4-bit numbers? [ ]

a) 4 bits b) 8 bits c) 12 bits d) 16 bits

2. During the multiplication process in the register configuration, what happens to the

multiplier bits in register Q? [ ]

a) They are shifted left and added to the multiplicand.

b) They are shifted right and discarded after use.

c) They are shifted right and added to the multiplicand.

d) They remain unchanged.

Descriptive questions
S.No Questions BL

1 Explain the process of binary multiplication using the array L2

multiplication method.
2 Describe the operation of the register configuration for L2
sequential multiplication. How is the final product obtained
after n cycles?
3 Given the multiplicand M=1101 and multiplier Q=1011 L3
explain the step-by-step process of obtaining the product using
the register configuration method.

3.9 Signed-operand Multiplication

Objective Questions

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1. When multiplying a positive multiplier with a negative multiplicand, what must be done to

the sign bit of the multiplicand? [ ]

a) Ignore it b) Extend it to the left as far as the product extends

c) Set it to 0 d) Set it to 1

2. Which feature of the Booth algorithm makes it efficient for multipliers with large blocks of

1s? [ ]

a) It handles positive multipliers only

b) It minimizes the number of additions required

c) It extends the product width

d) It uses unsigned operands only

3. How does the Booth algorithm treat negative multipliers? [ ]

a) It requires a separate process

b) It converts them to positive using 2’s complement and then proceeds

c) It ignores the negative sign

d) It uses sign extension

4. What is the advantage of the Booth algorithm over the normal multiplication method?

a) It only works for positive numbers [ ]

b) It requires more additions

c) It handles both positive and negative numbers uniformly and efficiently reduces the
number of additions

d) It only works for 16-bit multipliers

Descriptive questions
S.No Questions BL

1 Describe the Booth algorithm and explain how it simplifies the L3

multiplication process for both positive and negative
multipliers. Include an example to illustrate the steps involved.

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2 Provide a detailed explanation of how the Booth algorithm L2

handles negative multipliers and describe its advantages over
the standard multiplication method.

3.10 Integer Division

Objective Questions

1. What is the main difference between the restoring and non-restoring division
algorithms? [ ]

a) Restoring division uses extra hardware, while non-restoring does not

b) Non-restoring division avoids restoring the remainder after an unsuccessful

subtraction

c) Restoring division handles negative numbers better than non-restoring

d) Non-restoring division requires more iterations than restoring division

Descriptive questions
S.No Questions BL

Explain the restoring division algorithm and provide a step-by- L3

step description of how it operates using a 4-bit example.
Describe the non-restoring division algorithm and compare it L3
with the restoring division algorithm. Use an example to
illustrate the steps of the non-restoring division algorithm.

3.11 Floating-Point Numbers and Operations

Objective Questions

1. In the IEEE 32-bit floating-point format, what does the 8-bit exponent field represent?

a) The actual exponent value [ ]

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b) A signed scale factor for the mantissa

c) The exponent plus 127 (excess-127 format)

d) The base of the exponent

2. What happens when the exponent in a floating-point number exceeds +127? [ ]

a) Overflow occurs b) Underflow occurs

c) The number is normalized d) The exponent is wrapped around

3. Which of the following represents a special value in the IEEE 32-bit floating-point format

when the exponent is 255 and the mantissa is zero? [ ]

a) Zero b) Infinity

c) NaN (Not a Number) d) Denormalized number

4. What is the result of an invalid operation such as dividing by zero in floating-point

arithmetic? [ ]

a) NaN (Not a Number) b) Infinity

c) Zero d) Underflow

Descriptive questions
S.No Questions BL

1 Explain the IEEE 32-bit floating-point format. How are the L2

sign, exponent, and mantissa represented?
2 Represent -6.25 in IEEE 32-bit floating-point format L3

3 What are the special values represented in the IEEE floating- L2

point standard, and how are they used?

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UNIT -IV
PROCESSOR AND MEMORY ORGANIZATION
Course Objective:
• To familiarize the concept of Processor Organization and memory Organization.
Syllabus:
Processor Organization: Fundamental Concepts, Execution of a Complete Instruction, Multiple-
Bus Organization, Hardwired Control and Micro programmed Control
Memory Organization: Basic Concepts, Semiconductor RAM Memories, Read-Only Memories,
Speed, Size and Cost, Speed, Size and Cost, Cache Memories, Secondary Storage.

Course Outcomes:
At the end of the unit, student will be able to:
• How a processor executes instructions.

• The internal functional units of a processor and how they are interconnected.

• Hardware for generating internal control signals.

• Organization of a main memory

• Significance of virtual memory and cache memory.

• Magnetic and optical disks used for secondary storage.

Syllabus

4.1 Fundamental Concepts

4.1.1 Single Bus organization of Processor
4.1.2 Register Transfers
4.1.3 Performing an Arithmetic or Logic Operation
4.1.4 Fetching a Word from Memory
4.1.5 Storing a word in Memory

4.2 Execution of a Complete Instruction

4.2.1 Executing an Instruction

4.2.2 Branch Instruction

4.3 Multiple-Bus Organization

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4.4 Hardwired Control and Micro programmed Control

4.4.1 Hardwired Control

4.4.2 Micro programmed Control

4.5 Basic Concepts

4.5.1 Cache and Virtual Memory

4.6 Semiconductor RAM Memories

4.6.1 Internal Organization of Memory Chips
4.6.2 Static Memories
4.6.3 Asynchoronous Dynamic RAMs
4.6.4 Synchronous DRAMs

4.7 Read-Only Memories

4.7.1 PROM
4.7.2 EPROM
4.7.3 EEPROM
4.7.4 Flash Memory
4.8 Speed, Size and Cost

4.9 Cache Memories

4.9.1 Mapping Functions
4.9.2 Replacement Algorithms

4.10 Performance Considerations

4.10.1. Interleaving

4.10.2 Hit Rate and Miss Penalty

4.11 Virtual Memories

4.11.1 Virtual Memory Organization

4.11.2 Address Translation

4.11.3 Translation Lookaside Buffer

4.11.4 Page Faults

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4.12 Memory Management Requirements

4.13 Secondary Storage

4.13.1 Magnetic Hard Disks

4.13.2 Optical Disks

4.13.3 Magentic tape System

PROCESSOR ORGANIZATION
4.1 Basic Processing Unit-Some Fundamental Concepts

• To execute a program, the processor fetches one instruction at a time and performs the
operations specified. Instructions are fetched from successive memory locations until a
branch or a jump instruction is encountered.

• The processor keeps track of the address of the memory location containing the next
instruction to be fetched using the program counter, PC. After fetching an instruction, the
contents of the PC are updated to point to the next instruction in the sequence. A branch
instruction may load a different value into the PC. Another key register in the processor is
the instruction register, IR.

• Suppose that each instruction comprises 4 bytes, and that it is stored in one memory word.
To execute an instruction, the processor has to perform the following three steps:

1. Fetch the contents of the memory location pointed to by the PC. The contents of this
location are the instruction to be executed; hence they are loaded into the IR. In register
transfer notation, the required action is
IR←[[PC]]

2. Increment the PC to point to the next instruction. Assuming that the memory is byte
addressable, the PC is incremented by 4; that is
PC←[PC]+4
3. Carryout the operation specified by the instruction in the IR.

Fetching an instruction and loading it into the IR is usually referred to as the instruction
fetch phase. Performing the operation specified in the instruction constitutes the instruction

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execution phase.

4.1.1 Single Bus organization of Processor:

• Figure 4.1 shows the organization in which the arithmetic and logic unit (ALU) and all the
registers are interconnected via a single common bus. This bus is internal to the processor and
should not be confused with the external bus that connects the processor to the memory and
I/O devices.

• The data and address lines of the external memory bus are connected to the internal processor
bus via the memory data register, MDR, and the memory address register, MAR, respectively.
Register MDR has two inputs and two outputs. Data may be loaded into MDR either from the
memory bus or from the internal processor bus.

• The data stored in MDR may be placed on either bus. The input of MAR is connected to the
internal bus, and its output is connected to the external bus. The control lines of the memory
bus are connected to the instruction decoder and control logic block.

Figure 4.1: Single Bus Organization

• Three registers Y, Z, and TEMP registers are used by the processor for temporary storage
during execution of some instructions. The multiplexer MUX selects either the output of
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register Y or a constant value 4 to be provided as input A of the ALU. The constant 4 is used
to increment the contents of the program counter.

• With few exceptions, an instruction can be executed by performing one or more of the
following operations in some specified sequence:

➢ Transfer a word of data from one processor register to another or to the ALU
➢ Perform an arithmetic or a logic operation and store the result in a processor register
➢ Fetch the contents of a given memory location and load them into a processor register
➢ Store a word of data from a processor register into a given memory location

4.1.2 Register Transfers

• Instruction execution involves a sequence of steps in which data are transferred from one
register to another. For each register, two control signals are used to place the contents of that
register on the bus or to load the data on the bus into the register.

• The input and output of register Ri are connected to the bus via switches controlled by the
signals Riin and Riout, respectively. When Riin is set to 1, the data on the bus are loaded into
Ri. Similarly, when Riout, is set to 1, the contents of register Ri are placed on the bus. While
Riout is equal to 0, the bus can be used for transferring data from other registers.

Figure 4.2: Register transfer

• Suppose that we wish to transfer the contents of register R1 to register R4. This can be
accomplished as follows:
o Enable the output of register R1 by setting R1out to 1. This places the contents of R1
on the

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processor bus.
o Enable the input of register R4 by setting R4in,to1. This loads data from the processor
bus into register R4.

All operations and data transfers within the processor take place within time periods defined by the
processor clock.

4.1.3 Performing an Arithmetic or Logic Operation

• The ALU is a combinational circuit that has no internal storage. It performs arithmetic and
logic operations on the two operands applied to its A and B inputs In figures 4.1 and 4.3, one
of the operands is the output of the multiplexer MUX and the other operand is obtained
directly from the bus. The result produced by the ALU is stored temporarily in register Z.

• Therefore, a sequence of operations to add the contents of register R1 to those of register R2

and store the result in register R3 is

1. R1out,Yin
2. R2out,SelectY, Add, Zin
3. ZoutR3in

Step 1: The output of register R1 and the input of register Y are enabled, causing the contents of R1
to be transferred over the bus to Y.

Step 2: The multiplexer's Select signal is set to Select Y, causing the multiplexer to gate the contents
of register Y to input A of the ALU. At the same time, the contents of register R2 are gated onto the
bus and, hence, to input B. The function performed by the ALU depends on the signals applied to its
control lines. In this case, the Add line is set to 1, causing the output of the ALU to be the sum of the
two numbers at inputs A and B. This sum is loaded into register Z because its input control signal is
activated.

Step 3: The contents of register Z are transferred to the destination register, R3. This last transfer
cannot be carried out during step 2, because only one register output can be connected to the bus
during any clock cycle.

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Figure 4.3: Input and Output gating for the registers

4.1.4 Fetching a Word from Memory

• To fetch a word of information from memory, the processor has to specify the address of the
memory location where this information is stored and request a Read operation. The
connections for register MDR are illustrated in Figure 4.4.

• It has four control signals: MDRin and MDRout, control the connection to the internal bus, and
MDRinE and MDRoutE control the connection to the external bus.

Figure 4.4: Connection and control signals for register MDR

• As an example of a read operation, consider the instruction Move (R1), R2. The actions

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needed to execute this instruction are:

1. MAR[RI]
2. Start a Read operation on the memory bus
3. Wait for the MFC(Memory Function Completed) response from the memory
4. Load MDR from the memory bus
5. R2 [MDR]

• These actions may be carried out as separate steps, but some can be combined into a single
step. Each action can be completed in one clock cycle, except action 3 which requires one or
more clock cycles, depending on the speed of the addressed device.

• The memory read operation requires three steps, which can be described by the signals being
activated as follows:

1. Rlout,MARin, Read
2. MDRinE, WMFC
3. MDRout,R2in

where WMFC is the control signal that causes the processor's control circuitry to wait for the arrival
of the MFC signal.

4.1.5 Storing a word in Memory

• Writing a word into a memory location follows a similar procedure. The desired address is
loaded into MAR. Then, the data to be written are loaded into MDR, and a Write command is
issued. Hence, executing the instruction Move R2,(R1) requires the following sequence:

1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC

• As in the case of the read operation, the Write control signal causes the memory bus interface
hardware to issue a Write command on the memory bus. The processor remains in step 3 until
the memory operation is completed and an MFC response is received.

4.2 Execution of a complete instruction

4.2.1 Executing an Instruction

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• Consider the instruction Add(R3),R1which adds the contents of a memory location pointed to
by R3 to register R1.

• Executing this instruction requires the following actions:

1. Fetch the instruction.

2. Fetch the first operand (the contents of the memory location pointed to byR3).
3. Perform the addition.
4. Load the result into RI.
5. Instruction execution proceeds as follows.

Step 1: The instruction fetch operation is initiated by loading the contents of the PC into the
MAR and sending a Read request to the memory. The Select signal is set to Select4, which causes
the multiplexer MUX to select the constant 4. This value is added to the operand at input B, which
is the contents of the PC, and the result is stored in register Z.

Step 2: The updated value is moved from register Z back into the PC, while waiting for the memory
to respond.

Step 3: The word fetched from the memory is loaded into the IR.(Steps 1 through 3 constitute the
instruction fetch phase, which is the same for all instructions.)

Figure 4.5: Control Sequence for Execution of the instruction Add (R3), R1

Step 4: The instruction decoding circuit interprets the contents of the IR. This enables the control
circuitry to activate the control signals for steps 4 through 7, which constitute the execution phase.

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The contents of register R3 are transferred to the MAR in step4,and a memory read operation is
initiated.

Step 5: the contents of R1 are transferred to register Y, to prepare for the addition operation.

Step 6: When the Read operation is completed, the memory operand is available in register MDR,
and the addition operation is performed. The contents of MDR are gated to the bus, and thus also to
the B input of the ALU, and register Y is selected as the second input to the ALU by choosing
Select Y.

Step 7: The sum is stored in register Z, and then transferred to R1. The End signal causes a new
instruction fetch cycle to begin by returning to step 1.

• This discussion accounts for all control signals, except Y in step2. There is no need to copy the
updated contents of PC into register Y when executing the Add instruction.

• But, in Branch instructions the updated value of the PC is needed to compute the Branch target
address.

• To speed up the execution of Branch instructions, this value is copied into register Y in step 2.
Since step 2 is part of the fetch phase, the same action will be performed for all instructions.
This does not cause any harm because register Y is not used for any other purpose at that time.

4.2.2 Branch Instruction

• A branch instruction replaces the contents of the PC with the branch target address. This
address is usually obtained by adding an offset X, which is given in the branch instruction, to
the updated value of the PC. Figure gives a control sequence that implements an
unconditional branch instruction. Processing starts, as usual, with the fetch phase. This phase
ends when the instruction is loaded into the IR in step 3.

• The offset value is extracted from the IR by the instruction decoding circuit, which will also
perform sign extension if required. Since the value of the updated PC is already available in
register Y, the offset X is gated onto the bus in step 4, and an addition operation is performed.
The result, which is the branch target address, is loaded into the PC in step 5.

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• The offset X used in a branch instruction is usually the difference between the branch target
address and the address immediately following the branch instruction.

Figure 4.6: Control Sequence of Unconditional Branch

• For example: if the branch instruction is at location 2000 and if the branch target address is
2050, the value of X must be 46. The PC is incremented during the fetch phase before
knowing the type of the instruction being executed. Thus, when the branch address is
computed in step 4, the PC value uses the updated value, which points to the instruction
following the branch instruction in the memory.

4.3 Multiple Bus Organization

• We used the simple single-bus structure to illustrate the basic ideas. The resulting control
sequences are quite long because only one data item can be transferred over the bus in a
clock cycle.

• To reduce the number of steps needed, most commercial processors provide multiple
internal paths that enable several transfers to take place in parallel. Figure 4.7 depicts a
three-bus structure used to connect the registers and the ALU of a processor.

• The register file is said to have three ports. There are two outputs, allowing the contents of
two different registers to be accessed simultaneously and have their contents placed on buses
A and B. The third port allows the data on bus C to be loaded into a third register during the
same clock cycle.

• Buses A and B are used to transfer the source operands to the A and B inputs of the ALU,
where an arithmetic or logic operation may be performed. The result is transferred to the
destination over bus C. If needed, the ALU may simply pass one of its two input operands
unmodified to bus C. We will call the ALU control signals for such an operation R=A or

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R=B. The three-bus arrangement obviates the need for registers Y and Z.

• A second feature in Figure 4.7 is the introduction of the Incrementer unit, which is used to
increment the PC by 4. Using the Incrementer eliminates the need to add 4 to the PC using
the main ALU. The source for the constant 4 at the ALU input multiplexer is still useful. It
can be used to increment other addresses, such as the memory addresses in Load Multiple
and Store Multiple instructions.

Figure 4.7: Three Bus organization of the datapath

• Consider the three-operand instruction

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Add R4, R5, R6

The control sequence for executing this instruction is given as below

Figure 4.8: Control Sequence for the instruction Add R4, R5, R6

Step 1: the contents of the PC are passed through the ALU, using the R=B control signal, and
loaded into the MAR to start a memory read operation. At the same time the PC is incremented by
4. Note that the value loaded into MAR is the original contents of the PC. The incremented value is
loaded into the PC at the end of the clock cycle and will not affect the contents of MAR.
Step2: the processor waits for MFC and loads the data received into MDR.
.Step 3: Transfers the data received in MDR to IR.
Step4: The execution phase of the instruction requires only one control step to complete.

By providing more paths for data transfer a significant reduction in the number of clock cycles
needed to execute an instruction is achieved.

4.4 Hardwired Control and Micro programmed Control

4.4.1 Hardwired Control

• To execute instructions, the processor must generate the control signals in proper sequence.

• There are two basic approaches: hardwired control and microprogrammed control.

• Consider the sequence of control signals given in Figure 4.5. Each step in this sequence is
completed in one clock period. A counter may be used to keep track of the control steps, as
shown in Figure 4.9. Each state or count of this counter corresponds to one control step.

• The required control signals are determined by the following information:

• Contents of the control step counter

• Contents of the instruction register

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• Contents of condition code flags

• External input signals, such as MFC interrupt requests

• The decoder/encoder block in Figure 4.9 is a combinational circuit that generates the required
control outputs depending on the state of all its inputs.

• By separating the decoding and encoding functions, we obtain more detailed diagram shown
in Figure 4.10. The step decoder provides a separate signal line for each step, or time slot, in
the control sequence.

• Similarly the output of the instruction decoder consists of a separate line for each machine
instruction.

Figure 4.9 Control Unit Organization

• For any instruction loaded in the IR, one of the output lines INS1 through INSm is set to 1, and
all other lines are set to 0.

• The input signals to the encoder block are combined to generate the individual control signals
Yin, PCout, Add, End and so on.

• An example of how encoder generates the Zin control signal for the processor organization in
Fig 4.1 is given in Fig 4.11. This circuit implements the logic function

Zin = T1 + T6 . ADD + T4 . BR + ……

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Figure 4.10 Separation of the decoding and encoding functions

• This signal is asserted during time slot T1 for all instructions, during T6 for an ADD
instruction, during T4 for an unconditional branch instruction, and so on.

Fig 4.11 Generation of the Zin control signal for the processor

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• The logic function for Zin is derived from the control sequences in Figures 4.5 and 4.6.

• As another example Fig 4.12 gives a circuit that generates the END control signal from the
logic function
̅ ) . BRN + ……
END= T7 . ADD + T5 . BR + ( T5.N + T4. 𝑁

• The END signal starts a new instruction cycle by resetting the control step counter to its
starting value.

• Figure 4.10 contains another control signal called RUN. When set to 1, RUN causes the
counter to be incremented by one at the end of every clock cycle. When RUN is 0, the counter
stops counting. This is needed whenever the WMFC signal is issued, to cause the processoe to
wait for the reply from the memory.

Fig 4.12 Generation of END Control Signal.

4.4.2 Micro programmed Control

• In micro programmed control, control signals are generated by a program similar to machine
language programs.

• Some common terms are:

• Control Word (CW): It is a word whose individual bits represent various control signals in Fig

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4.10. Each of the control steps in the control sequence of an instruction defines a unique
combination of 1s and 0s in the CW.

• The CWs corresponding to the 7 steps of Figure 4.5 are shown in Figure 4.13. We have
assumed that SelectY is represented by Select=0 and Select4 by select=1.

• A sequence of CWS corresponding to the control sequence of a machine instruction

constitutes the Microroutine for that instruction and the individual control words in this
microroutine are referred to as microinstructions.

Fig 4.13: An example of microinstructions for Fig 4.5

• The Micro routines for all instructions in the instruction set of a computer are stored in a
special memory called the control store. The control unit can generate the control signals for
any instruction by sequentially reading the CWs of the corresponding micro routine from the
control store.

• To read the control words sequentially from the control store, a micro program counter (µPC)
is used. Every time a new instruction is loaded into the IR, the output of the block labeled
“starting address generator” is loaded in to the µPC. The µPC is then automatically
incremented by clock, causing successive micro instructions to be read from the control store.
Hence, the control signals are delivered to various parts of the processor in the correct
sequence.

• One important function of the control unit can not be implemented by the simple organization
in Fig 4.14. This is the situation that arises when the control unit is required to check the

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status of the condition codes or the external inputs to choose between alternative courses of
action.

• In the case of hardwired control, this situation is handled by including an appropriate logic
function in the encoder circuitry. In Microprogrammed control, an alternative approach is to
use conditional branch instructions. In addition to branch address, these micro instructions
specify which of the external inputs, condition codes, or possibly, bits of the instruction
register should be checked as a condition for branching to take place.

Fig 4.14 Basic organization of a micro programmed control

• The instruction Branch < 0 will implemented by a micro routine shown in Figure 4.15.

Fig 4.15 Micro Routine for the instruction Branch < 0

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• After loading this instruction to IR, a branch instruction, transfers control to the
corresponding micro routine, which is assumed to start at location 25 in the control store. This
address is the output of the starting address generator block in Figure 4.14.

• The micro instruction at location 25 tests the N bit of the condition codes. If this bit is equal
to 0 to fetch new machine instruction. Otherwise, the micro instruction at location 26 is
executed to put the branch target address into register Z. The micro instruction in location 27
loads this address into PC.

Fig 4.16 Organization of the control unit to allow conditional branching in the microprogram.

• To support micro program branching, the organization of the control unit should be modified
shown in Figure 4.16.

• The starting address generator block of Figure 4.14 becomes the starting and branch address
generator. This block loads a new into the µPC when a microinstruction instructs it to do so.

• To allow implementation a conditional branch, inputs to this block consist of the external
inputs and a codes as well as the contents of the instruction register.

• In this control unit, the µPC is incremented every time a new microinstruction is fetched from
the microg memory, except in the following situations:

1. When a new instruction is loaded into the IR, the µPC is loaded with the address of the

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micro routine for that instruction.

2. When a Branch microinstruction is encountered and the branch condition is satisfied, the
µPC is loaded with the branch address.

3. When an End microinstruction is encountered, the µPC is loaded with the a of the first CW
in the micro routine for the instruction fetch cycle (this address is 0 in Figure 4.15).

Memory Organization

4.5 Basic Concepts

• The maximum size of the memory that can be used in any computer is determined by the
addressing scheme. For example, a computer that generates 16-bit addresses is capable of
addressing up to 216 = 64K (kilo) memory locations. Machines whose instructions generate
32-bit addresses can utilize a memory that contains up to 232 = 4G (giga) locations, whereas
machines with 64-bit addresses can access up to 264 = 16E (exa) ≈ 16 × 1018 locations. The
number of locations represents the size of the address space of the computer.
• The memory is usually designed to store and retrieve data in word-length quantities. The
connection between the processor and its memory consists of address, data, and control lines,
as shown in Figure 4.17.
• The processor uses the address lines to specify the memory location involved in a data
transfer operation, and uses the data lines to transfer the data. At the same time, the control
lines carry the command indicating a Read or a Write operation and whether a byte or a word
is to be transferred. The control lines also provide the necessary timing information and are
used by the memory to indicate when it has completed the requested operation.
• Data transfer between the memory and the processor takes place through the use of two
processor registers, usually called MAR (memory address register) and MDR (memory data
register). If MAR is k bits long and MDR is n bits long, then the memory unit may contain up
to 2k addressable locations.
• During a memory cycle, n bits of data are transferred between the memory and the processor.
This transfer takes place over the processor bus, which has k address lines and n data lines.
̅̅̅̅̅̅̅̅ (R/𝑊
The bus also includes the control lines Read/𝑊𝑟𝑖𝑡𝑒 ̅ ) and Memory Function Completed

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(MFC) for coordinating data transfers. Other control lines may be added to indicate the
number of bytes to be transferred. The connection between the processor and the memory is
shown schematically in Figure 4.17.
• The processor reads data from the memory by loading the address of the required memory

̅̅̅̅ line to 1. The memory responds by

location into the MAR register and setting the R/𝑊

placing the data from the addressed location onto the data lines, and confirms this action by

asserting the MFC signal. Upon receipt of the MFC signal, the processor loads the data on the

data lines into the MIDR register.

• The processor writes data into a memory location by loading the address of this location into

MAR and loading the data into MDR. It indicates that a write operation is involved by setting

̅ line to 0.
the R/𝑊

• If read or write operations involve consecutive address locations in the main mem-ory, then a

"block transfer" operation can be performed in which the only address sent to the memory is

the one that identifies the first location.

Figure 4.17: Connection of the memory to the processor.

• A useful measure of the speed of memory units is the time that elapses between the initiation
of an operation to transfer a word of data and the completion of that operation. This is referred
to as the memory access time.
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• Another important measure is the memory cycle time, which is the minimum time delay
required between the initiation of two successive memory operations, for example, the time
between two successive Read operations. The cycle time is usually slightly longer than the
access time, depending on the implementation details of the memory unit.
• A memory unit is called a Random-Access Memory (RAM) if the access time to any location
is the same, independent of the location’s address. This distinguishes such memory units from
serial, or partly serial, access storage devices such as magnetic and optical disks. Access time
of the latter devices depends on the address or position of the data. The technology for
implementing computer memories uses semiconductor integrated circuits.

4.5.1 Cache and Virtual Memory

• The processor of a computer can usually process instructions and data faster than they can be
fetched from the main memory. Hence, the memory access time is the bottleneck in the
system. One way to reduce the memory access time is to use a cache memory. This is a small,
fast memory inserted between the larger, slower main memory and the processor. It holds the
currently active portions of a program and their data.
• Virtual memory is another important concept related to memory organization. With this
technique, only the active portions of a program are stored in the main memory, and the
remainder is stored on the much larger secondary storage device. Sections of the program are
transferred back and forth between the main memory and the secondary storage device in a
manner that is transparent to the application program. As a result, the application program
sees a memory that is much larger than the computer’s physical main memory.
4.6 Semiconductor RAM Memories:
• Semiconductor random-access memories (RAMs) are available in a wide range of speeds.
Their cycle times range from 100 ns to less than 10 ns. In this section, we discuss the way that
memory cells are organized inside a chip.
4.6.1 Internal Organization of Memory Chips:
• Memory cells are usually organized in the form of an array, in which each cell is capable of
storing one bit of information. A possible organization is illustrated in Figure 4.18 below.
Each row of cells constitutes a memory word, and all cells of a row are connected to a
common line referred to as the word line, which is driven by the address decoder on the chip.
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• The cells in each column are connected to a Sense/Write circuit by two bit lines, and the
Sense/Write circuits are connected to the data input/output lines of the chip.
• During a Read operation, these circuits sense, or read, the information stored in the cells
selected by a word line and place this information on the output data lines.
• During a Write operation, the Sense/Write circuits receive input data and store them in the
cells of the selected word.
• Figure 4.18 is an example of a very small memory circuit consisting of 16 words of 8 bits
each i.e; a 16 × 8 organization. A single bidirectional data line, Two control lines, R/W and
̅̅̅̅ (Read/𝑊𝑟𝑖𝑡𝑒
CS, are provided. The R/𝑊 ̅̅̅̅̅̅̅̅) input specifies the required operation, and the CS
(Chip Select) input selects a given chip in a multichip memory system.
• The memory circuit in Figure 4.18 stores 128 bits and requires 14 external connections for
address, data, and control lines. It also needs two lines for power supply and ground
connections. Consider now a slightly larger memory circuit, one that has 1K (1024) memory
cells shown in figure 14. This circuit can be organized as a 128 × 8 memory, requiring a total
of 19 external connections.
• Alternatively, the same number of cells can be organized into a 1K×1 format. In this case, a
10-bit address is needed, but there is only one data line, resulting in 15 external connections.
Figure 4.19 shows such an organization.

Figure 4.18: Organization of bit cells in a memory chip.

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Figure 4.19: Organization of a 1K ×1 memory chip

• The required 10-bit address is divided into two groups of 5 bits each to form the row and

column addresses for the cell array. A row address selects a row of 32 cells, all of which are

accessed in parallel. But, only one of these cells is connected to the external data line, based

on the column address by the output Mutliplexer and input demultiplexer.

• Large chips have essentially the same organization as Figure 4.18 and Figure 4.19, but use a

larger memory cell array and have more external connections. For example, a 4M-bit chip

may have a 512K × 8 organization, in which case a 19 address is needed and 8 data

input/output pins are needed.

4.6.2 Static Memories

• Memories that consist of circuits capable of retaining their state as long as power is applied

are known as static memories. Figure 4.20 illustrates how a static RAM (SRAM) cell may be

implemented.

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• Two inverters are cross-connected to form a latch. The latch is connected to two bit lines by

transistors T1 and T2. These transistors act as switches that can be opened or closed under

control of the word line.

• When the word line is at ground level, the transistors are turned off and the latch retains its

state. For example, if the logic value at point X is 1 and at point Y is 0, this state is maintained

as long as the signal on the word line is at ground level. Assume that this state represents the

value 1.

Figure 4.20: A static RAM cell

4.6.2.1 Read Operation

• In order to read the state of the SRAM cell, the word line is activated to close switches T1 and

T2. If the cell is in state 1, the signal on bit line b is high and the signal on bit line 𝑏 ′ is low.

• The opposite is true if the cell is in state 0. Thus, b and 𝑏 ′ are always complements of each

other. The Sense/Write circuit at the end of the two bit lines monitors their stateand sets the

corresponding output accordingly.

4.6.2.2 Write Operation

• During a Write operation, the Sense/Write circuit drives bit lines b and 𝑏 ′ , instead of sensing

their state. It places the appropriate value on bit line b and its complement on 𝑏 ′ and activates

the word line.

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• This forces the cell into the corresponding state, which the cell retains when the word line is

deactivated.

4.6.3 Asynchoronous Dynamic RAMs

• Static RAMs are fast, but their cells require several transistors. Less expensive and higher

density RAMs can be implemented with simpler cells. But, these simpler cells do not retain

their state for a long period, unless they are accessed frequently for Read or Write operations.

Memories that use such cells are called dynamic RAMs (DRAMs).

• Information is stored in a dynamic memory cell in the form of a charge on a capacitor, but this

charge can be maintained for only tens of milliseconds. Since the cell is required to store

information for a much longer time, its contents must be periodically refreshed by restoring the

capacitor charge to its full value. This occurs when the contents of the cell are read or when

new information is written into it.

• An example of a dynamic memory cell that consists of a capacitor, C, and a transistor, T, is

shown in Figure 4.21. To store information in this cell, transistor T is turned on and an

appropriate voltage is applied to the bit line.

• This causes a known amount of charge to be stored in the capacitor. After the transistor is

turned off, the charge remains stored in the capacitor, but not for long. The capacitor begins to

discharge. This is because the transistor continues to conduct a tiny amount of current,

measured in pico amperes, after it is turned off.

• Hence, the information stored in the cell can be retrieved correctly only if it is read before the

charge in the capacitor drops below some threshold value. During a Read operation, the

transistor in a selected cell is turned on.

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Figure 4.21: A single transistor dynamic memory cell

• A sense amplifier connected to the bit line detects whether the charge stored in the capacitor is

above or below the threshold value. If the charge is above the threshold, the sense amplifier

drives the bit line to the full voltage representing the logic value 1. As a result, the capacitor is

recharged to the full charge corresponding to the logic. value 1.

• If the sense amplifier detects that the charge in the capacitor is below the threshold value, it

pulls the bit line to ground level to discharge the capacitor fully. Thus, reading the contents of a

cell automatically refreshes its contents. Since the word line is common to all cells in a row, all

cells in a selected row are read and refreshed at the same time.

• A 16 -Megabit DRAM chip, configured as 2M × 8, is shown in Figure 4.22 The cells are

organized in the form of a 4K × 4K array. The 4096 cells in each row are divided into 512

groups of 8, forming 512 bytes of data. Therefore, 12 address bits are needed to select a row,

and another 9 bits are needed to specify a group of 8 bits in the selected row. In total, a 21-bit

address is needed to access a byte in this memory. The high-order 12 bits and the low-order 9

bits of the address constitute the row and column addresses of a byte, respectively.

• During a Read or a Write operation, the row address is applied first. It is loaded into the row

address latch in response to a signal pulse on an input control line called the Row Address

Strobe (RAS). This causes a Read operation to be initiated, in which all cells in the selected

row are read and refreshed.

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Figure 4.22: Internal organization of a 2M × 8 dynamic memory chip

• Shortly after the row address is loaded, the column address is applied to the address pins and

loaded into the column address latch under control of a second control line called the Column

Address Strobe (CAS). The information in this latch is decoded and the appropriate group of 8

Sense/Write circuits is selected.

• ̅ control signal indicates a Read operation, the output values of the selected circuits
If the R/𝑊

are transferred to the data lines, D7−0.

• For a Write operation, the information on the D7−0 lines is transferred to the selected circuits,

then used to overwrite the contents of the selected cells in the corresponding 8 columns. We

should note that in commercial DRAM chips, the RAS and CAS control signals are active

when low. Hence, addresses are latched when these signals change from high to low. The

signals are shown in diagrams as RAS and CAS to indicate this fact.

• The timing of the operation of the DRAM described above is controlled by the RAS and CAS
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signals. These signals are generated by a memory controller circuit external to the chip when

the processor issues a Read or a Write command. During a Read operation, the output data are

transferred to the processor after a delay equivalent to the memory’s access time. Such

memories are referred to as asynchronous DRAMs.

• A block of data can be transferred at a much faster rate than can be achieved for transfers

involving random addresses. The block transfer capability is referred to as the fast page mode

feature. (A large block of data is often called a page.) The faster rate attainable in the fast page

mode makes dynamic RAMs particularly well suited to this environment.

4.6.4 Synchronous DRAMs:

• More recent developments in memory technology have resulted in DRAMs whose operation is

directly synchronized with a clock signal. Such memories are known as synchronous DRAMs

(SDRAMs). Figure 4.22 indicates the structure of an SDRAM. The cell array is the same as in

asynchronous DRAMs. The address and data connections are buffered by means of registers.

We should particularly note that the output of each sense amplifier is connected to a latch.

• A Read operation causes the contents of all cells in the selected row to be loaded into these

latches. But, if an access is made for refreshing purposes only, it will not change the contents

of these latches; it will merely refresh the contents of the cells. Data held in the latches that

correspond to the selected column(s) are transferred into the data output register, thus

becoming available on the data output pins.

• SDRAMs have several different modes of operation, which can be selected by writing control

information into a mode register. For example, burst operations of different lengths can be

specified. The burst operations use the block transfer capability as the fast page mode feature.

In SDRAMs, it is not necessary to provide externally generated pulses on the CAS line to select

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successive columns. The necessary control signals are provided internally using a column

counter and the clock signal. New data can be placed on the data lines in each clock cycle. All

actions are triggered by the rising edge of the clock.

Figure 4.23 Synchronous DRAM

• SDRAMs have built-in refresh circuitry. A part of this circuitry is a refresh counter, which

provides the addresses of the rows that are selected for refreshing. In a typical SDRAM, each

row must be refreshed at least every 64 ms.

• The term memory latency is used to refer to the amount of time it takes to transfer a word of

data to or from the memory. In the case of reading or writing a single word of data, the latency

provides a complete indication of memory performance.

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• When transferring blocks of data, it is of interest to know how much time is needed to transfer

an entire block. Since blocks can be variable in size, it is useful to define a performance

measure in terms of the number of bits or bytes that can be transferred in one second. This

measure is often referred to as the memory bandwidth.

• A similar memory device is available, which accesses the cell array in the same way, but

transfers data on both edges of the clock. The latency of these devices is the same as for

standard SDRAMs. But, since they transfer data on both edges of the clock, their bandwidth is

essentially doubled for long burst transfers. Such devices are known as double-data-rate

SDRAMs (DDR SDRAMS).

4.7 Read-only Memories

• Both static and dynamic RAM chips are volatile, which means that they retain information

only while power is turned on. There are many applications requiring memory devices that

retain the stored information when power is turned off. Many embedded applications do not

use a hard disk and require nonvolatile memories to store their software.

• A special writing process is needed to place the information into a nonvolatile memory. Since

its normal operation involves only reading the stored data, a memory of this type is called a

read-only memory (ROM). Figure 4.24 shows a possible configuration of a ROM cell.

Figure 4.24 A ROM cell

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• A logic value 0 is stored in the cell if the transistor is connected to ground at point P; otherwise,

a 1 is stored. The bit line is connected through a resistor to the power supply. To read the state of

the cell, the word line is activated to close the transistor switch. As a result, the voltage on the bit

line drops to near zero if there is a connection between the transistor and ground.

• If there is no connection to ground, the bit line remains at the high voltage level, indicating a 1.

A sense circuit at the end of the bit line generates the proper output value. The state of the

connection to ground in each cell is determined when the chip is manufactured, using a mask

with a pattern that represents the information to be stored.

4.7.1 PROM

• Some ROM designs allow the data to be loaded by the user, thus providing a programmable

ROM (PROM). Programmability is achieved by inserting a fuse at point P Before it is

programmed, the memory contains all 0s. The user can insert 1s at the required locations by

burning out the fuses at these locations using high-current pulses. Of course, this process is

irreversible.

• PROMs provide flexibility and convenience not available with ROMs. The cost of preparing

the masks needed for storing a particular information pattern makes ROMs cost effective only

in large volumes. The alternative technology of PROMs provides a more convenient and

considerably less expensive approach, because memory chips can be programmed directly by

the user

4.7.2 EPROM

• Another type of ROM chip provides an even higher level of convenience. It allows the stored

data to be erased and new data to be written into it. Such an erasable, reprogrammable ROM is

usually called an EPROM. It provides considerable flexibility during the development phase of

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digital systems. Since EPROMs are capable of retaining stored information for a long time, they

can be used in place of ROMs or PROMs while software is being developed. In this way,

memory changes and updates can be easily made.

o An EPROM cell has a structure similar to the ROM cell in Figure 4.24. However, the connection

to ground at point P is made through a special transistor. The transistor is normally turned off,

creating an open switch. It can be turned on by injecting charge into it that becomes trapped

inside. Thus, an EPROM cell can be used to construct a memory in the same way as the

previously discussed ROM cell. Erasure requires dissipating the charge trapped in the transistors

that form the memory cells. This can be done by exposing the chip to ultraviolet light, which

erases the entire contents of the chip. To make this possible, EPROM chips are mounted in

packages that have transparent windows.

4.7.3 EEPROM

• An EPROM must be physically removed from the circuit for reprogramming. Also, the stored

information cannot be erased selectively. The entire contents of the chip are erased when

exposed to ultraviolet light. Another type of erasable PROM can be programmed, erased, and

reprogrammed electrically. Such a chip is called an electrically erasable PROM, or EEPROM.

It does not have to be removed for erasure.

• Moreover, it is possible to erase the cell contents selectively. One disadvantage of EEPROMs

is that different voltages are needed for erasing, writing, and reading the stored data, which

increases circuit complexity. However, this disadvantage is outweighed by the many

advantages of EEPROMs. They have replaced EPROMs in practice.

4.7.4 Flash Memory

• An approach similar to EEPROM technology has given rise to flash memory devices. A flash

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cell is based on a single transistor controlled by trapped charge, much like an EEPROM cell.

Also like an EEPROM, it is possible to read the contents of a single cell. The key difference is

that, in a flash device, it is only possible to write an entire block of cells. Prior to writing, the

previous contents of the block are erased. Flash devices have greater density, which leads to

higher capacity and a lower cost per bit. They require a single power supply voltage, and

consume less power in their operation.

• The low power consumption of flash memories makes them attractive for use in portable,

battery-powered equipment. Typical applications include hand-held computers, cell phones,

digital cameras, and MP3 music players. In hand-held computers and cell phones, a flash

memory holds the software needed to operate the equipment, thus obviating the need for a disk

drive. A flash memory is used in digital cameras to store picture data. In MP3 players, flash

memories store the data that represent sound. Cell phones, digital cameras, and MP3 players are

good examples of embedded systems.

• Single flash chips may not provide sufficient storage capacity for the applications mentioned

above. Larger memory modules consisting of a number of chips are used where needed. There

are two popular choices for the implementation of such modules: flash cards and flash drives.

4.8 Speed, size and cost

• As an ideal memory would be fast, large, and inexpensive. We know that a very fast memory

can be implemented if SRAM chips are used. But these chips are expensive. Thus, for cost

reasons, it is impractical to build a large memory using SRAM chips. The alternative is to use

Dynamic RAM chips, which have much simpler basic cells and thus are much less expensive.

But such memories are significantly slower.

• Although dynamic memory units in the range of hundreds of megabytes can be implemented at a

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reasonable cost, the affordable size is still small compared to the demands of large programs

with voluminous data. A solution is provided by using secondary storage, mainly magnetic

disks, to implement large memory spaces. Very large disks are available at a reasonable price,

and they are used extensively in computer systems. However, they are much slower than the

semiconductor memory units. So we conclude the following: A huge amount of cost-effective

storage can be provided by magnetic disks. A large, yet affordable, main memory can be built

with dynamic RAM technology. This leaves SRAMs to be used in smaller units where speed is

of the essence, such as in cache memories.

Figure 4.25: Memory hierarchy

• All of these different types of memory units are employed effectively in a computer. The entire

computer memory can be viewed as the hierarchy depicted in Figure below. The fastest access is

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to data held in processor registers. Therefore, if we consider the registers to be part of the

memory hierarchy, then the processor registers are at the top in terms of the speed of access. Of

course, the registers provide only a minuscule portion of the required memory.

• At the next level of the hierarchy is a relatively small amount of memory that can be

implemented directly on the processor chip. This memory, called a processor cache, holds

copies of instructions and data stored in a much larger memory that is provided externally.

There are often two levels of caches. A primary cache is always located on the processor chip.

This cache is small because it competes for space on the processor chip, which must implement

many other functions. The primary cache is referred to as level 1 (L1) cache. A larger,

secondary cache is placed between the primary cache and the rest of the memory. It is referred

to as level 2 (L2) cache. It is usually implemented using SRAM chips.

• Including a primary cache on the processor chip and using a larger, off-chip, secondary cache

is currently the most common way of designing computers. However, other arrangements can

be found in practice. It is possible not to have a cache on the processor chip at all. Also, it is

possible to have both L1 and L2 caches on the processor chip.

• The next level in hierarchy is called main memory. Thus rather large memory is implemented

using dynamic memory components typically in the form of SIMMs, DIMMs, or

RIMMs. The main memory is much larger but significantly slower than the cache memory. In

a typical computer, the access time for the main memory is about ten times longer than the

access time for the L1 cache.

• Disk devices provide a huge amount of inexpensive storage. They are very slow compared to

the semiconductor devices used to implement the main memory. During program execution,

the speed of memory access is of utmost importance. The key to managing the operation of the

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hierarchical memory system is to bring the instructions and data that will be used in the near

future as close to the processor as possible.

4.9 Cache Memories

• The cache is a small and very fast memory, interposed between the processor and the main

memory. Its purpose is to make the main memory appear to the processor to be much faster than

it actually is. The effectiveness of this approach is based on a property of computer programs

called locality of reference.

• Analysis of programs shows that most of their execution time is spent in routines in which many

instructions are executed repeatedly. These instructions may constitute a simple loop, nested

loops, or a few procedures that repeatedly call each other. The point is that many instructions in

localized areas of the program are executed repeatedly during some time period. This behavior

manifests itself in two ways: temporal and spatial.

Figure 4.26 Use of Cache memory

• Consider the arrangement in Figure 4.13. When the processor issues a Read request, the

contents of a block of memory words containing the location specified are transferred into the

cache. Subsequently, when the program references any of the locations in this block, the

desired contents are read directly from the cache. Usually, the cache memory can store a

reasonable number of blocks at any given time, but this number is small compared to the total

number of blocks in the main memory.

• The correspondence between the main memory blocks and those in the cache is specified by a
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mapping function. When the cache is full and a memory word (instruction or data) that is not in

the cache is referenced, the cache control hardware must decide which block should be

removed to create space for the new block that contains the referenced word. The collection of

rules for making this decision constitutes the cache’s replacement algorithm.

replacement algorithm.

Cache Hits

• The cache control circuitry determines whether the requested word that is requested by the

processor currently exists in the cache. If it does, the Read or Write operation is performed on

the appropriate cache location. In this case, a read or write hit is said to have occurred.

• For a Write operation, the system can proceed in one of two ways. In the first technique, called

the write-through protocol, both the cache location and the main memory location are updated.

• The second technique is to update only the cache location and to mark the block containing it

with an associated flag bit, often called the dirty or modified bit. The main memory location of

the word is updated later, when the block containing this marked word is removed from the

cache to make room for a new block. This technique is known as the write-back, or copy-back,

protocol.

Cache Misses

• A Read operation for a word that is not in the cache constitutes a Read miss. It causes the block

of words containing the requested word to be copied from the main memory into the cache.

After the entire block is loaded into the cache, the particular word requested is forwarded to the

processor. Alternatively, this word may be sent to the processor as soon as it is read from the

main memory. The latter approach, which is called load-through, or early restart, reduces the

processor’s waiting time somewhat, at the expense of more complex circuitry.

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• When a Write miss occurs in a computer that uses the write-through protocol, the information

is written directly into the main memory. For the write-back protocol, the block containing the

addressed word is first brought into the cache, and then the desired word in the cache is

overwritten with the new information.

4.9.1 Mapping Functions

• There are several possible methods for determining where memory blocks are placed in the

cache. It is instructive to describe these methods using a specific small example.

• Consider a cache consisting of 128 blocks of 16 words each, for a total of 2048 (2K) words,

and assume that the main memory is addressable by a 16-bit address. The main memory has

64K words, which we will view as 4K blocks of 16 words each. For simplicity, we have

assumed that consecutive addresses refer to consecutive words.

4.9.1.1 Direct Mapping

• The simplest way to determine cache locations in which to store memory blocks is the direct-

mapping technique. In this technique, block j of the main memory maps onto block j modulo

128 of the cache, as depicted in Figure 4.27. Thus, whenever one of the main memory blocks

0, 128, 256, . . . is loaded into the cache, it is stored in cache block 0. Blocks 1, 129, 257, . . .

are stored in cache block 1, and so on. Since more than one memory block is mapped onto a

given cache block position, contention may arise for that position even when the cache is not

full.

• For example, instructions of a program may start in block 1 and continue in block 129,

possibly after a branch. As this program is executed, both of these blocks must be transferred

to the block-1 position in the cache. Contention is resolved by allowing the new block to

overwrite the currently resident block.

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Figure 4.27: Direct-mapped cache

4.9.1.2 Associative Mapping

• Figure 4.28 shows the most flexible mapping method, in which a main memory block can be

placed into any cache block position. In this case, 12 tag bits are required to identify a memory

block when it is resident in the cache. The tag bits of an address received from the processor

are compared to the tag bits of each block of the cache to see if the desired block is present.

This is called the associative-mapping technique.

• When a new block is brought into the cache, it replaces (ejects)an existing block only if the

cache is full. In this case, we need an algorithm to select the block to be replaced.

• The complexity of an associative cache is higher than that of a direct-mapped cache, because of

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the need to search all 128 tag patterns to determine whether a given block is in the cache. To

avoid a long delay, the tags must be searched in parallel. A search of this kind is called an

associative search.

Figure 4.28: Associative-mapped cache.

4.9.1.3 Set-Associative Mapping

• Another approach is to use a combination of the direct- and associative-mapping techniques. The

blocks of the cache are grouped into sets, and the mapping allows a block of the main memory to

reside in any block of a specific set. Hence, the contention problem of the direct method is eased

by having a few choices for block placement.

• At the same time, the hardware cost is reduced by decreasing the size of the associative search.

An example of this set-associative-mapping technique is shown in Figure 8.18 for a cache with

two blocks per set. In this case, memory blocks 0, 64, 128, . . . , 4032 map into cache set 0, and

they can occupy either of the two block positions within this set. Having 64 sets means that the

6-bit set field of the address determines which set of the cache might contain the desired block.
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• The tag field of the address must then be associatively compared to the tags of the two blocks of

the set to check if the desired block is present. This two-way associative search is simple to

implement.

• The number of blocks per set is a parameter that can be selected to suit the requirements of a

particular computer. For the main memory and cache sizes in Figure 8.18, four blocks per set

can be accommodated by a 5-bit set field, eight blocks per set by a 4-bit set field, and so on.

• The extreme condition of 128 blocks per set requires no set bits and corresponds to the fully-

associative technique, with 12 tag bits. The other extreme of one block per set is the direct-

mapping method. A cache that has k blocks per set is referred to as a k-way set-associative

cache.

Fig 4.29 Set-associative-mapped cache with two blocks per set.

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4.9.2 Replacement Algorithms

• In a direct-mapped cache, the position of each block is predetermined by its address; hence, the

replacement strategy is trivial. In associative and set-associative caches there exists some

flexibility. When a new block is to be brought into the cache and all the positions that bit may

occupy are full, the cache controller must decide which of the old blocks to overwrite. This is an

important issue, because the decision can be a strong determining factor in system performance.

• In general, the objective is to keep blocks in the cache that are likely to be referenced in the near

future. But, it is not easy to determine which blocks are about to be referenced. The property of

locality of reference in programs gives a clue to a reasonable strategy. Because program

execution usually stays in localized areas for reasonable periods of time, there is a high

probability that the blocks that have been referenced recently will be referenced again soon.

Therefore, when a block is to be overwritten, it is sensible to overwrite the one that has gone the

longest time without being referenced. This block is called the least recently used (LRU) block,

and the technique is called the LRU replacement algorithm.

• To use the LRU algorithm, the cache controller must track references to all blocks as

computation proceeds. Suppose it is required to track the LRU block of four-block set in a set-

associative cache. A 2-bit counter can be used for each block. When a hit occurs, the counter of

the block that is referenced is set to 0. Counters with values originally lower than the referenced

one are incremented by one, and all others remain unchanged.

• When a miss occurs and the set is not full, the counter associated with the new block loaded

from the main memory is set to 0, and the values of all other counters are increased by one.

When a miss occurs and the set is full, the block with the counter value 3 is removed, the new

block is put in its place, and its counter is set to 0. The other three block counters are

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incremented by one. It can be easily verified that the counter values of occupied blocks are

always distinct.

• The simplest algorithm is to randomly choose the block to be overwritten. this simple algorithm

has been found to be quite effective in practice.

4.10 Performance Considerations

• Two key factors in the commercial success of a computer are performance and cost; the best

possible performance for a given cost is the objective. A common measure of success is the

price/performance ratio. Performance depends on how fast machine instructions can be brought

into the processor and how fast they can be executed.

• The main purpose of this hierarchy is to create a memory that the processor sees as having a

short access time and a large capacity. When a cache is used, the processor is able to access

instructions and data more quickly when the data from the referenced memory locations are in

the cache. Therefore, the extent to which caches improve performance is dependent on how

frequently the requested instructions and data are found in the cache. In this section, we examine

this issue quantitatively.

4.10.1. Interleaving:

• If the main memory of a computer is structured as a collection of physically separate modules,

each with its own address buffer register (ABR) and data buffer register (DBR), memory access

operations may proceed in more than one module at the same time. Thus, the aggregate rate of

transmission of words to and from the main memory system can be increased.

• How individual addresses are distributed over the modules is critical in determining the average

number of modules that can be kept busy as computations proceed.

• Two methods of address layout are indicated in Figure 4.30.

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Fig 4.30 Addressing multiple-module memory system

• In the first case, the memory address generated by the processor is decoded. The high- order k

bits name one of n modules, and the low-order m bits name a particular word in that module.

When consecutive locations are accessed, as happens when a block of data is transferred to a

cache, only one module is involved. At the same time, however, devices with direct memory

access (DMA) ability may be accessing information in other memory modules.

• The second and more effective way to address the modules is shown in Figure. It is called

memory interleaving. The low-order k bits of the memory address select a module, and the high-

order m bits name a location within that module. In this way, consecutive addresses are located

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in successive modules. Thus, any component of the system that generates requests for access to

consecutive memory locations can keep several modules busy at any one time. This results in

both faster access to a block of data and higher average utilization of the memory system as a

whole. To implement the interleaved structure, there must be 24 modules; otherwise, there will

be gaps of nonexistent locations in the memory address space.

• The effect of interleaving is substantial. Consider the time needed to transfer a block of data

from the main memory to the cache when a read miss occurs. Suppose that a cache with 8-word

blocks is used, similar to our examples in Section 5.5. On a read miss, the block that contains the

desired word must be copied from the memory into the cache. Assume that the hardware has the

following properties. It takes one clock cycle to send an address to the main memory.

• The memory is built with relatively slow DRAM chips that allow the first word to be accessed in

8 cycles, but subsequent words of the block are accessed in 4 clock cycles per word. when

consecutive locations in a DRAM are read from a given row of cells, the row address is decoded

only once. Addresses of consecutive columns of the array are then applied to access the desired

words, which takes only half the time per access.) Also, one clock cycle is needed to send one

word to the cache.

• If a single memory module is used, then the time needed to load the desired block into the cache

Is 1+8+ (7x4)+1=38 cycles.

4.10.2 Hit Rate and Miss Penalty

• An excellent indicator of the effectiveness of a particular implementation of the memory

hierarchy is the success rate in accessing information at various levels of the hierarchy. As a

successful access to data in a cache is called a hit. The number of hits stated as a fraction of all

attempted accesses is called the hit rate, and the miss rate is the number of misses stated as a

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fraction of attempted accesses.

• Ideally, the entire memory hierarchy would appear to the processor as a single memory unit

that has the access time of the cache on the processor chip and the size of the magnetic disk.

How close we get to this ideal depends largely on the hit rate at different levels of the

hierarchy. High hit rates well over 0.9 are essential for high-performance computers.

• Performance is adversely affected by the actions that need to be taken when a miss occurs. A

performance penalty is incurred because of the extra time needed to bring a block of data from

a slower unit in the memory hierarchy to a faster unit. During that period, the processor is

stalled waiting for instructions or data. The waiting time depends on the details of the operation

of the cache. For example, it depends on whether or not the load-through approach is used. We

refer to the total access time seen by the processor when a miss occurs as the miss penalty.

• Consider a system with only one level of cache. In this case, the miss penalty consists almost

entirely of the time to access a block of data in the main memory. Let h be the hit rate, M the

miss penalty, and C the time to access information in the cache. Thus, the average access time

experienced by the processor is

𝑡𝑎𝑣𝑔 = hC + (1 − h)M

4.11 Virtual memories:

• In most modern computer systems, the physical main memory is not as large as the address

space of the processor. For example, a processor that issues 32-bit addresses has an addressable

space of 4G bytes. The size of the main memory in a typical computer with a 32-bit processor

may range from 1G to 4G bytes. If a program does not completely fit into the main memory,

the parts of it not currently being executed are stored on a secondary storage device, typically a

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magnetic disk. As these parts are needed for execution, they must first be brought into the main

memory, possibly replacing other parts that are already in the memory. These actions are

performed automatically by the operating system, using a scheme known as virtual memory.

4.11.1 Virtual Memory Organization

• Figure 8.24 shows a typical organization that implements virtual memory.

Figure 4.31 Virtual memory organization

• Under a virtual memory system, programs, and hence the processor, reference instructions

and data in an address space that is independent of the available physical main memory space.

• The binary addresses that the processor issues for either instructions or data are called virtual

or logical addresses. These addresses are translated into physical addresses by a combination

of hardware and software actions.

• If a virtual address refers to a part of the program or data space that is currently in the physical

memory, then the contents of the appropriate location in the main memory are accessed

immediately. Otherwise, the contents of the referenced address must be brought into a suitable

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location in the memory before they can be used.

• A special hardware unit, called the Memory Management Unit (MMU), keeps track of which

parts of the virtual address space are in the physical memory. When the desired data or

instructions are in the main memory, the MMU translates the virtual address into the

corresponding physical address.

• If the data are not in the main memory, the MMU causes the operating system to transfer the

data from the disk to the memory.

4.11.2 Address Translation

• A simple method for translating virtual addresses into physical addresses is to assume that all

programs and data are composed of fixed-length units called pages, each of which consists of a

block of words that occupy contiguous locations in the main memory.

• Pages commonly range from 2K to 16K bytes in length. They constitute the basic unit of

information that is transferred between the main memory and the disk whenever the MMU

determines that a transfer is required.

• Pages should not be too small, because the access time of a magnetic disk is much longer

(several milliseconds) than the access time of the main memory.

• A virtual-memory address-translation method based on the concept of fixed-length pages is

shown schematically in Figure 4.32. Each virtual address generated by the processor, whether

it is for an instruction fetch or an operand load/store operation, is interpreted as a virtual page

number (high-order bits) followed by an offset (low-order bits) that specifies the location of a

particular byte (or word) within a page.

• Information about the main memory location of each page is kept in a page table. This

information includes the main memory address where the page is stored and the current status

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of the page.

• An area in the main memory that can hold one page is called a page frame. The starting

address of the page table is kept in a page table base register. By adding the virtual page

number to the contents of this register, the address of the corresponding entry in the page table

is obtained. The contents of this location give the starting address of the page if that page

currently resides in the main memory.

Figure 4.32 Virtual-memory address translation

• Each entry in the page table also includes some control bits that describe the status of the page

while it is in the main memory. One bit indicates the validity of the page, that is, whether the

page is actually loaded in the main memory. It allows the operating system to invalidate the page

without actually removing it.

• Another bit indicates whether the page has been modified during its residency in the memory. As

in cache memories, this information is needed to determine whether the page should be written

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back to the disk before it is removed from the main memory to make room for another page.

4.11.3 Translation Lookaside Buffer

• The page table information is used by the MMU for every read and write access. Ideally, the

page table should be situated within the MMU. Unfortunately, the page table may be rather

large. Since the MMU is normally implemented as part of the processor chip, it is impossible

to include the complete table within the MMU. Instead, a copy of only a small portion of the

table is accommodated within the MMU, and the complete table is kept in the main memory.

• The portion maintained within the MMU consists of the entries corresponding to the most

recently accessed pages. They are stored in a small table, usually called the Translation

Lookaside Buffer (TLB).

• The TLB functions as a cache for the page table in the main memory. Each entry in the TLB

includes a copy of the information in the corresponding entry in the page table. In addition, it

includes the virtual address of the page, which is needed to search the TLB for a particular

page.

• Figure 4.33 shows a possible organization of a TLB that uses the associative mapping

technique. Set-associative mapped TLBs are also found in commercial products. Address

translation proceeds as follows. Given a virtual address, the MMU looks in the TLB for the

referenced page. If the page table entry for this page is found in the TLB, the physical address

is obtained immediately. If there is a miss in the TLB, then the required entry is obtained from

the page table in the main memory and the TLB is updated. It is essential to ensure that the

contents of the TLB are always the same as the contents of page tables in the memory. When

the operating system changes the contents of a page table, it must simultaneously invalidate the

corresponding entries in the TLB. One of the control bits in the TLB is provided for this

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purpose. When an entry is invalidated, the TLB acquires the new information from the page

table in the memory as part of the MMU’s normal response to access misses.

Figure 4.33 Use of an associative-mapped TLB.

4.11.4 Page Faults

• When a program generates an access request to a page that is not in the main memory, a page

fault is said to have occurred. The entire page must be brought from the disk into the memory

before access can proceed. When it detects a page fault, the MMU asks the operating system to

intervene by raising an exception (interrupt). Processing of the program that generated the page

fault is interrupted, and control is transferred to the operating system.

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• The operating system copies the requested page from the disk into the main memory. Since this

process involves a long delay, the operating system may begin execution of another program

whose pages are in the main memory. When page transfer is completed, the execution of the

interrupted program is resumed.

• When the MMU raises an interrupt to indicate a page fault, the instruction that requested the

memory access may have been partially executed. It is essential to ensure that the interrupted

program continues correctly when it resumes execution. There are two options. Either the

execution of the interrupted instruction continues from the point of interruption, or the

instruction must be restarted.

• The design of a particular processor dictates which of these two options is used. If a new page

is brought from the disk when the main memory is full, it must replace one of the resident

pages. The problem of choosing which page to remove is just as critical here as it is in a cache,

and the observation that programs spend most of their time in a few localized areas also

applies. Because main memories are considerably larger than cache memories, it should be

possible to keep relatively larger portions of a program in the main memory. This reduces the

frequency of transfers to and from the disk.

• Concepts similar to the LRU replacement algorithm can be applied to page replacement, and

the control bits in the page table entries can be used to record usage history. One simple

scheme is based on a control bit that is set to 1 whenever the corresponding page is referenced

(accessed). The operating system periodically clears this bit in all page table entries, thus

providing a simple way of determining which pages have not been used recently.

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4.12 Memory Management Requirements

• Memory management routines are part of the operating system of the computer. It is convenient

to assemble the operating system routines into a virtual address space, called the system space,

that is separate from the virtual space in which user application programs reside. The latter space

is called the user space. There may be a number of user spaces, one for each user. This is

arranged by providing a separate page table for each user program.

• The MMU uses a page table base register to determine the address of the table to be used in the

translation process. Hence, by changing the contents of this register, the operating system can

switch from one space to another.

• In any computer system in which independent user programs coexist in the main memory, the

notion of protection must be addressed. No program should be allowed to destroy either the data

or instructions of other programs in the memory. The needed protection an be provided in

several ways.

• Let us first consider the most basic form of protection. Most processors can operate in one of

two modes, the supervisor mode and the user mode. The processor is usually placed in the

supervisor mode when operating system routines are being executed and in the user mode to

execute user programs.

• In the user mode, some machine instructions cannot be executed. These are privileged

instructions. They include instructions that modify the page table base register, which can only

be executed while the processor is in the supervisor mode. Since a user program is executed in

the user mode, it is prevented from accessing the page tables of other users or of the system

space.

• It is sometimes desirable for one application program to have access to certain pages belonging

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to another program. The operating system can arrange this by causing these pages to appear in

both spaces. The shared pages will therefore have entries in two different pagetables. The

control bits in each table entry can be set to control the access privileges granted to each

program.

4.13 Secondary memory:

• The large storage requirements of most computer systems are economically realized in the form

of magnetic and optical disks, which are usually referred to as secondary storage devices.

4.13.1 Magnetic Hard Disks

• The storage medium in a magnetic-disk system consists of one or more disk platters mounted
on a common spindle. A thin magnetic film is deposited on each platter, usually on both sides.
The assembly is placed in a drive that causes it to rotate at a constant speed.

• The magnetized surfaces move in close proximity to read/write heads, as shown in Figure 4.34
a. Data are stored on concentric tracks, and the read/write heads move radially to access
different tracks.

• Each read/write head consists of a magnetic yoke and a magnetizing coil, as indicated in Figure
4.34b. Digital information can be stored on the magnetic film by applying current pulses of
suitable polarity to the magnetizing coil.

• This causes the magnetization of the film in the area immediately underneath the head to switch
to a direction parallel to the applied field. The same head can be used for reading the stored
information. In this case, changes in the magnetic field in the vicinity of the head caused by the
movement of the film relative to the yoke induce a voltage in the coil, which now serves as a
sense coil.

• The polarity of this voltage is monitored by the control circuitry to determine the state of
magnetization of the film. Only changes in the magnetic field under the head can be sensed
during the Read operation. Therefore, if the binary states 0 and 1 are represented by two
opposite states of magnetization, a voltage is induced in the head only at 0-to-1 and at 1-to-0
transitions in the bit stream.
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• A long string of 0s or 1s causes an induced voltage only at the beginning and end of the string.
Therefore, to determine the number of consecutive 0s or 1s stored, a clock must provide
information for synchronization.

Figure 4.34 Magnetic disk principles.

• Read/write heads must be maintained at a very small distance from the moving disk
surfaces in order to achieve high bit densities and reliable Read and Write operations.
When the disks are moving at their steady rate, air pressure develops between the disk
surface and the head and forces the head away from the surface.

• The read/write heads of a disk system are movable. There is one head per surface. All
heads are mounted on a comb-like arm that can move radially across the stack of disks to
provide access to individual tracks, as shown in Figure 4.34a.

• To read or write data on a given track, the read/write heads must first be positioned over
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that track

• The disk system consists of three key parts. One part is the assembly of disk platters,
which is usually referred to as the disk.

• The second part comprises the electromechanical mechanism that spins the disk and moves
the read/write heads; it is called the disk drive.

• The third part is the disk controller, which is the electronic circuitry that controls the
operation of the system.

• The disk controller may be implemented as a separate module, or it may be incorporated

into the enclosure that contains the entire disk system. We should note that the term disk is
often used to refer to the combined package of the disk drive and the disk it contains.

4.13.1.1 Organization and Accessing of Data on a Disk

• The organization of data on a disk is illustrated in Figure 4.35.

• Each surface is divided into concentric tracks, and each track is divided into sectors. The
set of corresponding tracks on all surfaces of a stack of disks forms a logical cylinder.

• All tracks of a cylinder can be accessed without moving the read/write heads. Data are
accessed by specifying the surface number, the track number, and the sector number. Read
and Write operations always start at sector boundaries.

Fig 4.35 Organization of one surface of a disk

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• Data bits are stored serially on each track. Each sector may contain 512 or more bytes. The
data are preceded by a sector header that contains identification (addressing) information
used to find the desired sector on the selected track.

• Following the data, there are additional bits that constitute an error-correcting code (ECC).
The ECC bits are used to detect and correct errors that may have occurred in writing or
reading the data bytes.

• There is a small inter-sector gap that enables the disk control circuitry to distinguish easily
between two consecutive sectors.

4.13.2 Optical Disks

• Storage devices can also be implemented using optical means. The familiar compact disk
(CD), used in audio systems, was the first practical application of this technology. Soon
after, the optical technology was adapted to the computer environment to provide a high
capacity read-only storage medium known as a CD-ROM.

• The first generation of CDs was developed in the mid-1980s by the Sony and Philips
companies. The technology exploited the possibility of using a digital representation for
analog sound signals.

• To provide high-quality sound recording and reproduction, 16-bit samples of the analog
signal are taken at a rate of 44,100 samples per second. Initially, CDs were designed to hold
up to 75 minutes, requiring a total of about 3 × 109 bits (3 gigabits) of storage. Since then,
higher-capacity devices have been developed.

4.13.2.1 CD ROM

• As the information is stored in binary form in CDs, they are suitable for use as a storage
medium in computer systems.

• Stored data are organized on CD-ROM tracks in the form of blocks that are called sectors.
There are different forms for a sector.

• One format, known as Mode 1, uses 2352- byte sectors. There is a 16-byte header that
contains a synchronization field used to detect the beginning of the sector and addressing
information used to identify the sector.
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• This is followed by 2048 bytes of stored data. At the end of the sector, there are 288 bytes
used to implement the error-correcting scheme. The number of sectors per track is
variable; there are more sectors on the longer outer tracks. With the Mode 1 format, a CD-
ROM has a storage capacity of about 650 Mbytes.

• Error detection and correction is done at more than one level. each byte of information
stored on a CD is encoded using a 14-bit code that has some error-correcting capability.
This code can correct single-bit errors.

• CD-ROM drives operate at a number of different rotational speeds. The basic speed,
known as 1X, is 75 sectors per second. This provides a data rate of 153,600 bytes/s (150
Kbytes/s), using the Mode 1 format.

• Higher speed CD-ROM drives are identified in relation to the basic speed. Thus, a 56X
CD-ROM has a data transfer rate that is 56 times that of the 1X CD-ROM, or about 6
Mbytes/s. This transfer rate is considerably lower than the transfer rates of magnetic hard
disks, which are in the range of tens of megabytes per second.

4.13.2.2 CD-Rewritable

• The most flexible CDs are those that can be written multiple times by the user. They are
known as CD-RWs (CD-ReWritables). The basic structure of CD-RWs is similar to the
structure of CD-Rs.

• CD drives designed to read and write CD-RW disks can usually be used with other compact
disk media. They can read CD-ROMs and can read and write CD-Rs.

• CD-RW disks provide low-cost storage media. They are suitable for archival storage of
information that may range from databases to photographic images. They can be used for
low-volume distribution of information, just like CD-Rs, and for backup purposes.

• The CD-RW technology has made CD-Rs less relevant because it offers superior capability
at only slightly higher cost.

4.13.2.3 DVD Technology

• The success of CD technology and the continuing quest for greater storage capability has led
to the development of DVD (Digital Versatile Disk) technology.
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• The first DVD standard as defined in 1996 by a consortium of companies, with the objective
of being able to store a full-length movie on one side of a DVD disk. The physical size of a
DVD disk is the same as that of CDs. The disk is 1.2 mm thick, and it is 120 mm in
diameter. Its storage capacity is made much larger than that of CDs by several design
changes.

• Access times for DVD drives are similar to CD drives. However, when the DVD disks rotate
at the same speed, the data transfer rates are much higher because of the higher density.
Rewritable versions of DVD devices have also been developed, providing large storage
capacities.

4.13.3 Magentic tape System

• Magnetic tapes are suited for off-line storage of large amounts of data. They are typically
used for backup purposes and for archival storage.

• Magnetic-tape recording uses the same principle as magnetic disks. The main difference is
that the magnetic film is deposited on a very thin 0.5- or 0.25-inch wide plastic tape. Seven
or nine bits (corresponding to one character) are recorded in parallel across the width of the
tape, perpendicular to the direction of motion.

• A separate read/write head is provided for each bit position on the tape, so that all bits of a
character can be read or written in parallel. One of the character bits is used as a parity bit.

• To help users organize large amounts of data, a group of related records is called a file. The
beginning of a file is identified by a file mark, as shown in Figure 4.36.

Fig 4.36 organization of data on magnetic tape

• The file mark is a special single- or multiple-character record, usually preceded by a gap

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longer than the inter-record gap.

• The first record following a file mark can be used as a header or identifier for the file. This
allows the user to search a tape containing a large number of files for a particular file.

Assignment-Cum-Tutorial Questions Part– A

Processor Organization

Objective Questions

1. A sequence of microinstructions constitute a [ ]

a) Micro-program b)micro-operation
c) micro-instruction d)microprocessor
2. The instruction,Add#45,R1does [ ]
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned.
3. A sequence of microinstructions constitutes a [ ]
a) Micro-program b)micro-operation
c) micro-instruction d)micro-processor
4. A memory that is part of control unit is referred to as [ ]
a) Cache memory b)control memory
c) main memory d) virtual memory
5. Whenthecontrolsignalsaregeneratedbyhardwareusingconventionallogicdesign techniques, the
control unit is said to be [ ]
a) programmed b)micro-programmed
c) hardwired d)none of the above

6. The next address generator is also called [ ]

a) Micro-program sequencer b)control unit
c)micro-instruction sequencer d)micro-programmed control

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7. The goals of both hard wired control and micro-programmed control units are to
a) Access memory b)access ALU [ ]
c) none d)generate control signals
8. Each computer instruction has its own in control memory to generate the micro-
operations that execute the instruction. [ ]
a) microinstruction b)branch instruction
c)mapping logic d)micro-program routine
9. The control register specifies the address of the microinstruction and the control
Register holds the microinstruction read from memory. [ ]
a) Address, data b)data, memory
c)memory, instruction d) data, instruction
10. A control memory has 4096words of 24bitseach.Howmanybits are there in the control address
register? [ ]
a) 12 b)24 c) 32 d)25
11. Themicroprogramwrittenasstringsof0’sand 1’sisa [ ]

a) Symbolic microinstruction b)binary microinstruction

c)symbolic micro-program d)binary micro-program
12. Address information in the microinstruction cannot be [ ]
a) Single address field b)two address field
c)variable format d)a control signal
13. Micro instruction execution is [ ]
a) To generate the control signals needed to execute the microinstruction
b) To get the next microinstruction from the control memory
c) To get the next instruction from the main memory
d) To get the microinstruction from the main memory
14. Microinstruction sequencing is [ ]
a) To get the next instruction from the main memory
b) To get the next microinstruction from the control memory
c) To get the microinstruction from the main memory
d) To generate the control signals needed to execute the microinstruction
15. A micro-program sequencer

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a) Generates the address of next microinstruction to be executed

b) Generates the control signals to execute a microinstruction.
c) Sequentially averages all microinstructions in the control memory.
d) Enables the efficient handling of a micro-program subroutine.

Descriptive Questions

S.No. Name of the Question BL

1. L1
What are the main components of a processor, and how do they contribute to
its operation?
2. L2
Describe the role of registers in processor organization and list some
common types.
3. L2
Outline the steps involved in the instruction execution cycle in a typical
CPU.
4. How does the CPU's Control Unit facilitate the execution of an instruction? L3
5. L2
Explain how control signals are generated using hardwired control signals.
6. L2
Explain how control signals are generated using microprogrammed control
signals.
7. L2
Differentiate between hardwired control unit and microprogrammed control
unit.
8. L2
Explain how a typical multiple-bus system is structured in a processor and the role
of each bus.

Part-Β

Memory Organization

Objective Questions

1. How many unique memory locations can a computer with a 16-bit addressing scheme

access? [ ]

A) 64K B) 4G C) 16E D) 2^64

2. In a byte-addressable memory system with 32-bit addressing, how many bytes can be

addressed? [ ]

A) 64K B) 4G C) 16E D) 2^32

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3.A computer with a 64-bit address bus can theoretically address up to: [ ]

A) 4G locations B) 64K locations C) 16E locations D) 2^16 locations

4. What is the term used to describe the time from initiation of a memory request to when the

data is available? [ ]

A) Memory Cycle Time B) Memory Access Time

C) Data Transfer Time D) Cache Hit Time

5. Which of the following is typically longer in duration than the memory access time?

[ ]

A) Memory Access Time B) Memory Cycle Time

C) Cache Access Time D) Bus Transfer Time

6.Which type of memory has uniform access time regardless of the address being accessed?

[ ]

A) Serial Access Memory B) Magnetic Disk

C) Random-Access Memory (RAM) D) Optical Disk

7.Which of the following types of storage typically has varying access times depending on the data

location? [ ]

A) RAM B) Cache Memory C) Optical Disk D) Solid State Drive (SSD)

8.What is the primary purpose of cache memory in a computer system? [ ]

A) To increase the total storage capacity of the computer

B) To reduce the time the processor needs to access frequently used data

C) To extend the apparent size of physical memory using disk storage

D) To store long-term data permanently

9.Virtual memory allows a computer to [ ]

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A) Run programs that are larger than physical memory

B) Store data on removable disks

C) Increase the physical size of RAM

D) Improve data transfer rates between CPU and RAM

10. In modern computer systems, data are typically transferred in [ ]

A) Single bytes

B) Contiguous blocks of data

C) Random access patterns

D) Single-word increments

11. The ability to efficiently transfer large blocks of data is crucial for: [ ]

A) Reducing cache misses

B) Optimizing CPU clock speed

C) Enhancing performance of memory and I/O operations

12. Which of the following is a primary characteristic of Static RAM (SRAM)? [ ]

A) It requires periodic refreshing to maintain data.

B) It uses a flip-flop circuit to store each bit of data.

C) It has slower access times compared to DRAM.

D) It is used primarily for long-term storage.

13. Which characteristic best describes Asynchronous DRAMs (ADR)? [ ]

A) They operate synchronously with the system clock.

B) They do not require a clock signal for timing operations.

C) They have faster access times compared to Synchronous DRAMs.

D) They are used primarily for high-speed cache memory.

14. What is the primary advantage of Synchronous DRAM (SDRAM) over Asynchronous

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DRAM?

[ ]

A) SDRAM does not require periodic refreshing.

B) SDRAM operates in sync with the system clock, allowing for faster and more predictable data
access.

C) SDRAM has a simpler memory cell structure.

D) SDRAM offers larger storage capacities compared to other DRAM types.

15. Which type of memory allows data to be electrically erased and reprogrammed?

[ ]

A) ROM B) PROM C) EPROM D) EEPROM

16. What is a key feature of Flash memory that differentiates it from other types of non-volatile

memory? [ ]

A) It requires power to maintain data.

B) It can be electrically erased and reprogrammed in blocks.

C) It has slower write speeds compared to SRAM.

D) It is used only for long-term data storage in CPUs.

17. Which of the following statements accurately reflects the typical trade-offs between speed, size, and

cost in memory systems? [ ]

A) Faster memory is always cheaper than slower memory and can store more data.

B) Larger memory sizes generally result in higher costs and slower access speeds.

C) High-speed memory, such as SRAM, is typically more expensive per bit and offers less
capacity compared to slower, larger memory types like DRAM.

D) Cost is independent of memory speed and size, and all memory types provide equal storage
capacities.

18. Which of the following replacement algorithms selects the cache block to be replaced based on the block

that has not been used for the longest period? [ ]

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A) Least Recently Used (LRU) B) First-In-First-Out (FIFO)

C) Optimal Page Replacement D) Random Replacement

Descriptive Questions

S.No. Name of the Question BL

1. Explain the different cache memory mapping functions using suitable diagrams. L2
2. Describe the organization of virtual memory in a computer system. L2
3. Differentiate between magnetic hard disks, optical disks, and magnetic tape systems. L2
4. Compare and contrast ROM, PROM, EPROM, and EEPROM. L2
5. Describe the organization of a semiconductor RAM memory chip. L2

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UNIT-V

INPUT-OUTPUT ORGANIZATION

Course Objectives

• To familiarize with the concept of I/O organization and interaction with processor & memory,
peripheral devices.

Course Outcome

• Explain I/O system and their interaction with processor, memory, peripheral devices.

• Differentiate between synchronous and asynchronous transfer.

Syllabus:

5.1 Accessing I/O Devices

5.1.1 Memory mapped I/O

5.1.2 I/O mapped I/O

5.1.3 Program Controlled I/O

5.1.4 Mechanisms Used For Interfacing I/O Operations

5.2 Interrupts

5.2.1 Interrupt Hardware

5.2.2 Enabling and Disabling Interrupts

5.3 Processor Examples

5.3.1 ARM Interrupt Structure

5.3.1.1 Introduction to ARM

5.3.1.2 Sources for Exceptions in ARM

5.3.2 68000 Interrupt Structure

5.3.2.1 Introduction

5.3.2.2 Interrupt structure

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5.4 Direct Memory Access

5.4.1 Modes of DMA Transfer

5.4.2 Use of DMA Controller

5.4.3 Bus Arbitration

5.4.3.1 Centralized Arbitration

5.4.3.2 Distributed Arbitration

5.5 Buses

5.5.1 Synchronous Bus

5.5.2 Asynchronous Bus

Introduction:

Peripheral devices

• The input-output subsystem of a computer, referred to as I/O.

• Input or output devices attached to the computer are also called peripherals.

• Among the most common peripherals are keyboards, display units, and printers.

• Devices that are under the direct control of the computer are said to be connected on-line.

• Video monitors are the most commonly used peripherals. They consist of a keyboard as the input

device and a display unit as the output device.

5.1 Accessing I/O Devices

Fig 5.1: A single-bus structure

The I/O devices are connected by using a single bus which enables data transaction between each

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deviceas shown in Fig 5.1

• Bus consists of 3 sets of lines used to carry address, data and control signals.

• Each I/O device is assigned a unique set of address. When the processor places a particular
address on the address lines, the device that recognizes this address responds to the commands
issued on the control lines.
• The processor requests either a read or a write operation which is transferred over the data lines.
When I/O devices and the memory share the same address space, the arrangement is called
memory-mapped I/O. There are two ways to deal with I/O devices.

5.1.1 Memory mapped I/O

• The Memory and I/O devices are sharing information by a common address-space. Any data-
transfer instruction (like Move, Load) can be used to exchange information. For example,
Move DATAIN, R0

• This instruction reads data from DATAIN (address of input-buffer associated with Keyboard) &
stores them into processor-register R0.
Move R0, DATAOUT

• This instruction sends the contents of register R0 to location DATAOUT, which may be the
output data buffer of a display unit or a printer.

5.1.2 I/O mapped I/O

• In I/O mapped I/O, the memory and I/0 address-spaces are different. Special instructions are
used fordata transfer such as IN and OUT.

• The I/O devices use special I/O address space or memory address space.
• The I/O devices examine the low-order bits of the address bus to determine whether they should
respond.
• Advantage of separate I/O space: I/O devices deal with fewer address-lines.
• The hardware required to connect an I/O device to the bus as shown in the Fig 5.2

• The address decoder enables the device to recognize its address when this address appears on the
address lines.
• The data register holds the data being transferred to or from the processor.
• The status register contains information relevant to the operation of the I/O device.
• Both the data and status registers are connected to the data bus and assigned unique addresses.

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The address decoder, the data and status registers, and the control circuitry required to coordinate
I/O transfers constitute the device's interface circuit.

Fig 5.2: I/O interface for an input device

5.1.3 Program Controlled I/O

• Processor repeatedly checks a status-flag to achieve required synchronization between processor

& input/output device. (We say that the processor polls the device).
Drawback: The processor wastes its time in checking the status of the device before actual data
transfer takes place.

5.1.4 Mechanisms Used For Interfacing I/O Operations:

Interrupt I/O
• Synchronization is achieved by having I/O device send a special signal over bus whenever it is
ready for a data transfer operation.

Direct Memory Access (DMA)

• This involves having the device-interface transfer data directly to or from the memory without
continuous involvement by the processor. This technique is used for high-speed I/O devices.

5.2 Interrupts

• There are many situations where other tasks can be performed while waiting for an I/O device to
become ready. A hardware signal called an Interrupt will alert the processor when an I/O device
becomes ready. It can do so by sending a hardware signal called an interrupt to the processor.

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Fig 5.3: Schematic of Interrupt I/O

• For example, consider, COMPUTE and PRINT routines. The routine executed in response to an
interrupt request is called interrupt-service routine.
• Transfer of control through the use of interrupts happens. The processor must inform the device
that its request has been recognized by sending interrupt-acknowledge signal.

Fig 5.4: Transfer of control through the interrupts

• One must therefore know the difference between Interrupt Vs Subroutine. Interrupt latency is
concerned with saving information in registers will increase the delay between the time an
interrupt request is received and the start of execution of the interrupt-service routine.
• Processor is executing the instruction located at address i when an interrupt occurs.
• Routine executed in response to an interrupt request is called the interrupt-service routine.
• When an interrupt occurs, control must be transferred to the interrupt service routine.
• But before transferring control, the current contents of the PC (i+1), must be saved in a known
location.
• This will enable the return-from-interrupt instruction to resume execution at i+1.

• Return address, or the contents of the PC are usually stored on the processor stack.

Interrupt latency: Delay between the time an interrupt request is received and the start of execution of
the interrupt service routine.

5.2.1 Interrupt Hardware

• An I/O device requests an interrupt by activating a bus-line called interrupt-request (IR).

• A single interrupt request line may be used to serve n devices as depicted. All devices are

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connected to the line via switches to ground. To request an interrupt, a device closes its
associated switch. Thus, if all interrupt-request signals INTR1 to INTRn are inactive, that is, if
all switches are open, the voltage on the interrupt-request line will be equal to Vdd.
• This is the inactive state of the line. Since the closing of one or more switches will cause the line
voltage to drop to 0, causing the interrupt request signal, INTR received by the processor to go
to 1.
• The value of INTR is the logical OR of the requests from individual devices, that is,
INTR = INTR1 + ………+INTRn

It is customary to use the complemented form, INTR, to name the interrupt-request signal on the
common line, because this signal is active when in the low-voltage state.

Fig 5.5: An equivalent circuit for an open-drain bus used to implement a common interrupt-request line

• The Fig 5.5 shows that special gates known as open-collector (for bipolar circuits) or open-drain
(for MOS circuits) are used to drive the INTR line. The output of an open-collector or an open-
drain gate is equivalent to a switch to ground that is open when the gate‟s input is in the 0 state
and closed when it is in the 1 state. Resistor R is called a pull-up resistor because it pulls the line
voltage up to the high-voltage state when the switches are open.

5.2.2 Enabling and Disabling Interrupts

• The facilities provided in a computer must give the programmer complete control over the events
that take place during program execution. The arrival of an interrupt request from an external

device causes the processor to suspend the execution of one program and start the execution of
another.
• Because interrupts can arrive at any time, they may alter the sequence of events from the
envisaged by the programmer. Hence, the interruption of program execution must be carefully
controlled.
• Let us consider in detail the specific case of a single interrupt request from one device. When a
device activates the interrupt-request signal, it keeps this signal activated until it learns that the

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processor has accepted its request.

• This means that the interrupt-request signal will be active during execution of the interrupt-
service routine, perhaps until an instruction is reached that accesses the device .

• This activated signal, if not deactivated, may lead to successive interruptions, causing the system
to enter into an infinite loop.

To prevent the system from entering into an infinite-loop because of interrupt, there are 3 possibilities

First Option

• The first possibility is to have the processor hardware ignore the interrupt-request line until the
execution of the first instruction of the interrupt-service routine has been completed.
• Then, by using an Interrupt-disable instruction as the first instruction in the interrupt-service
routine, the programmer can ensure that no further interruptions will occur until an Interrupt-
enable instruction is executed.
• Typically, the Interrupt-enable instruction will be the last instruction in the interrupt-service
routine before the Return-from-interrupt instruction. The processor must guarantee that
execution of the Return-from-interrupt instruction is completed before further interruption can
occur.

Second Option

• The second option is to have the processor automatically disable interrupts before starting the
execution of the ISR.
• After saving the contents of the PC and the processor status register (PS) on the stack, the
processor performs the equivalent of executing an Interrupt-disable instruction. It is often the
case that one bit in the PS register, called Interrupt-enable, indicates whether interrupts are
enabled.

Third option

• In the third option, the processor has a special interrupt-request line for which the interrupt-
handling circuit responds only to the leading edge of the signal. Such a line is said to be edge-
triggered. Processor will receive only one request hence there will not be multiple interruption.

Sequence of events involved in handling an interrupt-request from a single device is as follows:

1. The device raises an interrupt request.

2. The processor interrupts the program currently being executed.

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3. Interrupts are disabled by changing the control bits in the PS (except in the case of edge-
triggeredinterrupts).
4. The device is informed that its request has been recognized, and in response, it
deactivates theinterrupt-request signal.

5. The action requested by the interrupt is performed by the interrupt-service routine.

6. Interrupts are enabled and execution of the interrupted program is resumed.

5.3 Processor Examples

5.3.1 ARM Interrupt Structure
5.3.1.1 Introduction to ARM
• A collection of Reduced Instruction Set Computer (RISC) instruction set architectures for
computer processors that are tailored for different contexts is known as ARM (stylized in
lowercase as an arm; originally an abbreviation for Advanced RISC Machines.
• For light, portable, battery-powered devices like smartphones, laptops, and tablet computers, as
well as other embedded systems, ARM processors are preferred because they are less expensive,
consume less power, and generate less heat than their competitors.
• Modes of operation
ARM processor has 7 modes of operation.
➢ Switching between modes can be done manually through modifying the mode bits in the
CPSR register.
➢ Most application programs execute in user mode
➢ Non user modes (called privileged modes) are entered to serve interrupts or exceptions
➢ The system mode is special mode for accessing protected resources. It don‘t use registers used
by exception handlers, so it can‘t be corrupted by any exception handler error.

Fig 5.6: ARM Modes of operation

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• ARM register set

➢ ARM processor has 37 32-bit registers.

➢ 31 registers are general purpose registers.
➢ 6 registers are control registers
➢ Registers are named from R0 to R16 with some registers banked in different modes
➢ R13 is the stack pointer SP (Banked)
➢ R14 is subroutine link register LR (Banked)
➢ R15 is progrm counter PC
➢ R16 is current program status register CPSR (Banked)

Fig 5.7: Accessible registers in different modes of the ARM processor

5.3.1.2 Sources for Exceptions in ARM

• The term exception is used to refer to any event that causes an interruption
• ARM processor has five sources for exceptions, only two of which are external interrupt
request lines, IRQ(Interrupt ReQuest) and FIQ (Fast Interrupt reQuest).

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• There is one software interrupt instruction, SWI and two exceptions that may be caused by
abnormal conditions encountered during program execution. These exceptions are an
external abort following a bus error and an attempt to execute an undefined instruction.
• The Reset condition is included in this structure because it must override all other conditions
to bring the processor to a known starting condition.
• There are two abort conditions. Data Abort arises from an error in reading or writing data,
and Prefetch abort arises from an error when prefetching instructions from the memory.

Table 5.1 Interrupt Vector Addresses for ARM Processor

Address (Hex) Exception Mode entered
0 Reset Supervisor
4 Undefined instruction Undefined
8 Software interrupt Supervisor
C Abort during prefetch Abort
10 Abort during data Abort
14 Reserved
18 IRQ IRQ
1C FIQ FIQ

• All interrupts are disabled on startup for the ARM CPU until the initialization code turns them
on.
• The Processor Status Registers’ bit can be changed to enable or disable the interrupts (PSR or
CPSR where C stands for current).

Fig 5.8: CPSR Structure

• The CPSR also determines whether the processor is decoding Thumb instructions and the
processor mode (SVC, System, User, etc.).
• The application can read and write to the CPSR in its entirety when operating in privileged
mode, but it can only read the CPSR when operating in non-privileged mode.

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• The processor enters the appropriate interrupt or exception mode in response to an interrupt or
exception, which causes a portion of the main registers to be banked, swapped out, or replaced
with set mode registers.
• The interrupt masks’ ability to be enabled and disabled is controlled by bits. The two interrupt
inputs on the ARM processor can both be regarded as general-purpose interrupts. Interrupt
Request (IRQ) and Fast Interrupt Request are the names of the first and second, respectively
(FIQ)

• The regular sequential execution of instructions can be stopped by one of seven events on the
ARM processor. Since not all events are created equal, the processor must adopt a priority
strategy because these events may occur simultaneously.
• Exceptions are handled according to the following priority structure
1. Reset (Highest Priority)
2. Data Abort
3. FIQ
4. IRQ
5. Prefetch Abort
6. Undefined Instruction (Lowest Priority)

5.3.2 68000 Interrupt Structure

5.3.2.1 Introduction
• Motorola 68000 is a 16/32-bit complex instruction set computer (CISC) Microprocessor.
• It has 32-bit data and address registers. Externally the processor has 16-bit data bus and 24-bit
address bus, which limits the size of addressable memory to 16 MB.
• It uses a 16-bit data arithmetic logic unit (ALU). The Register architecture of 68000 is shown in
Fig 5.9.
• The data registers can be used to handle (8-bit) bytes, (16-bit) words, or 32-bit long words.
• There are seven general purpose Address registers (A0-A6). These registers can handle either 16-
bit word or 32-bit long word operands.
• A 16-bit status register is divided into two 8-bit bytes : The system byte and the user byte. Fig.
shows the bit assignments for the status register. The system byte of the status register contains
status information that is system-related. The user byte, on the other hand, contains the condition
code status bits (X, N, Z, V and C) which are instruction or program related. Bits in the system
byte of the Status register can only be altered when the MC 68000 is in the supervisor mode.

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Fig 5.9: Register Architecture of 68000

Fig 5.10: Status register bit pattern

• Bit 13 of the status register is the S-bit, which specifies whether the MC68000 is in the supervisor or
user mode of operation. When the bit is 1, the MC68000 is in the supervisor mode, and when it is 0
the microprocessor is in the user mode.
• The most significant bit of the status register is the Trace (T) flag. If this bit is 0 then the MC68000
operates normally. However, if the bit is 1, the microprocessor is in the trace mode of operation.
After each instruction is executed in the trace mode, a trap is forced so that a debugging program
can monitor the results of that instruction’s execution.

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5.3.2.2 Interrupt structure

• The 68000 has eight interrupt priority levels. The priority at which the processor is running at
any given time is encoded in three bits of the processor status word (I2, I1, I0) With level 0
being the lowest priority.

Table 5.2: Interrupt Levels

• Levels 1 through 6 are the mask-enabled levels.

• For example, if you set the mask to 100 then only levels 5, 6 and 7 will be enabled; interrupt
‘levels 1 through 4 are disabled.
• An interrupt request is accepted only if its priority is higher than that of the processor, with one
exception: An interrupt request at level 7 is always accepted. This is an edge triggered non
maskable interrupt.
• When the processor accepts an interrupt request, the priority level indicated in the Processor
Status (PS) register is automatically raised to that of the request before interrupt request routine is
executed. This requests of equal or lower priority are disabled, except for level-7 interrupts, which
are always enabled.
• The processor automatically saves the contents of the program counter and the processor status
word at the time of interruption. The PC is pushed on to the processor stack followed by the PS,
using register A7 as the stack pointer.
• A Return from interrupt instruction, called Return-from-exception(RTE), pops the top element of
the stack into the PS and pops the next element into the PC.
• The 68000 processor uses vectored interrupts. When it accepts an interrupt request, it obtains the
starting address of the interrupt-service routine from an interrupt vector stored in main memory.
• There are 256 interrupt vectors, numbered o through 255. Each vector consists of 32 bits that

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constitute the required starting address.

5.4 Direct Memory Access (DMA)

• A special control unit will be provided to allow the transfer of large block of data at high speed
directly between the external device and main memory, without continuous intervention by the
processor. This approach is called direct memory access (DMA). DMA transfers are performed
by a control circuit called the DMA Controller.

Fig 5.11: Registers in a DMA Interface

• To initiate the transfer of a block of words, the processor sends, are Starting address, Number of
words in the block and Direction of transfer.
• When a block of data is transferred, the DMA controller increment the memory address for
successive words and keep track of number of words and it also informs the processor by raising
an interrupt signal.

• While DMA control is taking place, the program requested the transfer cannot continue and the
processor can be used to execute another program. After DMA transfer is completed, the
processor returns to the program that requested the transfer.

• The above Fig 5.11 shows an example of the DMA controller registers that are accessed by the
processor to initiate transfer operations. Two registers are used for storing the Starting address
and the word count. The third register contains status and control flags. The R/W bit determines
the direction of the transfer. When

➢ R/W =1, DMA controller read data from memory to I/O device.
➢ R/W =0, DMA controller perform write operation.
➢ Done Flag=1, the controller has completed transferring a block of data and is ready to
receiveanother command.
➢ IE=1, it causes the controller to raise an interrupt (interrupt Enabled) after it has
completedtransferring the block of data.

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➢ IRQ=1, it indicates that the controller has requested an interrupt.

• A DMA controller connects a high speed network to the computer bus. The disk controller two
disks, also has DMA capability and it provides two DMA channels. To start a DMA transfer of a
block of data from main memory to one of the disks, the program write s the address and the
word count information into the registers of the corresponding channel of the disk controller.
When DMA transfer is completed, it will be recorded in status and control registers of the
DMA channel (i.e.) done bit=IRQ=IE=1.

5.4.1 Modes of DMA Transfer

5.4.1.1 Cycle Stealing:

• Memory accesses by the processor and the DMA controller are inter woven. Requests by DMA
devices for using the bus are always given higher priority than processor requests.
• Among different DMA devices, top priority is given to high-speed peripherals such as a disk, a
high-speed network interface, or a graphics display device.
• Since the processor originates most memory access cycles, the DMA controller can be said to
“steal” memory cycles from the processor. Hence, the interweaving technique is usually called
cycle stealing.

5.4.1.2 Burst Mode:

• The DMA controller may be given exclusive access to the main memory to transfer a block of
data without interruption. This is known as Burst/Block Mode.

5.4.2 Use of DMA Controller

• An example of computer system is given in Fig 5.12, showing how DMA controllers may be
used.

• A DMA controller connects a high speed network to the computer bus. The disk controller,
which controls two disks, also has DMA capability and provides two DMA channels. It can
perform two independent DMA operations, as if each disk had its own DMA controller.

• The registers needed to store the memory address, the word count, and so on are duplicated, so
that one set can be used in each device.

• To start a DMA transfer of a block of data from the main memory to one of the disks, a program
writes the address and word count information into the registers of the corresponding channel of
the disk controller. It also provides the disk controller with information to identify the data for

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future retrieval.

• The DMA controller proceeds independently to implement the specified operation. When the
DMA transfer is completed, the done bit is set. At the same time IE bit is set, the controller sends
an interrupt request to the processor and sets the IRQ bit.

• The status register can also be used to record other information, such as whether the transfer took
place correctly or errors occurred.

Fig 5.12: Use of DMA controllers in a computer system

5.4.3 Bus Arbitration

• The device that is allowed to initiate data transfers on the bus at any given time is called the bus
master.

• Bus Arbitration is the process by which the next device to become the bus master is selected
and the bus mastership istransferred to it.

There are 2 approaches to bus arbitration. They are,

1. Centralized arbitration (A single bus arbiter performs arbitration)

2. Distributed arbitration (all devices participate in the selection of next bus master).

5.4.3.1 Centralized Arbitration:

• Here the processor is the bus master and it may grants bus mastership to one of its DMA
controller. A DMA controller indicates that it needs to become the bus master by activating the

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̅̅̅̅) which is an open drain line. The signal on Bus Request is the logical OR
Bus Request line (𝐵𝑅
of the bus request from all devices connected to it.
• When Bus Request is activated, the processor activates the Bus Grant Signal (BG1) and indicates
the DMA controller that they may use the bus when it becomes free. This signal is connected to
all DMA controllers using a daisy chain arrangement.
• If DMA controller 1 requests the bus, it blocks the propagation of Grant Signal to other devices
and it indicates to all devices that it is using the bus by activating open collector line, Bus Busy
(BBSY). Otherwise it passes the grant downstream by asserting BG2.

Fig 5.13: A simple arrangement for bus arbitration using a daisy chain

• The timing diagram shows the sequence of events for the devices connected to the processor is
shown in Fig 5.14. DMA Controller 2 requests and acquires bus mastership and later releases the
bus. During its tenure as bus master, it may perform one or more data transfer operations,
depending on whether it is operating in the cycle stealing or block mode. After it releases the
bus, the processor resumes bus mastership.

Fig 5.14: Sequence of signals during transfer of bus mastership for the devices

5.4.3.2 Distributed Arbitration:

• Distributed arbitration means that all devices waiting to use the bus have equal responsibility in
carrying out the arbitration process, without using a central arbiter.

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• Each device on the bus is assigned a 4 bit Identification number. When one or more devices
request the bus, they assert the ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑆𝑡𝑎𝑟𝑡 − 𝐴𝑟𝑏𝑖𝑡𝑟𝑎𝑡𝑖𝑜𝑛 signal and place their 4 bit ID number on
four open collector lines, ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵0 to ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵3
• A winner is selected as a result of the interaction among the sig.nals transmitted over these lines.
The net outcome is that the code on the four lines represents the request that has the highest ID
number. The drivers are of open collector type.
• Hence, if the input to one driver is equal to 1, the input to another driver connected to the same
bus line is equal to “0” the bus will be in low-voltage state.
Example:

• Assume two devices A and B have their ID 5 (0101), 6(0110) and their code is 0111. Each
device compares the pattern on the arbitration line to its own ID, starting from most significant
bit (MSB).
• If it detects a difference at any bit position, it disables the drivers at that bit position and for all
lower-order bits. It does this by placing “0” at the input of these drivers. In our example, device
“A” detects a difference in line ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵1.

Fig 5.15: A distributed arbitration scheme

• Hence it disables the drivers on lines ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵1 and ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵0. This causes the pattern on the
arbitrationline to change to 0110 which means that “B” has won the contention.
• It has the advantage of offering higher reliability, because operation of the bus is not dependent
on any single device.

5.5 Buses
• A bus protocol is the set of rules that govern the behavior of various devices connected to the

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bus as to when to place information on the bus, assert control signals, and so on. The bus lines
used for transferring data is grouped into 3 types. They are Address line, Data line and Control
line.
• Control signals Specifies that whether read or write operation has to perform and also carries
timing information. They specify the time at which the processor & I/O devices place the data
onthe bus and receive the data from the bus.
• During data transfer operation, one device plays the role of a “Master”. Master device initiates
the data transfer by issuing read or write command on the bus. Hence it is also called as
“Initiator”. The device addressed by the master is called as Slave or Target.

• There are 2 types of buses. They are Synchronous Bus and Asynchronous Bus.

5.5.1 Synchronous Bus

• In synchronous bus, all devices derive timing information from a common clock line. Equally
spaced pulses on this line define equal time intervals. In the simplest form of a synchronous
bus, each of these intervals constitutes a bus cycle during which one data transfer can take
place. Such scheme is shown in Fig 5.16.

Fig 5.16: Timing of an input transfer on a synchronous bus

5.5.1.1 Sequence of events during a read operation:

• At time t0, the master places the device address on the address lines and sends an appropriate
command on the control lines. In this case, the command will indicate an input operation and
specify the length of the operand to be read.

• The clock pulse width t1 – t0 must be longer than the maximum delay between devices
connected to the bus. The clock pulse width should be long to allow the devices to decode the
address and control signals so that the addressed device can respond at time t1. The slaves take no
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action or place any data on the bus before t1.

• The information on the bus is unreliable during the period t0 – t1 because signals are changing
state. The addressed slave places data on the data lines at time t1.

• The Fig 5.17 gives more realistic picture of what happens in practice. It shows two views of the
signal except the clock.

• One view shows the signal seen by the master and the other is seen by the slave. T The dthe
master sends the address and command signals on the rising edge at the beginning of clock
period (t0). These signals do not actually appear on the bus until tAM. A while later, at tAS the
signals reach the slave. The slave decodes the address and at t1, it sends the requested data. The
data signals do not appear on the bus until tDS . They travel toward the master and arrive at tDM .
• At t2, the master loads the data into its input buffer. Hence the period t2 - tDM is the setup time
for the masters input buffer. The data must be continued to be valid after t2, for a period equal to
the hold time of that buffers.

Fig 5.17: A detailed timing diagram for the input transfer

Demerits:

1. The device does not respond.

2. The error will not be detected.

5.5.1.2 Multiple Cycle Transfer

• During, clock cycle1, the master sends address and command information. On the bus requesting
a “read” operation. The slave receives this information and decodes it. At the active edge of the
clock (i.e.) the beginning of clock cycel2, it makes accession to respond immediately.

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• The data become ready and are placed in the bus at clock cycle3. At the same times, the slave
asserts a control signal called “slave-ready”. The master device has been waiting for this signal,
strobes, and the data to its input buffer at the end of clock cycle3.
• The bus transfer operation is now complete & the master sends a new address to start a new
transfer in clock cycle4. The „slave-ready‟ signal is an acknowledgement form the slave to the
master confirming that valid data has been sent.

Fig 5.18: An input transfer using multiple clock cycles

5.5.2 Asynchronous Bus

• An alternate scheme for controlling data transfer on the bus is based on the use of
“handshake” between Master and the Slave. The common clock is replaced by two timing
control lines. They are Master–ready and Slave ready.

Fig 5.19: Handshake control of data transfer during an input operation

• The handshake protocol proceeds as follows:

➢ At t0: The master places the address and command information on the bus and all devices
on the bus begin to decode the information.

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➢ At t1: The master sets the Master ready line to 1 to inform the I/O devices that the address
and command information is ready.

▪ The delay t1 – t0 is intended to allow for any skew that may occur on the bus.

▪ The skew occurs when two signals simultaneously transmitted from one source
arrive at the destination at different time.
▪ Thus to guarantee that the Master ready signal does not arrive at any device a head
of the address and command information the delay t1 – t0 should be larger than the
maximum possible bus skew.
➢ At t2: The selected slave having decoded the address and command information performs
the required i/p operation by placing the data from its data register on the data lines. At the
same time, it sets the “slave – Ready” signal to 1.

➢ At t3:The slave ready signal arrives at the master indicating that the input data are available
on the bus.

➢ At t4: The master removes the address and command information on the bus. The delay
between t3 and t4 is again intended to allow for bus skew. Erroneous addressing may take
place if the address, as seen by some device on the bus, starts to change while the master –
ready signal is still equal to 1.

➢ At t5: When the device interface receives the 1 to 0 transitions of the Master–ready signal,
it removes the data and the slave – ready signal from the bus. This completes the input
transfer.

• In Fig 5.20, the master place the output data on the data lines and at the same time it transmits
the address and command information. The selected slave strobes the data to its output buffer
when it receives the Master ready signal and it indicates this by setting the slave–ready signal to
1. At time t0 to t1 and from t3 to t4, the Master compensates for bus.

• In the above and below timing diagrams, it is assumed that the master compensates for bus skew
and address decoding delay. It introduces the delays from t0 to t1 and from t3 to t4 for this
purpose. If this delay provides sufficient time for the I/O device interface to decode the address,
the interface circuit can use the Master-ready signal directly to gate other signals to or from the
bus,

• A change of state is one signal is followed by a change is the other signal. Hence this scheme is
called asFull Handshake. It provides the higher degree of flexibility and reliability.

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Fig 5.20: Handshake control of data transfer during an output operation

Advantages of asynchronous bus:

• Eliminates the need for synchronization between the sender and the receiver.
• Can accommodate varying delays automatically, using the Slave-ready signal.

Disadvantages of asynchronous bus:

▪ Data transfer rate with full handshake is limited by two-round trip delays.
▪ A data transfer using a synchronous bus involves only one round trip delay, and hence a
synchronous bus can achieve faster rates.

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Assignment cum Tutorial Questions
5.1 Accessing I/O Devices

Objective Questions

1. Which of the following is correct in I/O mapped I/O [ ]

a) The memory and I/0 address-spaces are different

b) The memory and I/0 address-spaces are same

c) None of the above

2. Which of the following is correct in Memory mapped I/O [ ]

a) The memory and I/0 address-spaces are different

b) The memory and I/0 address-spaces are same

c) None of the above

3. The bus used in I/O devices consists of the three sets of lines used to carry [ ]

a) Address, data and control signals b) Address and data

c) Data and control signals d) None of the above

4. The usual BUS structure used to connect the I/O devices is ___________ [ ]
a) Star BUS structure b) Multiple BUS structure
c) Single BUS structure d) Node to Node BUS structure

5. In memory-mapped I/O ____________ [ ]

a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation

6. The method of accessing the I/O devices by repeatedly checking the status [ ]
flags is ___________
a) Program-controlled I/O b) Memory-mapped I/O
c) I/O mapped d) None of the mentioned

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Descriptive Questions

S.No. Name of the question BL

1. How to access I/O devices and explain in detail. L2

2. Differentiate between Memory Mapped and I/O mapped I/O. L2

5.2 Interrupts
Objective Questions

1. An I/O device requests an interrupt by activating a bus-line called [ ]

a) Interrupt-routine
b) Interrupt-request
c) None of the above

2. The method of synchronizing the processor with the I/O device in which the [ ]
device sends a signal when it is ready is?
a) Exceptions b) Signal handling
c) Interrupts d) DMA

3. The interrupt-request line is a part of the ___________ [ ]

a) Data line b) Control line
c) Address line d) None of the mentioned

4. The signal sent to the device from the processor to the device after receiving [ ]
an interrupt is ___________
a) Interrupt-acknowledge b) Return signal
c) Service signal d) Permission signal

5. The time between the receiver of an interrupt and its service is ______ [ ]
a) Interrupt delay b) Interrupt latency
c) Cycle time d) Switching time

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6. An interrupt that can be temporarily ignored is ___________ [ ]

a) Vectored interrupt b) Non-maskable interrupt
c) Maskable interrupt d) High priority interrupt

An interrupt breaks the execution of instructions and diverts its execution to

7. [ ]
a) Interrupt service routine b) Counter word register
c) Execution unit d) control unit

Descriptive Questions

S.No. Name of the question BL

1. Explain the Interrupt hardware in detail. L2

2. Explain about the enabling and disabling interrupts. L2

5.3 Processor examples

Objective Questions

1. How many interrupt levels are supported in the MC68000? [ ]

a) 2 b) 3 c) 4 d) 7

2. ARM stands for _____________ [ ]

a) Advanced Rate Machines b) Advanced RISC Machines
c) Artificial Running Machines d) Aviary Running Machines

3. RISC stands for _________ [ ]

a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer

4. The ARM core uses ________ architecture. [ ]

a) RISC b) CISC c) both d) none

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Descriptive Questions

S.No. Name of the question BL

1. Explain the ARM Interrupt Structure. L2

2. Explain the 68000 Interrupt structure L2

5.4 DMA

Objective Questions
1. The DMA transfers are performed by a control circuit called as __________ [ ]
a) Device interface b) DMA controller
c) Data controller d) Over looker

2. After the completion of the DMA transfer, the processor is notified by ____ [ ]
a) Acknowledge signal b) Interrupt signal
c) WMFC signal d) None of the mentioned

3. The DMA controller has _______ registers. [ ]

a) 4 b) 2 c) 3 d) 1

4. When the R/W bit of the status register of the DMA controller is set to 1. [ ]
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned

5. Can a single DMA controller perform operations on two different disks [ ]

simultaneously?
a) True b) False

6. The technique whereby the DMA controller steals the access cycles of the [ ]
processor to operate is called __________
a) Fast conning b) Memory Con
c) Cycle stealing d) Memory stealing

7. The technique where the controller is given complete access to main memory [ ]
is __________
a) Cycle stealing b) Memory stealing

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c) Memory Con d) Burst mode

8. To overcome the conflict over the possession of the BUS we use ______ [ ]
a) Optimizers b) BUS arbitrators
c) Multiple BUS structure d) None of the mentioned

Descriptive Questions

S.No. Name of the question BL

1. With a neat sketch explain the registers in DMA transfer. L2

2. Explain the Bus arbitration-centralized and distributed. L2

3. How to access Main memory by processor and DMA? Explain different modes. L3

5.5 Buses

Objective questions

1. The primary function of the BUS is __________ [ ]

a) To connect the various devices to the CPU
b) To provide a path for communication between the processor and other
devices
c) To facilitate data transfer between various devices
d) All of the mentioned

2. The classification of BUSes into synchronous and asynchronous is based on [ ]

__________
a) The devices connected to them b) The type of data transfer
c) The Timing of data transfers d) None of the mentioned

3. In synchronous BUS, the devices get the timing signals from __________ [ ]
a) Timing generator in the device b) A common clock line
c) Timing signals are not used at all d) None of the mentioned

4. The delays caused in the switching of the timing signals is due to [ ]

__________
a) Memory access time b) WMFC

c) Propagation delay d) Processor delay

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5. The transmission on the asynchronous BUS is also called _____ [ ]
a) Switch mode transmission b) Variable transfer
c) Bulk transfer d) Hand-Shake transmission

Descriptive Questions

S.No. Name of the question BL

1. What is BUS? Explain different types of BUS transfers. L2

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