Decoders- is a combinational circuit that converts binary information from the n coded inputs to a

maximum of 2n outputs,

3-to-8-line decoder

Truth table for 3-to-8-line decoder

Inputs Outputs
X Y Z D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

2-to-4-line Decoders
 E A1 A2 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 x x 1 1 1 1

D0 = E A 1 A 0 D2 = E A 1 A 0

D1 = E A 1 A 0 D3 = E A 1 A 0

Decoder Expansion

A 3-to-8 decoder constructed with two 2-to-4 decoders

Decoder implementation of binary adder:

S(x , y , z) = ∑ m(1,2,4,7 )
C (x , y , z ) = ∑ m(3,5,6,7)

Encoders

-an encoder is a digital function that perform the inverse operation of a decoder. An encoder has 2 n (or
fewer) input lines and n output lines. The output lines generate the binary code corresponding to the
input value.

Octal-to-binary encoder

Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
A 0 = D1 + D 3 + D5 + D7
A 1 = D2 + D3 + D6 + D7
A 2 = D4 + D 5 + D6 + D7
Priority Encoders
- is a combinational circuit that implements a priority function. The operation of the priority encoder is
such that if two or more inputs are equal to 1 at the same time, the input having the highest priority
takes precedence.

Inputs Outputs
D3 D2 D1 D0 A1 A0
0 0 0 0 x x
0 0 0 1 0 0
0 0 1 x 0 1
0 1 x x 1 0
1 x x x 1 1

A 1 = D2 + D3

A 0 = D3 + D2 D 1

Multiplexers

-combinational circuit that selects binary information from one of many input lines and directs the
information to a single output line. The selection of a particular input line is controlled by a set of
input variables called “Selection Inputs”. Normally , there are 2 n input lines and n selection inputs
whose bit combinations determine which input is selected.
4-to-1-line multiplexer

Function table

S1 S0 Y
0 0 D0
0 0 D1
1 0 D2
1 1 D3
Function table

E Selection Inputs Output

S1 S0 Y
0 x x 0
1 0 0 D0
1 0 1 D1
1 1 0 D2
1 1 1 D3
Demultiplexer

Function table

Input Selection Inputs Output

S1 S0
D 0 0 Y0 = D
D 0 1 Y1 = D
D 1 0 Y2 = D
D 1 1 Y3 = D
Programmable array logic (PAL) has a programmable AND array at the input and a fixed OR array at
the output. The number of programmable AND gates in PAL architecture are smaller than the number
of minterms. The OR array is fixed and the AND outputs are divided between OR gates.

A programmable logic array (PLA) is a kind of programmable logic device used to implement
combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set
of programmable OR gate planes, which can then be conditionally complemented to produce an output.
It has 2N AND gates for N input variables, and for M outputs from PLA, there should be M OR gates,
each with programmable inputs from all of the AND gates. This layout allows for many logic functions
to be synthesized in the sum of products canonical forms.

PLAs differ from programmable array logic devices (PALs and GALs) in that both the AND and OR
gate planes are programmable