AMERICAN INTERNATIONAL

UNIVERSITY-BANGLADESH
Faculty of Engineering

Implementation of asynchronous and synchronous counters using

Assignment Title:
flip-flops
Experiment No: 07 Date of Submission: 23 September 2024
Course Title: Digital Logic and Circuit Lab
Course Code: COE3103 Section: F
DR. TANBIR IBNE
Semester: Summer 2023-24 Course Teacher:
ANOWAR
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* Student(s) must complete all details except the faculty use part.
** Please submit all assignments to your course teacher or the office of the concerned teacher.

Group Name/No.: 07

No Name ID Program

FORMTEX
1 FORMTEXT DIP KHASTAGIR BSc [CSE]
T 23-
50346-1

2 FORMTEXT FOYSAL MUNSY FORMTEX BSc [CSE]

T 22-47225-1
22-
3 FORMTEXT MD ARMAN ISLAM BSc [CSE]
49141-3

4 FORMTEXT ABU NAYEM MD. ARMAN FORMTEX BSc [CSE]

T 22-47249-1
5 ABRAR SHAKIL 23-46257-1 BSc [CSE]
6 MAHNAZ TABASSUM ORPITA 22-46024-1 BSc [CSE]

Faculty use only

FACULTYCOMMENTS

Marks Obtained

Total Marks
Theory:
Asynchronous and synchronous counters are two types of digital counters used in sequential logic
circuits, and both can be implemented using flip-flops. These counters are primarily used to count
events, time intervals, or the number of clock pulses. The main difference between them is how the
clock signal is propagated through the flip-flops.
Asynchronous Counter (Ripple Counter): An asynchronous counter is a type of counter where the
clock input is applied only to the first flip-flop, and the output of each flip-flop is used as the clock
input for the next flip-flop in the sequence. This type of counter is called a ripple counter because the
clock signal ripples through the flip-flops, resulting in propagation delay.
Implementation with Flip-Flops: Each flip-flop is typically a T flip-flop (or a JK flip-flop with both
inputs tied to logic 1). The first flip-flop toggles on every clock pulse, while the subsequent flip-flops
toggle when the preceding flip-flop’s output changes from 1 to 0 (falling edge of the signal).
Synchronous Counter: In a synchronous counter, all the flip-flops are clocked simultaneously with
the same clock signal. This eliminates the propagation delay found in asynchronous counters, making
the synchronous counter faster and more efficient for higher-speed applications.

Implementation with Flip-Flops: T flip-flops are typically used, or JK flip-flops** with both inputs
tied to logic 1. Instead of cascading the clock inputs, a common clock signal is applied to all flip-flops
simultaneously. The toggling of each flip-flop is controlled by logic that depends on the states of the
previous flip-flops.
Pin Configuration of 74LS76 and 7408:
Apparatus:
 IC 74LS76 (JK Flip Flop)
 IC 7408 (AND Gate)
 LED Lamps or Display
 Trainer Board
 Oscilloscope
 Connecting Wires

Experimental Procedure:
3 Bit Asynchronous Counter:
1. The circuit was designed on the bread board as shown in Figure 9.5.
2. The trainer board’s signal generator was used for the clock pulse and power
supply for biasing the Flip Flops.
3. The output was also viewed in oscilloscope; outputs were connected to the
different channels of the oscilloscope.
4. The output results were observed, results were recorded and also took some
pictures for our lab report.

3 Bit Synchronous Counter:

1. The circuit was designed on the bread board as shown in figure.
2. The trainer board’s signal generator was used for the clock pulse and power
supply for biasing the Flip Flops.
3. The output was also viewed in oscilloscope; outputs were connected to the
different channels of the oscilloscope.
4. The output results were observed & recorded and also took some pictures
for our lab report.
Lab Images:

Simulation and Measurement:

3 Bit Asynchronous Counter
3 Bit Synchronous Counter
Question with answers:
4 Bit Asynchronous Up Counter
 4 Bit Synchronous Up Counter

Bit Asynchronous Down Counter

 MOD 10 Synchronous Up Counter

Discussion: In asynchronous counters, each flip-flop's clock input is connected to the output of
the preceding flip-flop. This creates a ripple effect, where the state of the counter changes one
flip-flop at a time. Simple design and implementation. Propagation delays between flip-flops
can lead to glitches and inaccurate counting. This becomes more pronounced with larger
counters. In synchronous counters, all flip-flops are clocked simultaneously by a common clock
signal. The state of each flip-flop is determined by a combinatorial logic circuit that takes the
current state and the input signal as inputs. Faster and more accurate than asynchronous
counters, especially for larger counts. No propagation delays between flip-flops. More complex
design and implementation, requiring additional logic for state control.
Conclusion: Asynchronous counters are suitable for applications where speed and accuracy are
not critical, and simplicity is a priority. Synchronous counters are preferred in applications
where high-speed and accurate counting are essential, such as digital clocks, frequency counters,
and data transmission systems.
Lab Performance:
Reference: 1. Thomas L. Floyd, “Digital Fundamentals”, Ninth Edition.
2. https://www.geeksforgeeks.org/differences-between-
synchronous-and- asynchronous-counter/
3. https://www.shiksha.com/online-courses/articles/difference-
between-synchronous- and-asynchronous-counter/
4. https://www.geeksforgeeks.org/design-mod-n-synchronous-counter/