Analog CMOS IC Lab Report

(22ECP218)

Presented By: harsh aggarwal (2023UEC1024)

Presented To: Dr. Menka Yadav

Department of Electronics and Communication Engineering

MNIT Jaipur

April 21, 2025

 Contents

Sr.No. Experiment Experiment Date Submission Date Page No.

1. To study I/O characteristics of 20 JAN 2025 17 FEB 2025 2
NMOS
2. To study I/O characteristics of 27 JAN 2025 17 FEB 2025 6
PMOS
3. Implementation of NMOS inverter 03 FEB 2025 28 FEB 2025 10
with resistive load
4. Implementation of PMOS inverter 10 FEB 2025 28 FEB 2025 14
with resistive load

1
 Experiment - 1
0.1 Objective
To study I/O characteristics of NMOS transistor in Cadence.

0.2 Software Required

Cadence

0.3 Theoretical Foundations of NMOS Transistors

• Fundamental Composition:

– The core structure of an NMOS transistor comprises a channel constructed

from N-type semiconductor material, situated between the source and drain
terminals.
– The substrate, in this case, is typically P-type.
– The gate terminal is insulated from the channel by a thin dielectric layer,
commonly silicon dioxide.

• Operational Mechanism:

– Application of a positive voltage to the gate induces the concentration of neg-

ative charge carriers (electrons) near the oxide boundary.
– This leads to the formation of a depletion region.
– Incrementing the gate-source voltage (VGS ) results in an expansion of the de-
pletion region’s width.
– Once VGS surpasses a critical threshold voltage (VT H ), electrons accumulate
sufficiently to create an N-type inversion layer, establishing a conductive path-
way between the source and drain.
– This inversion enables the flow of electrons from the source to the drain, man-
ifesting as a current from drain to source, thereby activating the transistor.

• Operational States:

– Cutoff State: If the gate-source voltage (VGS ) is less than or equal to the
threshold voltage (VT H ), the NMOS transistor is in a non-conductive state
(OFF).
– Linear (Ohmic) State: When VGS > VT H and the drain-source voltage
(VDS ) is less than or equal to VGS − VT H , the NMOS transistor operates in the
linear or triode region, where drain current (ID ) is proportional to VDS .
– Saturation State: If VGS > VT H and VDS > VGS − VT H , the NMOS transis-
tor operates in the saturation region, where drain current becomes relatively
independent of VDS .
– Zero Drain-Source Voltage State: When VGS > VT H and VDS = 0, the
NMOS transistor is in an ON state, but no drain current (ID = 0) flows.

2
0.4 Circuit Diagram

Figure 1: Circuit Diagram for NMOS

3
0.5 Procedure
1. Begin by navigating to your project directory, specifically the “Work Cadence”
folder.

2. Within this folder, initiate a terminal session by right-clicking and selecting “Open
in Terminal”.

3. In the terminal, switch to the C Shell environment by typing csh and pressing
Enter.

4. Load the necessary environment configurations by executing source CSHRC and

pressing Enter.

5. Launch the Virtuoso software using the command virtuoso & followed by Enter.
The ampersand allows Virtuoso to run in the background.

6. Inside the Virtuoso CIW, create a new library via “File → New → Library”.

7. Provide a descriptive library name (e.g., my circuit), select “Attach to an existing

technology library”, and confirm with “OK”.

8. Choose the appropriate technology library, either gpdk180 or ts018 scl, and click
“OK”.

9. Create a new cell view within the library using “File → New → Cell View”.

10. Select your newly created library (e.g., my circuit) from the Library dropdown.

11. Assign a cell name and click “OK” to open the Virtuoso Schematic Editor.

12. Add instances by pressing “i” and clicking “Browse”.

13. Select the technology library, choose either NMOS or PMOS, and place it in the
schematic editor.

14. Exit the instance placement mode by pressing “ESC”.

15. Repeat the instance addition process for any additional components.

16. Incorporate voltage sources and ground by pressing “i”, clicking “Browse”, and
selecting from the “analogLib” library (e.g., vdc, vpulse, gnd).

17. Connect components by pressing “w” and clicking on the respective terminals.

18. Save your design using the “Check and Save” function.

19. Modify component parameters by selecting a component, pressing “q”, and adjust-
ing the values (e.g., set the DC voltage of a voltage source to 1.8V).

20. Launch the Analog Design Environment (ADE L) by navigating to “Launch →

ADE L”.

21. Add the technology library for gpdk180 or ts180scl in the ADE L window via
“Setup → Model Library” (if not already added).

4
 22. Configure a DC analysis in ADE L by selecting “Analysis → Choose → DC”.

23. Initiate a component parameter sweep by choosing “Component Parameter → Se-

lect Component”.

24. Select the input voltage source on the schematic, then choose “DC → OK”.

25. Define the DC sweep range in ADE L by entering “start: 0, stop: 1.8 → OK”.

26. Select outputs for plotting via “Outputs → To Be Plotted → Select on Design”.

27. Click on the desired wires or nodes to plot voltage or current.

28. Execute the DC simulation by clicking the “Run” option in ADE L and examine
the results.

29. Change the input DC source to a pulse source, vpulse, from “analogLib”.

30. Adjust the properties of vpulse, such as delay, period, and width, as required.

31. Save the updated design.

32. Configure a transient analysis in ADE L by selecting “Analysis → Trans → Stop

Time → 50n” (or a different stop time).

33. Select outputs and inputs for plotting in ADE L via “Output → To Be Plotted →
Select on Design”.

34. Click on the desired output and input wires.

35. Run the transient simulation in ADE L and analyze the output plots.

0.6 Observations

Figure 2: ID v/s VGS graph for VDS = 1.8V Figure 3: ID v/s VDS graph for VGS = 1.8V

5
0.7 Result
The I/O characteristics of NMOS were successfully observed, analyzed and plotted in
cadence and SciDAVis software.

0.8 Conclusion
This experiment provided an understanding of the behavior of N channel MOSFETs
(NMOS) in different regions of operation like triode , saturation , cutoff by Output
characteristics and on - off of MOSFETS by Input characteristics.

6
 Experiment - 2
0.9 Objective
To study I/O characteristics of PMOS transistor in Cadence.

0.10 Software Required

Cadence

0.11 Theoretical Background of PMOS Transistors

• Fundamental Structure:

– The core of a PMOS transistor consists of a channel formed from P-type

semiconductor material, positioned between the source and drain terminals.
– Typically, the substrate material is N-type.
– An insulating layer, often silicon dioxide, isolates the gate terminal from the
channel.

• Operational Principles:

– Applying a negative voltage to the gate induces the accumulation of positive

charge carriers (holes) near the oxide interface.
– This leads to the formation of a depletion region.
– Progressively decreasing the gate-source voltage (VGS ) expands the width of
this depletion region.
– When VGS reaches a critical threshold voltage (VT H ), holes begin to accumulate
in sufficient quantity to create a P-type inversion layer, effectively forming a
channel between the source and drain.
– This inversion facilitates the flow of holes from the source to the drain, resulting
in a current flow and activating the transistor.

• Operational Regimes:

– Cut-off Region: If the absolute value of the gate-source voltage, |VGS |, is

less than or equal to the absolute value of the threshold voltage, |VT H |, the
PMOS transistor is in a non-conducting state (OFF).
– Linear (Ohmic) Region: When |VGS | > |VT H | and the absolute value of the
drain-source voltage, |VDS |, is less than or equal to |VGS − VT H |, the PMOS
transistor operates in the linear or triode region. In this region, the drain
current (ID ) is proportional to VDS .
– Saturation Region: If |VGS | > |VT H | and |VDS | > |VGS − VT H |, the PMOS
transistor operates in the saturation region. In this region, the drain current
becomes relatively independent of VDS .
– Zero Drain-Source Voltage: When |VGS | > |VT H | and |VDS | = 0, the
PMOS transistor is in an ON state, but no drain current (ID = 0) flows.

7
0.12 Circuit Diagram

Figure 1: Circuit Diagram for PMOS

8
0.13 Procedure
1. Setup and Library Creation: Follow steps 1-11 from the previous instructions
to create a library, a cell view, and open the Virtuoso Schematic Editor. Place a
PMOS transistor in your schematic.

2. Circuit Setup for IV Characteristics:

(a) Add a DC voltage source (vdc) for the gate-source voltage (VGS).
(b) Add another DC voltage source (vdc) for the drain-source voltage (VDS).
(c) Connect the sources and the PMOS transistor as shown below.
(d) Add a ground (gnd) connection.

3. ADE L Setup: Launch ADE L (“Launch → ADE L”). Add the necessary model
libraries.

4. DC Analysis Setup (VDS Sweep):

(a) Go to “Analysis → Choose → DC”.

(b) Set the VDS source as the sweep variable (“Component Parameter → Select
Component”).
(c) Define the VDS sweep range (e.g., start: 0, stop: -1.8). Note the negative sign
for PMOS.
(d) Set the VGS source to a fixed value (e.g., -1.8V for the first curve).

5. Output Selection:

(a) Go to “Outputs → To Be Plotted → Select on Design”.

(b) Select the drain current of the PMOS transistor.

6. Run Simulation and Plot:

(a) Run the simulation.

(b) Observe the ID vs. VDS curve.

7. Repeat for Different VGS Values:

(a) Change the VGS value in ADE L.

(b) Re-run the simulation.
(c) Repeat this process for multiple VGS values to generate a family of curves.

8. Analyze the Results: Observe the resulting IV characteristics, including the

linear and saturation regions of the PMOS transistor.

0.14 Observations
0.15 Result
The I/O characteristics of PMOS were successfully observed, analyzed and plotted in
cadence and SciDAVis software.

9
Figure 2: ID v/s VGS graph for VDS = 1.8V

Figure 3: ID v/s VDS graph for VGS = 1.8V

0.16 Conclusion
This experiment provided an understanding of the behavior of N channel MOSFETs
(PMOS) in different regions of operation like triode , saturation , cutoff by Output
characteristics and on - off of MOSFETS by Input characteristics.

10
Experiment - 3: Common Source Amplifier Analysis
0.17 Objective
To perform direct current (DC), alternating current (AC), and transient analysis of a
Common Source (CS) MOSFET amplifier utilizing simulation tools.

0.18 Materials and Software

Cadence Virtuoso software suite.

0.19 Schematic Representation

Figure 4: Common Source Amplifier Schematic

0.20 Theoretical Framework

0.20.1 Circuit Functionality
The Common Source amplifier is characterized by its source terminal being common to
both the input and output signal paths. The input signal is applied to the gate, and the
amplified output is derived from the drain terminal.

11
0.20.2 DC Operating Point Analysis
The quiescent operating point of the CS amplifier is determined by the MOSFET’s trans-
fer characteristics and the biasing network. For a MOSFET operating in saturation, the
drain current (ID ) is expressed as:

ID = K(VGS − VT H )2
where K = 21 µn Cox W
L
.

0.20.3 AC Signal Analysis

The small-signal equivalent model is utilized to evaluate the amplifier’s gain, input, and
output impedances.

0.20.4 Small-Signal Equivalent Circuit

For AC analysis, the MOSFET is modeled using:

• Transconductance (gm ): gm = ∂ID

∂VGS
= 2K(VGS − VT H )

• Output Resistance (ro ): ro = 1

λID

• Voltage Gain (Av ): Av = Vout

Vin
′
= −gm RD ′
where RD = RD ∥ ro

0.20.5 Input and Output Impedance

• Input Impedance (Zin ): For an ideal MOSFET, Zin is infinite. In practice, Zin ≈
RG .

• Output Impedance (Zout ): Zout = RD ∥ ro

0.21 Procedure
1. Access the project directory, ”Work Cadence.”

2. Open a terminal within the directory.

3. Initiate the C shell: csh → Enter.

4. Load environment configurations: source CSHRC → Enter.

5. Launch Virtuoso: virtuoso & → Enter.

6. Create a new library: File → New → Library.

7. Define library parameters and attach to technology library.

8. Select the appropriate technology library.

9. Create a new cell view: File → New → Cell View.

10. Select the created library and define a cell name.

12
 11. Place MOSFET and other components using the instance browser.

12. Connect components using wires.

13. Save the schematic.

14. Adjust component parameters as needed.

15. Launch ADE L: Launch → ADE L.

16. Add model libraries.

17. Perform DC analysis: Analysis → Choose → DC.

18. Configure DC sweep parameters.

19. Select outputs for plotting.

20. Run DC simulation and analyze results.

21. Change input source to pulse for transient analysis.

22. Configure pulse parameters.

23. Perform transient analysis: Analysis → Trans.

24. Select inputs and outputs for transient plotting.

25. Run transient simulation.

0.22 Computational Analysis

Given:

|Av | = 10
Vth = 0.49 V
L = 180 nm
ID = 50 µA
K = 300 µA/V2
VDD = 1.8 V
VO = 0.9 V

0.22.1 Output Resistance Calculation

VDD − VDS 1.8 V − 0.9 V
Ro = = = 18 kΩ
ID 50 µA

13
0.22.2 Transistor Width Calculation
Given VGS = 0.67 V,
VGS − Vth = 0.67 V − 0.49 V = 0.18 V
1 W
ID = K (VGS − Vth )2
2 L
1 W
50 µA = × 300 µA/V2 × × (0.18 V)2
2 L
W
≈ 10.29
L
W ≈ 10.29 × 180 nm ≈ 1.85 µm

0.23 Conclusion
The DC, AC, and transient analyses of the Common Source amplifier were successfully
performed, demonstrating its operational characteristics.

14
 Experiment - 4: Common Source Amplifier with
Active Diode Load
0.24 Aim
The purpose of this experiment is to explore and analyze the behavior of a Common
Source (CS) amplifier, specifically when implemented with a diode-connected MOSFET
functioning as an active load, through the use of Cadence Virtuoso simulation.

0.25 Apparatus
• Cadence Virtuoso Integrated Circuit Design Platform

0.26 Visual Representation of the Circuit

Figure 5: CS Amplifier Schematic Utilizing a Diode-Connected MOSFET as Load

0.27 Underlying Principles

In a CS amplifier design where a diode-connected MOSFET serves as the load, the active
load is realized by directly linking the gate terminal to the drain terminal of the MOSFET.
This architectural choice compels the load transistor into saturation mode, characterized
by a specific current-voltage relationship:
µn Cox W
ID = K(VGS − VT H )2 where K =
2L
The diode-connected load not only defines the operating bias but also introduces a
high impedance, influencing the voltage gain positively. Since the gate and drain are
intrinsically connected, the transistor operates in saturation, a prerequisite for linear
amplification.

0.28 Circuit Architectural Overview

The amplifier is structured around an NMOS transistor operating in a CS configuration.
The input signal is fed into the gate, and the amplified output is extracted from the
drain. Instead of a conventional resistive load, a MOSFET configured as a diode (gate

15
and drain joined) is employed. This active load enhances the stability of the operating
point and refines the amplifier’s gain and linearity.

0.29 Operating Point Determination

The quiescent operating point is defined by the biasing arrangement and the inherent
characteristics of the diode-connected load. The load transistor dictates a specific voltage
drop, thereby fixing the amplifying transistor’s drain voltage. Establishing this operating
point is vital for ensuring the transistor’s operation within its intended region.

0.30 DC Signal Analysis

For small-signal analysis, the MOSFET is represented by its equivalent small-signal pa-
rameters:

• Transconductance (gm ):

gm = 2K(VGS − VT H )

• Output Resistance (ro ):

1
ro =
λID
The amplifier’s voltage gain is calculated using:

Av = −gm Ref f
where Ref f signifies the effective resistance observed at the drain, accounting for the
diode-connected load’s contribution.

0.31 Procedure
1. Access the ”Work Cadence” directory.

2. Launch a terminal session within the directory.

3. Start the C shell: csh → Enter.

4. Load the environment profile: source CSHRC → Enter.

5. Initiate Virtuoso: virtuoso & → Enter.

6. Create a new library: File → New → Library.

7. Link the library to the required technology library.

8. Generate a new cell view within the library.

9. Add MOSFET instances and supplementary components via the instance browser.

10. Place the transistors and components on the schematic canvas.

11. Connect components using the wire tool.

16
 12. Store the design.

13. Modify component parameters as required.

14. Launch ADE L: Launch → ADE L.

15. Integrate necessary model libraries: Setup → Model Library.

16. Execute DC analysis: Analysis → Choose → DC.

17. Configure DC sweep parameters and select output nodes for observation.

18. Run DC simulation and examine the results.

19. Set up AC analysis by defining frequency parameters.

20. Simulate and plot the AC gain and phase.

21. For transient analysis, substitute the input source with a pulse generator.

22. Adjust pulse generator parameters.

23. Configure transient analysis parameters and run the simulation.

0.32 Numerical Analysis and Results

Given parameters:

|Av | = 2, Vd = 0.8 V, VDD = 1.8 V, ID = 0.8 µA,

Kn = 300 µA/V2 , Kp = 60 µA/V2 , L = 0.18 µm, |Vthn | = |Vthp | = 0.5 V.

For a MOSFET in saturation:

1 W
ID = K (VGS − Vth )2
2 L
For NMOS:
1 Wn
ID = Kn (VGS − Vthn )2
2 L
For PMOS:
1 Wp
ID = Kp (VSG − |Vthp |)2
2 L
Based on the specified design constraints and biasing conditions:

Wn = 0.72 µm and Wp = 0.92 µm

0.33 Result
The experiment successfully validated the DC, AC, and transient operational character-
istics of a Common Source amplifier configured with a diode-connected MOSFET as an
active load.

17