Digital CMOS

Integrated Circuits

By Dr. Bharat Choudhary

1
2
Course Outcome
• Analyze NMOS & CMOS inverter circuits
• Analyze and Design combinational and sequential circuits using
MOS devices.
• Describe the process of fabrication of NMOS and CMOS devices •
Draw the stick diagrams and layouts for different MOS circuits. •
Describe various issues involved in subsystem design and estimate
performance parameters.
 • Analyze the impact of interconnects on the circuit performance 3

Reference Books
Digital Integrated CIRCUITS:Analysis and Design” 3rd Systems
Circuits – A Design Perspective”, Ed. McGraw-Hill. Perspective” 4th ed. Addison Wesley
2nd ed. by J. Rabaey, A. By:SUNG-MO (STEVE) KANG By: Neil H. E. Weste,
“CMOS DIGITAL INTEGRATED “CMOS VLSI Design:A Circuits and
Chandrakasan, B. Nikolic David Money Harris
 4

Reference Books

“Basic VLSI Design”, 3rd Ed., A.ESHRAGHIAN,

PHI By: PUCKNELL DOUGLAS KAMRAN
 “CMOS LOGIC CIRCUIT DESIGN” PUBLISHERS By: John P.
KLUWER ACADEMIC Uyemura

Introduction
What is expected ?

Cost
Complexity ∝ Min
Intel 4004 Processor: $60 Intel i7 Processor :
Intel 4004 Processor: 2300 Transistor 10µm $366
Technology Intel i7 Processor : 3,200,000,000
Transistors 14nm Technology
 Intel i7 Processor : 47W Intel 4004 Processor: 12 mm2 Intel
Power Min i7 Processor : 246 mm²
Intel 4004 Processor: 1 W
Size Min
Delay Min
Intel 4004 Processor: 740KHz
Intel i7 Processor : 3.6 GHz

TECHNOLOGY GENERATIONS
Integration Year No. of transistors
level
SSI 1950s Less than 102
MSI 1960s 102 ≈ 103
 LSI 1970s 103 ≈ 105
VLSI 1980s 105 ≈ 107
ULSI 1990s 107 ≈ 109
SLSI 2000s Over 109

Moore’slaw
The evolution of MOS technology has followed the famous Moore’s law that
predicts a steady decrease in gate length. As predicted by Gordon Moore in
the 1960s, integrated circuit (IC) densities have been doubling
approximately every 18 months, and this doubling in size has been
accompanied by a similar exponential increase in circuit speed (or more
precisely, clock frequency).
 On-chip transistor count increase for the Intel processors (Source: Intel).
8

Moore’s Law and our expectation

Assume initial L=1,W=1 and Tox=1
Assume initial Vdd =1, Vt =1 and Tox=1
W=0.7, L=0.7, Tox=0.7
Vdd=0.7, Vt=0.7, T ox=0.7,
=> Lateral and vertical dimensions reduce 30 %
Area Cap = C = 0.7 X 0.7 = 0.7
T= C x Vdd = 0.7, Power = CV2f = 0.7 x 0.72 = 0.72
0.7
I 0.7
• Area reduced by 50%
 => Delay reduces by 30 % and Power reduces by 50 %
• Capacitance reduced by 30%

Microelectron Active
Bipolar
Substrate
ics Technology Micro
NMOS

PMOS

CMOS
MOS
TTL
Silicon ECL
 resistors

Electronics
Inert
Substrate
Very Fast
GaAs
10

Devices

Good

MOS Vs. BJT

Factors CMOS Bipolar
Static Power Dissipation Low High
Input Impedance High Low
 Noise Margin High Low
Packing Density High Low
Fan-out Low High
Direction Bidirectional Unidirectional

CMOS is superior!
11

Power Dissipation Vs. Delay

CMOS offers low powers dissipation with large
 delay 12

MOS Capacitor

Oxide thickness, Threshold voltage, and Doping levels, depend on the

fabrication process, and cannot be changed by design; they are
technology parameters.

13

MOS Capacitor
i. Accumulation

������
�� =
������
��
 A negative voltage is applied to the gate, so there is negative
charge on the gate. The mobile positively charged holes are
attracted to the region beneath the gate. This is called the
accumulation mode

14

MOS Capacitor
ii. Depletion
������
�� =
������
��

A small positive voltage is applied to the gate, resulting in some

positive charge on the gate. The holes in the body are repelled from
the region directly beneath the gate, resulting in a depletion region
forming below the gate.
 15

MOS Capacitor
iii. inversion

������
�� =
������
��

A higher positive potential exceeding a critical threshold

 voltage Vtis applied, attracting more positive charge to the
gate. The holes are repelled further and some free electrons
in the body are attracted to the region beneath the gate.
This conductive layer of electrons in the p-type body is
called the inversion layer

16

MOS Capacitor
 17

MOSFET
• Enhancement type MOSFET
1. N-Channel MOSFET
2. P-Channel MOSFET
• Depletion type MOSFET
1. N-Channel MOSFET
2. P-Channel MOSFET

18
 Enhancement MOSFET

Tox= 15Å to 100 Å (Diameter of SiO2 molecule is about 3.2Å)

Arrows always point from P to N, so an NMOS (N-channel in P-well or

P-substrate) has the arrow pointing in (from the bulk to the channel)
19

Enhancement MOSFET

VTh is fixed for NMOS and PMOS devices for given

 fabrication process 20

Enhancement NMOS Transistor 21

Operation Of N-MOS Transistor

Depending on the relative voltages of the source, drain and gate,
the NMOS transistor may operate in any of three regions viz :
 • Cut_off : Current flow is essentially zero (also called
accumulation region)

• Linear : (Non saturated region)-It is weak inversion region

drain current depends on gate and drain voltage.

• Saturation : It is strong inversion region where drain current

is independent of drain-source voltage.

22
23
24
25
25
27
 28

Important Observations
• The bulk or substrate of nMOS transistors must always be connected
to the lower voltage that is the reference terminal.
• The positive convention current in an nMOS device is from the drain
to the source, and is referred to as IDS or just ID, since drain and source
current are equal.
• When a positive voltage is applied to the drain terminal, the drain
current depends on the voltage applied to the gate control terminal.
 29

Input and Output characteristics of nMOS

input characteristics (ID vs. VGS ) for an nMOS,

30
nMOS transistor output characteristics

Enhancement PMOS Transistor 31

32
33
34
35
36
 37

pMOS transistor output characteristics

input characteristics (ID vs. VGS ) for an pMOS,

38
Depletion NMOS Transistor 39

Depletion Type MOS

Drain
Drain

Gate
 Gate

Source
Source
NMOS
PMOS

• In Depletion MOS structure, the source & drain are diffused

on P- substrate as shown above.
• Positive voltages enhances number of electrons from source
to drain.
• Negative voltage applied to gate reduces the drain current
• This is called as ‘ normally ON ’ MOS.
40
Determine the region of operation of M1in
each of the circuits shown in Fig.
VTH = 0.4 V for NMOS devices and −0.4 V for PMOS devices.
41
 VTH = 0.4V for NMOSdevicesand−0.4V for PMOS devices.
42

Determine the region of operation of M1in

each of the circuits shown in Fig.

43
Current Derivation For Enhancement NMOS 44

Drain to Source Current IDS

 45

The gate and the channel region form a parallel plate capacitor
for which the oxide layer serves as a dielectric.
������
�� =
������
��

ɛox= 3.9ɛ0 = 3.9×8.854×10−12 = 3.45×10−11 F/m

consider the infinitesimal strip of the gate at distance x from
the source. The capacitance of this strip is
CoxWdx

To find the charge stored on this infinitesimal strip of the gate

capacitance, we multiply the capacitance by the effective
voltage between the gate and the channel at point x,

������ − �� �� − ����
 46

Charge dq in the infinitesimal portion of the channel at point x

is

���� = −������������[������ − �� �� − ����]

Negative sign accounts for the fact that dq is a negative charge

The voltage VDS produces an electric field along the channel in

the negative x direction
����
�� �� (��)
=− ����
 The electric field E(x) causes the electron charge dq to

drift toward the drain with a velocity

47

����
= −������ ��

����= ��������(��)
����

Where µnis the mobility of electrons in the channel (called

surface mobility).

The resulting drift current i

����
 �� = =���� ����
���� ���� ����
�� = −������������[������ − �� �� −
����]����(��)
����

48

Thus i must be equal to the source-to-drain current. Since we

are interested in the drain-to-source current iD, we can find it
as
���� = ������������[������ − �� �� −
 ����]����(��)
����
�������� = ������������[������ − �� �� −
����]����(��)

Integrating both sides of this equation from x = 0 to x = L

and, correspondingly, for V(0) = 0 to V(L) = VDS,

49

Linear region: �� = ����������������22

[(������ − ����)������ − ����]

50
 Drain to Source Current IDS
Saturation Region ������ ≥ (������ − ����)
�� = ��������������[(������ − ����)(������ − ����)
2
− (������ − ����)

2]
�� 2 (��
�� = ���������� ��[ (������ − ����) − ���� −
����)2

2]
 ��
�� = �� ��
�� ���� 2
2��(������ − ����)

51
����������0����
��=
������
��

µ����
��′=
����
 ����=����������

52

1. A 0.18-μm fabrication process is specified to

2
have tox= 4nm, µn=450cm /Vs and VT=0.5V. Find
the value of µnCox(Also known as kn’ process
transconductance) For a MOSFET with minimum
length fabricated in this process, find the required
value of W so that the device exhibits a channel
=1V. Given eox=3.45e
resistance rDS of 1K at VGS
11 F/m Kn’= 388μA/V2
W= 0.93μm

53

2. Consider a process technology for which Lmin = 0.4 μm,

tox = 8 nm, μn = 450 cm2/V⋅ s, and Vt = 0.7 V.
Cox =4.31x10-3F/m2 Kn’= 194.1
(a) Find Cox and Kn’. μA/V2

(b) For a MOSFET with W/L= 8 μm ⁄ 0.8 μm calculate the

 values of VOV, VGS, and VDSmin needed to operate the
transistor in the saturation region with a dc current
= 1.015 V
ID = 100 μA.
VDSmin = VOV = 0.32 V VGS

(c) For the device in (b), find the values of VOV and VGS
required to cause the device to operate as a 1000-resistor
for very small vD VOV = 0.51 V VGS = 1.215 V

54

3. For a 0.8-μm process technology for which tox = 15 nm and

μn = 550 cm2/V⋅s, find Cox, K’n, and the overdrive voltage VOV
required to operate a transistor having W/L=20 in saturation
with ID = 0.2 mA. What is the minimum value of VDS needed?
C Kn’= 126.5μA/V2 VDSmin = VOV = .397 V≈0.4V ox =2.301x10-3F/m2

4. A circuit designer intending to operate a MOSFET in

saturation is considering the effect of changing the device
dimensions and operating voltages on the drain current ID.
Specifically, by what factor does ID change in each of the
following cases?
(a) The channel length is doubled.
(b) The channel width is doubled.
(c) The overdrive voltage is doubled.
(d) The drain-to-source voltage is doubled.
55

5. An enhancement type NMOS transistor with Vt = 0.7V

has its source terminal grounded and a 1.5-V DC is
applied to the gate. In what region does the device
operate :for (a) VD = +0.5 V (b) VD = +0.9 V (c) VD = +3 V

If the NMOS device in µnCox = 100 µA/V2, W = 10 µm,

and L = 1 µm, find the value of drain current that results
in each of the three cases (a), (b), and (c).

(a) Non Satn 275 µA

(b) Satn 320 µA
(c) Satn 320 µA

56
Second-order Effects
• Body Effect.
• Sub threshold conduction
• Channel length modulation
• Mobility variation
• Fowler-Nordheim tunneling
• Drain punchthrough
• Impact Ionization-Hot electrons.
 57

Body Effect
What happens if the bulk voltage of an N-MOSFET drops below
the source voltage ?
 ������0 = ������ + 2���� +��������
������

where φMS is the difference between the work

functions of the polysilicon gate and the silicon
substrate
φF= Fermi potential

58

Sub threshold conduction

For VGS ≈ VTH, a "weak“ inversion layer still exists and some
current flows from D to S. Even for VGS < VTH, IDis finite, but it
exhibits an exponential dependence on VGS Called "subthreshold
conduction“. this effect can be formulated for VDS greater than
roughly 200 m V as

ζ>1 is a nonideality factor

59
Channel length modulation

λ is a process-technology parameter
with the dimensions of V-1
 60

VAis a process-technology parameter with the dimensions of

 V.
61

Mobility variation
Mobility is the defined as the ease with which the charge carriers drift in the
substrate material. Mobility decreases with increase in doping concentration and
increase in temperature. Mobility is the ratio of average carrier drift velocity and
electric field. Mobility is represented by the symbol μ.
 62

Fowler Nordhiem tunneling:

When the gate oxide is very thin there can be a current between
gate and source or drain by electron tunneling through the gate
oxide. This current is proportional to the area of the gate of the
transistor.

63

Drain punchthrough
When the drain is a high voltage, the depletion region around
the drain may extend to the source, causing the current to flow
 even it gate voltage is zero. This is known as Punchthrough
condition.

64

Impact Ionization-Hot electrons

When the length of the transistor is reduced, the electric field at
the drain increases. The field can be come so high that electrons
are imparted with enough energy we can term them as hot. These
hot electrons impact the drain, dislodging holes that are then
swept toward the negatively charged substrate and appear as a
substrate current. This effect is known as Impact Ionization.

65
 Inverters
1. Ideal inverter
2. Resistive load inverter
3. n-type MOSFET load
i. Enhancement load inverter
ii. Depletion load inverter
4. CMOS inverter

66
Ideal Inverters

DC Voltage transfer characteristics (VTC)

of an ideal inverter
 67

General circuit of an nMOS Inverter

Vin = VGSLumped
capacitance
 VOH: Maximum output voltage when the output level is logic " 1”
VOL: Minimum output voltage when the output level is logic “0”
VIL: Maximum input voltage which can be interpreted as logic "0"
VIH: Minimum input voltage which can be interpreted as logic "1" 68

Resistive Load Inverter

 69

Calculation of VOH, VOL, VIL, VIH

VOH: Maximum output voltage when the output level is
logic " 1”
70
Calculation of VOH,
 VOL, VIL, VIH
VOL: Minimum output voltage when the output level is logic “0”
71
Calculation of VOH, VOL, VIL, VIH
VIL: Maximum input voltage which can be interpreted as logic "0"
 72

Calculation of VOH, VOL, VIL, VIH

VIH: Minimum input voltage which can be interpreted as logic "1"
73
Enhancement load NMOS inverter

Load is in saturation
 Load is in Linear VOH = VDD – VT,load VOH = VDD75
Depletion Load NMOS Inverter
 VT0,driver > 0
VT0,load < 0

At this condition the load will always be in ON state.76

Depletion Load NMOS
Inverter
 76

smaller than the

Depletion Load
NMOS Inverter
Calculation of VOH
driver
When the input voltage Vin is
threshold voltage VT0, the driver transistor is turned off and
does not conduct any drain current. Consequently, the load
device, which operates in the linear region, also has zero drain
current.
Substituting VOH for Vout
 78

Depletion Load NMOS Inverter Calculation of VOL

We assume that the input voltage Vin of the inverter is equal to VOH = VDD Driver transistor linear
region
Depletion-type load saturation region

This second-order equation in VOL can be solved by temporarily

neglecting the dependence of VT load on VOL, as follows.
 79

Depletion Load NMOS Inverter

Calculation of VIL
80