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The document discusses the completeness of 2-input NAND and NOR gates as logic gates, providing proofs for both. It includes definitions of various terms related to combinational and sequential circuits, as well as expressions like product terms and canonical forms. Additionally, it covers the design of CMOS circuits, minimization using Boolean algebra, and methods for finding minimal expressions using Karnaugh maps.

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15 views8 pages

Mid

The document discusses the completeness of 2-input NAND and NOR gates as logic gates, providing proofs for both. It includes definitions of various terms related to combinational and sequential circuits, as well as expressions like product terms and canonical forms. Additionally, it covers the design of CMOS circuits, minimization using Boolean algebra, and methods for finding minimal expressions using Karnaugh maps.

Uploaded by

alhoxha23
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1. Do 2-inputs NAND gate form a complete set of logic gates? Prove your answer.

2. Do 2-inputs NOR gate form a complete set of logic gates? Prove your answer.
3. The definitions of:
a. Literals: a variable or its complement 1 point
b. Combinational circuit: Output depends only on the current input values (called an input
combination) 1 point
c. Sequential circuit’s: Sequential circuit’s output depends not only on its current input but also on
the past sequence of inputs that have been applied to it. • I.e., a sequential circuit has memory of
past events 1 point
d. Product term: X, X’·Y, X·Y’·Z 1 point
e. Sum-of-products expression: X + X·W’ 1 point
f. Sum term: X, X’+Y, X+Y’+Z 1 point
g. Product-of-sums expression: (X’+Y) · (Y+Z) 1 point
h. Minterm (n variables) -- a normal product term with n literals
– 2n terms, e.g., X·Y’·Z (n=3)
--- AND terms with every variable present in either true or complemented form
-– is “1” in a given row of the truth table. 1 point
i. Maxterm (n variables) -- a normal sum term with n literals
– 2n terms, e.g., X’+Y’+Z
--- OR terms with every variable in true or complemented form
– is “0” in a given row of the truth table 1 point
j. First and second Canonical form (SOP and POS). 2 point
Canonical sum: is the sum of the minterms corresponding to the truth-table rows of values “1”.
F = ΣX,Y,Z (1,2,5,7) minterm list = X’·Y’·Z + X’·Y·Z’ + X·Y’·Z + X·Y·Z
Canonical product: is the product of the maxterms corresponding to the truth-table rows of values
“0”. F = ΠX,Y,Z (0,3,4,6) maxterm list = (X+Y+Z) · (X+Y’+Z’) · (X’+Y+Z) · (X’+Y’+Z)
The two descriptions are in fact the same. The relation between the minterm and the maxterm lists
is e.g. ΣX,Y,Z (1,2,5,7) = ΠX,Y,Z (0,3,4,6)
k. Decoder: A decoder is a logic circuit that converts coded inputs into coded outputs. Each input
code word produces a different output code word (there is a one-to-one mapping between inputs
and outputs) 2 points

Binary Decoder: Accepts a n-bit binary input code and generates a 1-outof- 2n output code. Used to
activate exactly one of 2n outputs based on n-bit input value. Examples: 2-to-4, 3-to-8, 4-to-16, etc.
l. Multiplexer: A multiplexer (MUX for short) is a digital switch: – it passes (connects) one of its
data inputs to the Output - – the data input selected is a function of a set of control inputs
called selection inputs. 2 points
4. DeMorgan Symbols 6 points

5. Minimized using Boolean algebra: 5 points

a) A• A•0 = 0 A+A+0= A A• A•1 = A A + A +1 = 1

b) (A• A + E) • (A + A + Ē) = (A+E) • (A+Ē)= A•A+A•Ē +E•A+E•Ē = A+A(Ē+E)+0=


A+A•1= A+A=A
7. Give the answers:

F1 = (A• A)’=A’ F=A’ F2 = (1•A)’=A’ F=A F3= (0•A)’=0’=1 F=1


F4 = (A+A)’=A’ F=A’ F5 = (1+A)’=1’=0 F=0 F6 = (0+A)’= A’ F=A’

PART B - (55 + 5 bonus)Points


8. Design a CMOS circuit for the following logic function: F = (A+B) • (E’+F+C’) 7.5 points

F = (A+B) • (E’+F+C’) = F = ((A+B) • (E’+F+C’))’’ =((A+B)’ + (E’+F+C’)’ )’ = ((A’B’) + (EF’C))’


9. Complete the down part of CMOS circuit and define the OUT function: 7.5 points

F = ((A’+B+C’)(M’+LN))’
OUT=(A’+B+C’)(M’+LN)
10. Write the canonical sum and product for each of the following logic functions: 5 points (bonus)
F = Σ X1X0 (1,3) = X 1 ’X0 + X 1 X0 F = ΠX1X0 (0,1,3) = (X1 +X 0 ) (X1 + X0 ’) (X 1 ’+ X0)
’

F = Σ X2X1X0 (0,1,3,4,5) = X2’X1’X0’+ X2’X1’X0+ X2’X1X0 + X2X1‘X0’ + X2 X1’X0


F = Π X2X1X0 (2,4,6,7) = (X2+X1’+X0)(X2’+X1+X0)(X2’+X1’+X0) (X2’+X1’+X0’)
11. Using Karnaugh map (KM), find a minimal sum-of-products expression, minimal product-of-sums
expression for logic function : F = Σ X3X2X1X0 (0,2,3,6,7,8,10,11,15), and obtain the corresponding logic diagram
using : 40 points
a. AND/OR, OR/AND, NAND/NAND, NOR/NOR Gates.
b. Eliminate static hazards only for the sum-of-products expression
c. Implement the Boolean function using:
i. only: a. one 8/1 multiplexer, b. 4/1 multiplexers (mux-tree).
ii. only: a. 2/4 decoders and OR gate b. 3/8 decoders and OR gate
X3, X2
F1 = X0’X2’ + X1X0 + X1X3’
X1, X0 00 01 11 10
0 1 F2 =(F1’)’ =( (X0’X2’)’(X1X0)’(X1X3’)’)’
00 1 0
0 F3 =( X1+X0’)(X1+X2’)(X0+X2’+X3’)
01 0 0 0
F4 =(F3’)’=(( X1+X0’)’+(X1+X2’)’+(X0+X2’+X3’)’)’
1 1
11 1 1
Eliminate static hazards:
10 F5 = X0’X2’ + X1X0 + X1X3’ + X1X2’
1 1 1
0
N X3 X2 X1 X0 F I
0 0 0 0 0 1 I0=X0’
1 0 0 0 1 0
2 0 0 1 0 1 I1=1
3 0 0 1 1 1
4 0 1 0 0 0 I2=0
5 0 1 0 1 0
6 0 1 1 0 1 I3=1
7 0 1 1 1 1
8 1 0 0 0 1 I4= X0’
9 1 0 0 1 0
10 1 0 1 0 1 I5=1
11 1 0 1 1 1
12 1 1 0 0 0 I6=0
13 1 1 0 1 0
14 1 1 1 0 0 I7=X0
15 1 1 1 1 1

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