Here are the answers to the microcontroller question bank:

1.​ Demonstrate and explain ARM processors exception and associated modes with a
neat diagram. [cite_start]An exception in an ARM processor is an event that causes a
change in the normal flow of program execution. [cite_start]This can be due to external
interrupts, internal errors, or software interrupts. [cite_start]When an exception occurs, the
processor typically switches to a specific exception mode to handle the event. Associated
modes for ARM processors typically include:
○​ [cite_start]User Mode: The normal execution mode for applications.
○​ [cite_start]System Mode: A privileged mode that shares the same registers as
User mode.
○​ [cite_start]Supervisor (SVC) Mode: Entered on reset and software interrupts.
○​ [cite_start]Abort Mode: Entered when there's a memory access violation.
○​ [cite_start]Undefined Mode: Entered when an undefined instruction is
encountered.
○​ [cite_start]IRQ Mode: Entered when a normal interrupt request occurs.
○​ [cite_start]FIQ Mode: Entered when a fast interrupt request occurs. (A neat
diagram would typically show the processor and how different events lead to
transitions between these modes, indicating the flow of control and register sets
involved.)
2.​ Illustrate the Interrupt latency and nested interrupt and explain in detail with
diagram.
○​ [cite_start]Interrupt Latency: This refers to the time delay between an interrupt
event occurring and the processor starting to execute the corresponding Interrupt
Service Routine (ISR). [cite_start]Factors affecting latency include the current
instruction being executed, context switching overhead, and any interrupt masking.
○​ [cite_start]Nested Interrupts: This occurs when an interrupt happens while another
interrupt's ISR is already being executed. [cite_start]If the priority of the new
interrupt is higher than the currently executing one, the processor will pause the
current ISR, save its context, and jump to the new, higher-priority ISR.
[cite_start]Once the higher-priority ISR completes, the processor returns to the
interrupted ISR. (A diagram for interrupt latency would show the timeline from
interrupt assertion to ISR execution. A diagram for nested interrupts would show
two ISRs, one interrupting the other, with context saving and restoring indicated.)
3.​ Write a short code snippet to enable and disable interrupts with expected outputs.
(Note: The actual code snippet would depend on the specific ARM architecture and
compiler being used, but a generic conceptual example can be provided.) To
enable/disable interrupts on ARM, you often manipulate the CPSR (Current Program
Status Register) or use specific assembly instructions.
○​ To Disable IRQ interrupts (example using MSR instruction):​
MRS R0, CPSR ; Read current CPSR into R0​
ORR R0, R0, #0x80 ; Set the I-bit (bit 7) to disable IRQ​
MSR CPSR_c, R0 ; Write updated CPSR back​
Expected Output: After this, the processor will not respond to normal IRQ interrupts
until re-enabled.
○​ To Enable IRQ interrupts (example using MSR instruction):​
MRS R0, CPSR ; Read current CPSR into R0​
BIC R0, R0, #0x80 ; Clear the I-bit (bit 7) to enable IRQ​
MSR CPSR_c, R0 ; Write updated CPSR back​
 Expected Output: After this, the processor will respond to pending and future IRQ
interrupts.
[cite_start](Similar methods apply for FIQ interrupts by manipulating the F-bit (bit 6) in the
CPSR. Some ARM architectures also provide CPSIE and CPSID instructions for easier
interrupt enabling/disabling.)
4.​ Draw the Exception priority level table and explain exception priorities. (A table
would typically list exceptions in descending order of priority, with higher priority meaning
it will be handled first if multiple exceptions occur simultaneously.) Common ARM
exception priorities (highest to lowest):
1.​ [cite_start]Reset
2.​ [cite_start]Memory Abort (Data Abort/Prefetch Abort)
3.​ [cite_start]FIQ (Fast Interrupt Request)
4.​ [cite_start]IRQ (Interrupt Request)
5.​ [cite_start]Software Interrupt (SWI) / Undefined Instruction [cite_start]The priority
level determines which exception takes precedence if multiple exception conditions
are met simultaneously. [cite_start]A higher priority exception will interrupt a lower
priority exception's handler if it occurs during its execution.
5.​ Illustrate IRQ and FIQ exceptions with state diagrams. (State diagrams for IRQ and
FIQ would show the normal program execution state transitioning to the respective
IRQ/FIQ handler state upon the assertion of the interrupt signal, followed by a return to
the original execution state after the handler completes. The key difference in the
diagrams would be the saving/restoring of registers and potentially a shorter latency for
FIQ due to dedicated banked registers.)
○​ [cite_start]IRQ (Interrupt Request): A general-purpose interrupt that uses banked
registers for R13 (SP) and R14 (LR). [cite_start]When an IRQ occurs, the processor
saves the current CPSR, the return address (PC + 4 or PC + 8 depending on the
instruction), and switches to IRQ mode to execute the ISR.
○​ [cite_start]FIQ (Fast Interrupt Request): A high-priority interrupt designed for
low-latency responses. [cite_start]It has more banked registers (R8-R12, R13, R14)
than IRQ, which reduces the need to save and restore general-purpose registers,
thus speeding up context switching.
6.​ Demonstrate how to enable and disable IRQ and FIQ interrupts. This is similar to
question 3.
○​ Enabling/Disabling using CPSR manipulation:
■​ The I-bit (bit 7) in the CPSR controls IRQ interrupts. [cite_start]Setting it
disables IRQ, clearing it enables IRQ.
■​ The F-bit (bit 6) in the CPSR controls FIQ interrupts. [cite_start]Setting it
disables FIQ, clearing it enables FIQ.
○​ Assembly Instructions (e.g., MSR, CPSIE, CPSID):
■​ [cite_start]To disable IRQ: CPSID i or manipulate CPSR using MRS and MSR
to set the I-bit.
■​ [cite_start]To enable IRQ: CPSIE i or manipulate CPSR using MRS and MSR
to clear the I-bit.
■​ [cite_start]To disable FIQ: CPSID f or manipulate CPSR using MRS and MSR
to set the F-bit.
■​ [cite_start]To enable FIQ: CPSIE f or manipulate CPSR using MRS and MSR
to clear the F-bit.
7.​ Define firmware? Explain firmware execution flow with examples.
 [cite_start]Firmware is a specific class of computer software that provides low-level
control for a device's specific hardware. [cite_start]It acts as a bridge between the
hardware and the operating system or application software. [cite_start]Examples include
the BIOS/UEFI in a computer, the software in a router, or the embedded code in a
microcontroller.Firmware Execution Flow: When a device with firmware is powered on:
1.​ [cite_start]Reset Vector: The processor typically starts execution from a predefined
memory location, often called the reset vector.
2.​ [cite_start]Initialization: The firmware's initial code performs essential hardware
initialization tasks, such as setting up clock speeds, memory controllers, and
peripheral devices.
3.​ [cite_start]Self-Test (Optional): Some firmware might run self-tests to ensure
hardware components are functioning correctly.
4.​ [cite_start]Bootloader/OS Loading: For systems with an operating system, the
firmware (often a bootloader) then loads the OS kernel from a storage device into
memory and transfers control to it.
5.​ [cite_start]Main Loop (for embedded systems): In simpler embedded systems
without a full OS, the firmware might enter a main loop that continuously monitors
inputs, processes data, and controls outputs based on its programmed logic.
Example: A simple washing machine microcontroller firmware:
○​ Power On: Microcontroller starts, loads firmware.
○​ Initialization: Sets up timers, ADC for water level sensor, motor control pins.
○​ User Input: Waits for user to select a wash cycle.
○​ Execution: Based on selection, starts filling water, turning the motor, heating water,
draining, and spinning. This entire sequence is orchestrated by the firmware.
○​ Error Handling: If a sensor detects an overflow, the firmware might activate a drain
pump and display an error.
8.​ Illustrate and explain in detail the memory hierarchy and cache memory.
○​ [cite_start]Memory Hierarchy: This is a system that organizes computer storage
into a hierarchy based on speed, cost, and capacity. [cite_start]The goal is to
provide fast access to frequently used data while keeping overall storage costs
down.
■​ [cite_start]Registers: Fastest, smallest, most expensive (within the CPU).
■​ [cite_start]Cache Memory (L1, L2, L3): Faster than main memory, smaller
capacity, more expensive.
■​ [cite_start]Main Memory (RAM): Slower than cache, larger capacity, less
expensive.
■​ [cite_start]Secondary Storage (SSD/HDD): Slowest, largest capacity,
cheapest. (A diagram would show layers of memory, with capacity increasing
and speed decreasing as you move down the hierarchy from CPU registers
to secondary storage.)
○​ [cite_start]Cache Memory: A smaller, faster memory that stores copies of data
from frequently used main memory locations. [cite_start]When the CPU needs data,
it first checks the cache.
■​ [cite_start]Cache Hit: If the data is found in the cache, it's a "cache hit," and
the data is retrieved quickly.
■​ [cite_start]Cache Miss: If the data is not in the cache, it's a "cache miss," and
the CPU fetches the data from the next level of the memory hierarchy (e.g.,
main memory) and brings a copy into the cache for future use.
 ■​ [cite_start]Locality of Reference: Cache memory works on the principle of
locality of reference, meaning programs tend to access data that is spatially
or temporally close to recently accessed data.
9.​ Examine the basic architecture of cache memory with a neat diagram. (A diagram of
cache memory would typically show the CPU connected to the cache, and the cache
connected to main memory. The cache itself would be divided into cache lines/blocks,
each containing data, a tag, and a valid bit. The tag is used to identify which block of main
memory is currently stored in that cache line.) Basic components of cache memory
architecture:
○​ [cite_start]Cache Lines/Blocks: The smallest unit of data transferred between
main memory and cache.
○​ [cite_start]Tag: A portion of the memory address that identifies which block of main
memory data is currently stored in a particular cache line.
○​ [cite_start]Index: A portion of the memory address used to determine which cache
set or line a particular memory block might reside in.
○​ [cite_start]Offset: A portion of the memory address that indicates the position of the
desired data within a cache line.
○​ [cite_start]Valid Bit: Indicates whether the data in a cache line is valid (i.e.,
contains current data).
○​ [cite_start]Dirty Bit (for write-back caches): Indicates whether the data in the
cache line has been modified and is different from the data in main memory.
10.​Demonstrate the Sandstone execution flow in detail with a diagram. (Without specific
documentation on "Sandstone," this question is difficult to answer accurately. Assuming
"Sandstone" refers to a specific embedded system framework or a particular processor's
boot process, the answer would need that context. If "Sandstone" is a generic term for a
robust embedded system boot, the flow might involve secure boot, bootloader stages, and
application loading.)If "Sandstone" refers to a specific ARM platform or framework, its
execution flow would typically involve several stages:
1.​ [cite_start]ROM Boot: Initial code execution from internal ROM. [cite_start]This
often includes basic hardware initialization and security checks.
2.​ [cite_start]Primary Bootloader: Loads a secondary bootloader or OS kernel from
external non-volatile memory (e.g., eMMC, NAND). [cite_start]This stage might also
handle memory controller setup.
3.​ [cite_start]Secondary Bootloader (if applicable): Further initializes the system,
potentially sets up peripherals, and loads the main operating system or application.
4.​ [cite_start]OS/Application Execution: The main software takes control.
(A diagram would show these stages, indicating the flow of control and data loading.)
11.​List and explain the different types of Cache policy. Cache policies dictate how data is
managed within the cache, particularly during write operations and when a cache line
needs to be replaced.
○​ Write Policies:
■​ [cite_start]Write-Through: Data is written to both the cache and main
memory simultaneously. [cite_start]This ensures data consistency but can be
slower due to main memory access latency.
■​ [cite_start]Write-Back (or Copy-Back): Data is initially written only to the
cache. [cite_start]A "dirty bit" is set for the modified cache line. [cite_start]The
updated data is written back to main memory only when the cache line is
evicted (replaced) or explicitly flushed. [cite_start]This is generally faster but
 introduces complexity in maintaining consistency.
○​ Cache Miss Policies (Allocation Policy on a cache miss):
■​ [cite_start]Write-Allocate (or Fetch on Write): On a write miss, the block
containing the target address is first loaded into the cache, and then the write
operation is performed on the cache. [cite_start]Often used with write-back
caches.
■​ [cite_start]No-Write-Allocate (or Write-No-Allocate, Write-Around): On a
write miss, the data is written directly to main memory without loading the
block into the cache. [cite_start]Often used with write-through caches.
○​ Replacement Policies: Determine which cache line to evict when a new block
needs to be brought into a full cache set.
■​ [cite_start]LRU (Least Recently Used): Evicts the block that has not been
accessed for the longest time.
■​ [cite_start]FIFO (First-In, First-Out): Evicts the block that has been in the
cache for the longest time.
■​ [cite_start]LFU (Least Frequently Used): Evicts the block that has been
accessed the fewest times.
■​ [cite_start]Random: Randomly selects a block to evict.
12.​Illustrate and explain the measuring of Cache efficiency. Cache efficiency is typically
measured by metrics related to cache hits and misses.
○​ Hit Rate: The percentage of memory accesses that are found in the cache. Hit
Rate = \\frac{Number; of; Cache; Hits}{Total; Number; of; Memory; Accesses}
[cite_start]A higher hit rate indicates better cache efficiency.
○​ Miss Rate: The percentage of memory accesses that are not found in the cache.
Miss Rate = \\frac{Number; of; Cache; Misses}{Total; Number; of; Memory;
Accesses} Miss Rate = 1 - Hit Rate [cite_start]A lower miss rate indicates better
cache efficiency.
○​ Average Memory Access Time (AMAT): This metric combines the hit rate, miss
rate, cache access time, and main memory access time to give an overall picture of
memory system performance. AMAT = Cache; Hit; Time + (Miss; Rate \\times Main;
Memory; Access; Time) [cite_start]A lower AMAT indicates better cache efficiency.
(An illustration would show the flow of memory access, indicating where hits and misses
occur and how they contribute to the overall access time.)
13.​Draw and explain the vector table and processor modes.
○​ [cite_start]Vector Table: The ARM vector table is a table of memory addresses
(vectors) that the processor jumps to when an exception occurs. [cite_start]Each
entry in the table corresponds to a specific exception type (e.g., Reset, Undefined
Instruction, SWI, Prefetch Abort, Data Abort, IRQ, FIQ). [cite_start]The table is
typically located at a fixed memory address (e.g., 0x00000000) or a configurable
base address. (A diagram would show a memory block labeled "Vector Table" with
entries like "Reset Vector," "Undefined Instruction Vector," "SWI Vector," etc., each
pointing to the start address of the corresponding exception handler.)
○​ [cite_start]Processor Modes: (As explained in Question 1) ARM processors
operate in various modes, each with different privilege levels and access rights to
system resources. [cite_start]These modes are crucial for managing exceptions and
ensuring system stability.
■​ User Mode
■​ System Mode
 ■​ Supervisor (SVC) Mode
■​ Abort Mode
■​ Undefined Mode
■​ IRQ Mode
■​ FIQ Mode (A diagram for processor modes would show how the modes relate
to each other and how exceptions cause transitions between them.)
14.​Demonstrate the types of interrupts available on ARM processor. ARM processors
support several types of interrupts, which are a subset of exceptions:
○​ [cite_start]IRQ (Interrupt Request): General-purpose, lower-priority interrupt.
[cite_start]It's typically used for common peripheral events.
○​ [cite_start]FIQ (Fast Interrupt Request): High-priority interrupt designed for rapid
response. [cite_start]It has dedicated banked registers to reduce context-switching
overhead.
○​ [cite_start]Software Interrupt (SWI) / System Call: An exception triggered by a
software instruction (SWI or SVC instruction). [cite_start]Used by applications to
request services from the operating system kernel.
○​ [cite_start]Reset: Not strictly an "interrupt" in the sense of an event during
execution, but it's the initial exception that occurs when the processor is powered
on or reset, leading to the boot process.
○​ [cite_start]Data Abort: An exception caused by an illegal memory access during a
data transfer (e.g., trying to access a non-existent memory location or a protected
area).
○​ [cite_start]Prefetch Abort: An exception caused by an attempt to fetch an
instruction from an invalid or protected memory address.
○​ [cite_start]Undefined Instruction: An exception that occurs when the processor
tries to execute an instruction that it doesn't recognize.
15.​Write a short code snippet to enable and disable interrupts, with expected outputs.
This is a duplicate of Question 3. Please refer to the answer for Question 3.
16.​Explain link register offset, with examples and the link register table.
○​ [cite_start]Link Register (LR) Offset: The Link Register (R14) in ARM stores the
return address when a branch with link (BL) instruction is executed, or when an
exception occurs. [cite_start]The offset refers to the adjustment needed to the LR
value to get the actual instruction address where execution should resume.
■​ [cite_start]For a BL instruction, the LR stores PC - 4 (on ARMv4T and later,
for 32-bit instructions), so the return address is LR.
■​ [cite_start]For exceptions, the LR stores the address of the instruction after
the one that caused the exception, or the instruction that needs to be
re-executed. The specific offset depends on the exception type.
○​ Link Register Table (for exceptions, simplified): | Exception Type | LR Value
(before adjustment) | Return Address Calculation | | :-------------------- |
:--------------------------- | :------------------------- | | Software Interrupt (SWI) | Address of
SWI instruction | LR - 4 (to re-execute SWI) or LR (if SWI is not to be re-executed) |
| Undefined Instruction | Address of Undefined Instruction | LR - 4 (to re-execute or
skip) | | Prefetch Abort | Address of aborted instruction | LR - 4 (to re-execute) | |
Data Abort | Address of aborted instruction | LR - 8 (to re-execute) | | IRQ | Address
of next instruction | LR (usually) | | FIQ | Address of next instruction | LR (usually) |
○​ Example (Prefetch Abort): If a Prefetch Abort occurs at address 0x1000, the LR
will be loaded with 0x1004 (address of the instruction that caused the abort + 4, for
 32-bit instructions). [cite_start]To return to the instruction that caused the abort for
re-execution after fixing the issue, you would need to subtract 4 from LR (LR - 4 =
0x1000).
17.​List the design decisions to be made for the stacks and explain with a diagram of
memory layouts. Stack design decisions are crucial for system stability and efficient
memory usage.
○​ Number of Stacks:
■​ [cite_start]Single Stack: A simpler approach where all modes share one
stack. [cite_start]Can lead to issues if a user mode application corrupts the
stack, affecting privileged modes.
■​ [cite_start]Multiple Stacks (Banked Stacks): ARM processors use banked
R13 (SP) registers for different processor modes (e.g., User/System, SVC,
IRQ, FIQ, Abort, Undefined). [cite_start]This provides a separate stack for
each privileged mode, enhancing robustness as an issue in one mode's stack
won't directly affect others.
○​ Stack Growth Direction:
■​ [cite_start]Ascending: Stack grows towards higher memory addresses.
■​ [cite_start]Descending: Stack grows towards lower memory addresses (most
common in ARM).
○​ Full/Empty Stack:
■​ [cite_start]Full: Stack pointer points to the last valid (full) item on the stack.
PUSH decrements SP, then stores. [cite_start]POP retrieves, then increments
SP.
■​ [cite_start]Empty: Stack pointer points to the next empty location. PUSH
stores, then increments SP. [cite_start]POP decrements SP, then retrieves.
■​ [cite_start]Combined (FA/FD/EA/ED): ARM typically uses Full Descending
(FD) or Empty Descending (ED). FD means SP points to the last pushed
item, and the stack grows downwards. ED means SP points to the next
available location, and the stack grows downwards.
○​ [cite_start]Stack Size: Determining the maximum stack usage for each mode to
prevent stack overflow.
○​ [cite_start]Stack Overflow/Underflow Detection: Mechanisms to detect when the
stack grows beyond its allocated memory or when a pop operation is attempted on
an empty stack.
(A diagram of memory layouts would show separate memory regions allocated for each
mode's stack, with arrows indicating the stack growth direction (e.g., downwards from a
high address).)
18.​Illustrate IRQ and FIQ exceptions with state diagrams. This is a duplicate of Question
5. Please refer to the answer for Question 5.
19.​List ARM firmware execution flow with features and explain. This is a duplicate of
Question 7, with a focus on features. ARM Firmware Execution Flow (with features):
1.​ Reset and Initial Entry:
■​ Feature: Fixed entry point (reset vector) in ROM.
■​ [cite_start]Explanation: When the ARM processor powers on or resets, it
starts executing code from a predetermined memory address, usually in
internal ROM. This ensures a consistent boot sequence.
2.​ Basic Hardware Initialization:
■​ Feature: Minimalistic setup of essential components.
 ■​ [cite_start]Explanation: The first stage of firmware initializes core
components like the clock system, memory controller, and potentially basic
I/O (e.g., serial port for debugging). This ensures the processor can
communicate with vital hardware.
3.​ Bootloader Stages (if applicable):
■​ Feature: Multi-stage loading for complex systems.
■​ [cite_start]Explanation: For systems with external flash memory or complex
boot sequences, the initial ROM code (Stage 1 bootloader) might load a more
capable bootloader (Stage 2) into RAM. [cite_start]This second stage can
then perform more extensive hardware setup and load the main operating
system or application.
4.​ Security Features:
■​ Feature: Secure Boot, TrustZone.
■​ [cite_start]Explanation: Modern ARM firmware often includes secure boot
mechanisms to verify the authenticity and integrity of subsequent boot stages
and the loaded software. [cite_start]ARM's TrustZone technology allows for a
secure (trusted) world and a non-secure (normal) world, providing
hardware-enforced isolation for critical operations.
5.​ Device-Specific Initialization:
■​ Feature: Tailored setup for peripherals.
■​ [cite_start]Explanation: The firmware initializes specific peripherals relevant
to the device's function, such as GPIOs, timers, ADCs, communication
interfaces (SPI, I2C, UART), etc..
6.​ OS/Application Hand-off:
■​ Feature: Transfer of control.
■​ [cite_start]Explanation: For systems running an OS, the firmware
(bootloader) eventually loads the OS kernel into RAM and jumps to its entry
point, handing over control. [cite_start]For bare-metal embedded systems,
the firmware enters its main application loop.
7.​ Power Management:
■​ Feature: Control of power states.
■​ [cite_start]Explanation: Firmware is responsible for managing power states,
allowing the system to enter low-power modes when idle to conserve energy.
20.​Contrast between Logical and Physical Caches with neat diagrams.
○​ Logical (Virtual) Cache:
■​ [cite_start]Definition: The cache stores data indexed and tagged by virtual
(logical) addresses.
■​ [cite_start]Pros: Faster cache access because the CPU can access the
cache in parallel with the Memory Management Unit (MMU) doing address
translation; no need to wait for physical address translation before cache
lookup.
■​ [cite_start]Cons: Can have issues with aliasing (different virtual addresses
mapping to the same physical address) and homonyms (same virtual address
mapping to different physical addresses across processes), requiring
complex solutions to maintain cache coherence, especially in multi-tasking
environments. [cite_start]Context switches require flushing parts of the cache
or using ASID (Address Space ID) to differentiate processes. (Diagram would
show CPU generating virtual address, which directly goes to cache, while
 MMU translates to physical address concurrently.)
○​ Physical Cache:
■​ [cite_start]Definition: The cache stores data indexed and tagged by physical
addresses.
■​ [cite_start]Pros: Simpler to design and manage in multi-tasking systems as
physical addresses are unique; no aliasing/homonym issues; no need to flush
cache on context switches.
■​ [cite_start]Cons: Slower cache access because the virtual address must first
be translated to a physical address by the MMU before the cache can be
accessed, introducing a latency. (Diagram would show CPU generating virtual
address, MMU translating to physical address, and then the physical address
going to cache.)
21.​Illustrate and explain in detail memory hierarchy and cache memory. This is a
duplicate of Question 8. Please refer to the answer for Question 8.
22.​Demonstrate Sandstone execution flow in detail with a neat diagram of the
directory layout. This is a duplicate of Question 10. As noted previously, specific details
depend on what "Sandstone" refers to. A diagram would show the boot stages and how
different components (ROM, bootloader, kernel, etc.) are organized within
memory/storage.
23.​List and explain the Cache policy in detail. This is a duplicate of Question 11. Please
refer to the answer for Question 11.
24.​Illustrate the Allocation policy on a cache miss with example. This refers to the
"Cache Miss Policies" discussed in Question 11.
○​ Write-Allocate (or Fetch on Write):
■​ Illustration:
1.​ CPU issues a write to an address X (cache miss).
2.​ The cache controller fetches the entire cache block containing X from
main memory into the cache.
3.​ The write operation is then performed on the data in the cache.
4.​ (If write-back policy) The dirty bit for this cache line is set.
■​ Example: If the CPU wants to write to address 0x1004, and 0x1000-0x100F
is a cache block, on a write miss, the entire 0x1000-0x100F block is brought
into the cache, and then 0x1004 is updated. This is beneficial if there's high
spatial locality, as subsequent reads or writes to the same block will be cache
hits.
○​ No-Write-Allocate (or Write-Around):
■​ Illustration:
1.​ CPU issues a write to an address X (cache miss).
2.​ The write operation is performed directly to main memory, bypassing
the cache.
3.​ The cache block containing X is not brought into the cache.
■​ Example: If the CPU wants to write to address 0x1004, and it's a write miss,
the data is written directly to 0x1004 in main memory. The cache content
remains unchanged. This is useful for data that is written once and rarely
read, to avoid polluting the cache with transient data.
(Diagrams for each policy would show the data flow between CPU, Cache, and Main Memory
during a write miss, highlighting whether the block is brought into the cache or not.)