Scribd
Upload
4 views51 pages

MODULE_4.doc

The document provides an overview of ARM Embedded Systems, covering RISC design philosophy, ARM architecture, and embedded system hardware and software components. It details processor modes, instruction sets, pipeline execution, and core extensions such as cache and memory management. Additionally, it discusses the role of coprocessors in enhancing ARM core functionalities.

Uploaded by

prajwal24dsouza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
4 views51 pages

MODULE_4.doc

The document provides an overview of ARM Embedded Systems, covering RISC design philosophy, ARM architecture, and embedded system hardware and software components. It details processor modes, instruction sets, pipeline execution, and core extensions such as cache and memory management. Additionally, it discusses the role of coprocessors in enhancing ARM core functionalities.

Uploaded by

prajwal24dsouza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 51

Module-4

ARM Embedded Systems:


Introduction, RISC design philosophy, ARM design philosophy,
Embedded system hardware – AMBA bus protocol, ARM bus
technology, Memory, Peripherals, Embedded system software –
Initialization (BOOT) code, Operating System, Applications.
ARM Processor Fundamentals, ARM core dataflow model, registers,
currentprogramstatusregister,Pipeline,Exceptions,Interruptsand
Vector Table, Core extensions.

Textbook2:Chapter1,2
ARMEmbeddedSystems:

Introduction
​TheRISCdesignphilosophy

Figure1.1 CISC vs.RISC.CISC emphasizes hardware complexity.RISC emphasizes compiler


complexity.
The RISC philosophy is implemented with four major design rules:
​ The ARM Design Philosophy
​ Instruction Set for Embedded Systems
​ Embedded System Hardware

Figure1.2 An example of an ARM-based embedded device,a microcontroller.


​ ARMBusTechnology
​ AMBABusProtocol
Hierarchy
Types
Peripherals
TheTypicalEmbeddedSystem

Real World
​
​
CurrentProgramStatusRegister
​ ProcessorModes
•​ Each processor mode is either privileged or
nonprivileged:
​ A privileged mode allows full read-write access to
the cpsr.
​ A non privileged mode only allows read access to
the control field in the cpsr but still allows read-
write access to the condition flags.
•​ Therearesevenprocessormodesintotal:
1.​ Six privileged modes (abort, fast interrupt request,
interrupt request, supervisor, system, and
undefined)
2.​ One non privileged mode(user).
2.2.1ProcessorModes
•​ The processorenters abort mode when there is a failed
attempt to access memory.
•​ Fast​ interrupt​ request​ and​ interrupt​ request​ modes
Correspond to the two interrupt levels available on the
ARM processor.
•​ Supervisor mode is the mode that the processor is in after
reset and is generally the mode that an operating system
kernel operates in.
•​ System mode is a special version of user mode that allows
Full read-write access to the cpsr.
•​ Undefined mode is used when the processor encounters
an instruction that is undefined or not supported by the
implementation.
•​ Usermode is used for programs and applications.
​ ProcessorModes
​ Banked Registers
​ State and Instruction Sets
•​ The state of the core determines which instruction set is being
executed. There are three instruction sets: ARM, Thumb, and
Jazelle.
•​ The ARM instruction set is only active when the processor is in
ARM state.
•​ The JazelleJ andThumbT bits in the cpsr reflect the state of the
processor.
•​ When both JandT bits are 0,the processor is in ARM state and
executes ARM instructions.
•​ When theT bit is1,then the processor is inThumb state.
•​ Table2.2 compares the ARM and Thumb instruction set features.
•​ The ARM designers introduced a third instruction set called Jazelle.
Jazelle executes 8-bit instructions and is a hybrid mix of software
and hardware designed to speed up the execution of Java byte
codes.
​ StateandInstructionSets
​ Interrupt Masks
•​ Interrupt masks are used to stop specific
interrupt requests from interrupting the
processor.
•​ There are two interrupt request levels available
on the ARM processor core—interrupt request
(IRQ) and fast interrupt request (FIQ).
•​ The cpsr has two interrupt maskbits,7and6(orI
and F), which control the masking of IRQ and FIQ,
respectively.
​ ConditionFlags
•​ Condition flags are updated by comparisons and the result of
ALU operations that specify the S instruction suffix.
•​ For example, if a SUBS subtract instruction results in a register
value of zero, then the Z flag in the cpsr is set.
•​ This particular subtract instruction specifically updates the
cpsr.
​ Conditional Execution
2.3 Pipeline
•​ A pipeline is the mechanism a RISC processor uses to execute
instructions.
•​ Using a pipeline speeds up execution by fetching the next instruction
While other instructions are being decoded and executed.
•​ ​One way to view the pipeline is to think of it as an automobile
assembly line, with each stage carrying out a particular task to
manufacture the vehicle.

■​ Fetch loads an instruction from memory.


■​ Decode identifies the instruction to be executed.
■​ Execute processes the instruction and writes the result back to
a register.
2.3Pipeline
​ Pipeline
​ PipelineExecutingCharacteristics
•​ The ARM pipeline has not processed an instruction until it passes
Completely through the execute stage.
2.3.1Pipeline Executing Characteristics
​Exceptions,Interrupts,andtheVectorTable

•​ When an exception or interrupt occurs, the processor sets the pc to a specific


memory address. The address is within a special address range called the
vector table. The entries in the vector table are instructions that branch to
specific routines designed to handle a particular exception or interrupt.
•​ When an exception or interrupt occurs, the processor suspends normal
execution and starts loading instructions from the exception vector table (see
Table 2.6). Each vector table entry contains a form of branch instruction
pointing to the start of a specific routine:
​ Core Extensions
•​ The hardware extensions covered in this section are standard
Components placed next to the ARM core.
•​ They improve performance, manage resources, and provide
extra functionality and are designed to provide flexibility in
handling particular applications.
•​ Each ARM family has different extensions available.
•​ There are three hardware extensions ARM wraps around the
core:
1.​ Cache
2.​ Tightly coupled memory,memory management,
3.​ The co-processor interface.
​ Cache and Tightly Coupled Memory
•​ The cache is a block of fast memory placed between main
Memory and the core.
•​ It allows for more efficient fetches from some memory types.
•​ With a cache the processor core can run for the majority of the
time without having to wait for data from slow external
memory.
•​ Most ARM-based embedded systems use a single-level cache
Internal to the processor.
•​ Of course,many small embedded systems do not require the
Performance gains that a cache brings.
•​ ARM has two forms of cache.
•​ The first is found attached to the Von Neumann–style cores. It
combines both data and instruction into a single unified cache,
as shown in Figure 2.13.
•​ For simplicity,we have called the glue logic that connects the
Memory system to the AMBA bus logic and control.
​ Cache and Tightly Coupled Memory
​ Memory Management
•​ Embedded systems often use multiple memory
devices.
•​ It is usually necessary to have a method to help
organize these devices and protect the system from
applications trying to make inappropriate accesses to
hardware.
•​ This is achieved with the assistance of memory
Management hardware.
•​ ARM cores have three different types of memory
management hardware—no extensions providing no
protection,a memory protection unit(MPU)providing
limited protection, and a memory management unit
(MMU) providing full protection:
​ Coprocessors
•​ Coprocessors can be attached to the ARM processor. A
coprocessor extends the processing features of a core by
extending the instruction set or by providing configuration
registers.
•​ More than one co-processor can be added to the ARM core via
The coprocessor interface.
•​ The coprocessor can be accessed through a group of
dedicated ARM instructions that provide a load-store type
interface.
•​ Consider,for example,coprocessor15:TheARMprocessor
uses co-processor 15 registers to control the cache, TCMs, and
memory management.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy