FPGA Programming Handcode Framework

Guide
For FPGA Programming Blockset 2024-A

Release 2024-A – May 2024

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 Contents

Contents

About This Guide 5

Introduction 7
FPGA Basics...................................................................................... .............. 8
Basics on the System Architecture..................................................... .............. 9
Components of the FPGA Programming Blockset.......................................... 10
Basics on Exchanging Data Between Processor and FPGA.............................. 11
Exchanging Data With the Processor Model................................................... 13
Software Tools for Working With the FPGA Programming Handcode
Framework.................................................................................................... 17
Supported Hardware..................................................................................... 19
Typical Workflow for FPGA Handcoding........................................................ 25
Modeling Aspects............................................................................. ............ 26

Detailed Instructions on the Handcode Workflow 29

Preparing Your Environment.......................................................................... 30
Specifying the FPGA I/O Interface.................................................................. 30
Configuring the FPGA Code With the Specified I/O Interface......................... 32
Specifying the FPGA Functionality.................................................................. 33
How to Build the FPGA Application............................................................... 37
Generating an FPGA Model INI File/FPGAC File.............................................. 39
Using the FPGA Model INI File for the Processor Interface.............................. 40

Using RTI to Implement the Processor Interface 43

Modeling the Processor Communication.................................................... ............ 44
How to Generate a Processor Model Interface............................................... 44
How to Trigger Interrupt-Driven Tasks............................................................ 46

Working with the Processor Model......................................................................... 47

Simulating a Processor Model........................................................................ 47
How to Build a Processor Application............................................................ 48
How to Create Burn Applications for MicroAutoBox II....................... ............ 49

Using RTLib to Implement the Processor Interface 53

Handcoding the Processor Interface............................................................... 54
How to Extract Bitstream Files from FPGA Model INI Files.................. ............ 56

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 Contents

How to Include Bitstream Files to Handcoded Processor Applications............. 57

How to Download FPGA Applications and Program the FPGA........... ............ 58

Running Processor and FPGA Applications on the Real-

Time Hardware 61
Experimenting with an FPGA Application....................................................... 61

Features Provided by Specific FPGA Boards 63

Handcoding Inter-FPGA Communication.................................................... ............ 64

Introduction to Inter-FPGA Communication........................................................ 64

Overview of Inter-FPGA Communication........................................................ 64

Handcoding Inter-FPGA Communication via IOCNET.......................................... 66

Implementing Inter-FPGA Communication via IOCNET................................... 66
Calculating the Latency (IOCNET).................................................................. 67

Handcoding Inter-FPGA Communication via MGT Modules................................ 69

Implementing Inter-FPGA Communication via MGT Modules......................... 69

Handcoding Inter-FPGA Communication via I/O Module Slots............................ 70

Implementing Inter-FPGA Communication via I/O Module Slots..................... 70
How to Determine the Bit Ranges for Inter-FPGA Subbuses Between
SCALEXIO FPGA Base Boards......................................................................... 75
Calculating the Data Rate and Latency (SCALEXIO)........................................ 78

MicroLabBox: Using Remaining I/O Channels with RTI/RTLib................................... 81

Features of the MicroLabBox Flexible I/O Framework......................... ............ 81
Workflow when Using MicroLabBox Flexible I/O Framework.......................... 82

DS6602: Accessing the DDR4 RAM........................................................................ 84

Accessing the DDR4 RAM of the DS6602...................................................... 84
Initializing the DDR4 RAM of the DS6602...................................................... 85

DS6601, DS6602: Coding a Customized MGT Protocol ......................................... 87

Customizing MGT Protocols.......................................................................... 87

DS6601, DS6602: Configuring the Timeout of a Watchdog I/O Function................ 89

How to Configure the Condition when the Watchdog Expires....................... 89

Troubleshooting 93
Problems and Their Solutions......................................................................... 93

Index 95

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 About This Guide

About This Guide

Introduction This guide provides information about the FPGA Programming Handcode
Framework implementation flow. You will learn how to implement an FPGA
application for dSPACE FPGA hardware. You will also learn how to access the
FPGA application from a processor application running on a processor board.

Audience profile It is assumed that you have good knowledge in:

§ Applying generally accepted FPGA design rules to ensure a stable and reliable
FPGA application.
§ The architectural structure of FPGAs (CLB architecture, slice flip-flops, memory
resources, DSP resources, clocking resources) with a verifiable experience on
digital designs (structural mapping, tool-flow knowledge, synthesis options,
timing analysis).
§ Verifiable experience on implementing HDL code (VHDL or Verilog).
§ Implementing FPGA designs with AMD® FPGA design tools.

Symbols dSPACE user documentation uses the following symbols:

Symbol Description
Indicates a hazardous situation that, if not avoided,
V DANGER
will result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V WARNING could result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V CAUTION could result in minor or moderate injury.
Indicates a hazard that, if not avoided, could result in
NOTICE
property damage.
Indicates important information that you should take
Note
into account to avoid malfunctions.
Indicates tips that can make your work easier.
Tip

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 About This Guide

Symbol Description
Indicates a link that refers to a definition in the
glossary, which you can find at the end of the
document unless stated otherwise.
Follows the document title in a link that refers to
another document.

Naming conventions dSPACE user documentation uses the following naming conventions:

%name% Names enclosed in percent signs refer to environment variables for

file and path names.

<> Angle brackets contain wildcard characters or placeholders for variable

file and path names, etc.

Special Windows folders Windows‑based software products use the following special folders:

Common Program Data folder A standard folder for application-specific

program data that is used by all users.
%PROGRAMDATA%\dSPACE\<InstallationGUID>\<ProductName>
or
%PROGRAMDATA%\dSPACE\<ProductName>\<VersionNumber>

Documents folder A standard folder for application‑specific files that are

used by the current user.
%USERPROFILE%\Documents\dSPACE\<ProductName>\<VersionNumber>

Local Program Data folder A standard folder for application-specific

program data that is used by the current user.
%USERPROFILE%\AppData\Local\dSPACE\<InstallationGUID>\
<ProductName>

Accessing dSPACE Help and After you install and decrypt Windows‑based dSPACE software, the
PDF files documentation for the installed products is available in dSPACE Help and as PDF
files.

dSPACE Help (local) You can open your local installation of dSPACE Help:
§ On its home page via Windows Start Menu
§ On specific content using context-sensitive help via F1

PDF files You can access PDF files via the icon in dSPACE Help. The PDF
opens on the first page.

dSPACE Help (Web) Independently of the software installation, you can

access the Web version of dSPACE Help at https://www.dspace.com/go/help.
To access the Web version, you must have a mydSPACE account.
For more information on the mydSPACE registration process, refer to
https://www.dspace.com/faq?097.

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FPGA Programming Handcode Framework Guide May 2024
 Introduction

Introduction

Basic feature of the The FPGA Handcode Framework allows you to integrate a custom, code‑based
framework FPGA application in a dSPACE hardware and software environment.

Where to go from here Information in this section

FPGA Basics............................................................................................... 8
General information on FPGAs.

Basics on the System Architecture.............................................................. 9

The system architecture determines the signals your FPGA applications
can read, process and update. It shows the data flow to download
applications and to analyze data.

Components of the FPGA Programming Blockset.................................... 10

The FPGA Programming Blockset is a Simulink blockset for integrating an
FPGA application into a dSPACE system.

Basics on Exchanging Data Between Processor and FPGA........................ 11

Only the processor application initiates data exchange between the real-
time processor and the FPGA. To be able to exchange data, the processor
interface provides different data storages.

Exchanging Data With the Processor Model............................................. 13

Modeling the data exchange between the FPGA application and the
processor application depends on the hardware used.

Software Tools for Working With the FPGA Programming

Handcode Framework............................................................................. 17
Information about the required software tools.

Supported Hardware............................................................................... 19
Overview of the supported hardware.

Typical Workflow for FPGA Handcoding................................................... 25

Describes the typical workflow to handcode an FPGA application by
using the FPGA Programming Handcode Framework.

Modeling Aspects.................................................................................... 26
Describes general modeling aspects that have no particular context.

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 Introduction

FPGA Basics

FPGA architecture FPGA stands for Field Programmable Gate Array. It is used in digital technology
to allow modifications in a circuit's functionality without replacing hardware. A
specific circuit is implemented as a specific configuration of the internal logic
cells. The configurable logic blocks (CLBs) are connected with each other via
switch boxes. The external connection is realized by I/O pins.

Reasons for using FPGAs The main advantages of an FPGA are its flexibility and high speed for signal
processing:
§ Flexibility
You can implement any kind of circuit, from a simple counter to an entire
microprocessor.
You can reconfigure your implementation in the development phase without
hardware changes.
§ Speed
The specific implementations are usually concentrated on one functionality
without any overhead.
The bit architecture is often more efficiently than the word architecture with a
fix data width.
Execution can be done in parallel which results in a high throughput.
Control loops (input of data, result calculation, output of data) can usually
be performed at higher overall sample rates on an FPGA than on non-FPGA
platforms.

Fields of application All of the above-mentioned features of an FPGA are very useful for function
prototyping, which can be performed with dSPACE hardware and software.

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 Basics on the System Architecture

FPGAs are used, if you have a task that cannot be solved by standard
implementations. They are used for tasks that require high performance, for
example, for complex signal processing, or if you want to move some of your
model's functionality to a separate application.

Basics on the System Architecture

Introduction The system architecture determines the signals your FPGA applications can read,
process, and update. It shows the data flow to download applications and to
analyze data.

Components of a dSPACE The following illustration shows you the components and the signal connections
system and their connections of a dSPACE system, such as a MicroAutoBox III.

dSPACE system

Real-time I/O
Host PC processor channels

External
device

FPGA I/O
channels

Description of the elements shown in the illustration:

§ Host PC
With the host PC, you download the processor and FPGA application. You
can use dSPACE software installed on the host PC to experiment with your
real-time application.
§ Real-time processor
The real-time processor executes your processor application. It initiates sending
and receiving data to/from the FPGA via a board-specific bus. The real-time
processor can also be connected to its own I/O channels to provide I/O
functionality independently of the FPGA.
§ FPGA
The FPGA processes your FPGA application (FPGA logic implementation). The
FPGA is connected to its own I/O channels to process I/O signals independently
of the real-time processor. If the real-time processor initiates data exchange,
the FPGA sends and receives data to/from a board-specific bus.

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 Introduction

§ I/O channels
To access the external I/O signals of the external device, the signals must be
converted so that they meet the requirements of the connected components.
This is done, for example, by filters, signal amplifiers or analog-to-digital
converters.
§ External device
Device that can be connected to the dSPACE system, such as an ECU.

Components of the FPGA Programming Blockset

Introduction The FPGA Programming Blockset is a Simulink blockset for integrating an FPGA
application into a dSPACE system. It provides Simulink blocks for implementing
the interface between the FPGA and the real-time processor. Furthermore, script
functions let you execute functions via command line or M file.

Overview of the blockset Processor interface

board-specific bus

PROC_XDATA_READ_BL

Processor
model

PROC_XDATA_WRITE_BL

FPGA logic

I/O channel

Processor interface Processor interface when using a MicroAutoBox II or a

MicroLabBox The Simulink blocks of the Processor Interface library are
used to implement processor communication with the FPGA via the board-
specific bus. They access the data storage that you configured in the FPGA
model. The setup block of the Processor Interface library lets you automatically
generate the interface blocks for the processor model.

Processor interface when using MicroLabBox II, MicroAutoBox III, or a

SCALEXIO system When you use a MicroLabBox II, MicroAutoBox III, or a
SCALEXIO system, the Processor Interface library is not required. Instead, you
implement the data exchange between the FPGA model and the processor
model with ConfigurationDesk. This represents a connection to the real-time
processor in your FPGA model by a function port that you can connect to a
related model port block.

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 Basics on Exchanging Data Between Processor and FPGA

For details on adding FPGA applications to the signal chain in ConfigurationDesk,

refer to Adding FPGA Applications to the Signal Chain (ConfigurationDesk Real-
Time Implementation Guide ).

Available script functions The FPGA Programming Blockset comes with script functions for executing
functions via command line or M file. You can use them, for example, to
initialize the framework. For more information on the script functions, refer to
Script Functions Supporting the FPGA Programming Handcode Framework (FPGA
Programming Software Script Interface Reference ).

Related topics Basics

Basics on Exchanging Data Between Processor and FPGA......................................................... 11

Exchanging Data With the Processor Model.............................................................................. 13

Basics on Exchanging Data Between Processor and FPGA

Introduction Only the processor application initiates a data exchange between the real-time
processor and the FPGA. To be able to exchange data, the processor interface
provides different data storages.

Provided data storage You can choose the data storage that you want to use for the data exchange
with the following access types:
§ Register
Registers are implemented as flip-flops to exchange scalar values.
§ Register group
Register groups are implemented as flip-flops to exchange a data package
with synchronized elements.
§ Buffer
Buffers are implemented in the FPGA RAM to exchange data packages with a
buffer size of up to 32,768 elements.

For board-specific details on, such as data width or data format, refer to
Exchanging Data With the Processor Model on page 13.

Details on the access types Register access Register access lets you access a scalar value in the register.
The data is identified by the specified channel number. The values are
transmitted element by element.

Register group access You can group registers to a register group via a
common Register Group ID. All the values that belong to the same Register
Group ID are synchronously updated in the FPGA subsystem.

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 Introduction

For read access, the registers of a register group are read from the board-specific
bus sequentially and then provided to the FPGA application simultaneously. For
write access, the registers of a register group are sampled simultaneously in the
FPGA application. These values form a consistent data group that is written to
the board-specific bus.

Buffer access Buffer access lets you access a vector value in the data buffer.
One specific value of the data is identified by the specified channel number and
the position within the buffer.
Data exchange is implemented via a FIFO buffer that works as a swinging buffer.
This means that there are two separate buffers for reading and writing, and
one buffer that switches between reading and writing. Only the pointer has to
be changed to switch the buffer so that no buffer has to be copied from one
position to another.

Free buffer

Application Read buffer Write buffer FPGA application

running on the
processor board

Processing the data exchange Only the processor application can initiate data exchange between the real-time
processor and the FPGA. The following illustration shows you the main steps that
a processor task performs.

Processor task
From external device To external device
Read Process Update
inputs model outputs

From FPGA To FPGA

From external device To external device

FPGA

The FPGA executes its operations in parallel because the FPGA application is a
logic implementation: i.e., the execution time of an FPGA is much faster than the
execution time of the real-time processor.

Several processor tasks with different task periods can request read/write access
to the FPGA at different points in time. These read/write requests are executed
by the FPGA in parallel. The following illustration shows you the read/write
requests of a real-time application with two processor tasks.

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 Exchanging Data With the Processor Model

Read Read Read Compute Write Read Read Read Compute Write Read
Processor FPGA FPGA FPGA model of
Write
FPGA FPGA FPGA FPGA model of
Write
FPGA FPGA
Idle Idle
task 1 FPGA FPGA
Reg1 Reg3 Reg7 task 1 Reg9 Reg1 Reg3 Reg7 task 1 Reg9 Reg1
Reg4 Reg4

t Task 1 t Task 1

Processor Read Read Compute Write Read Read Compute Write Read Read Compute Write
FPGA FPGA model of FPGA Idle FPGA FPGA model of FPGA Idle FPGA FPGA model of FPGA Idle
task 2 Reg2 Reg4 task 2 Reg8 Reg2 Reg4 task 2 Reg8 Reg2 Reg4 task 2 Reg8

t Task 2 t Task 2 t Task 2

Related topics Basics

Exchanging Data With the Processor Model.............................................................................. 13

Exchanging Data With the Processor Model

Introduction Modeling the data exchange between the FPGA application and the processor
application depends on the hardware used.

Basics on the processor The data is exchanged via the communication line between MicroLabBox's
communication using base board and the I/O FPGA module mounted on the DS1302 board.
MicroLabBox/MicroLabBox II For MicroLabBox, communication runs via the local bus. For MicroLabBox II,
communication runs via IOCNET.

The 32‑bit parallel data bus enables a complete 32‑bit word to be transferred in
a single operation. For transferring a 64‑bit word, two operations are internally
required.

The data is transmitted via the local bus to specific data storage areas. The
implementation details of these storage areas are defined in the framework.

Data Data Data Storage Size Data Format

Storage Width
Area
Register 32 bit 256 32-bit registers Can be specified to fixed-point or floating-point format.
64 bit and 256 64-bit § Fixed-point format:
registers Signed or unsigned data format with adjustable binary point
Buffer 32 bit 32 32-bit buffers and position.
32 64-bit buffers MicroLabBox: 64-bit fixed-point data types are converted to double.
Each buffer with up to Therefore, the fixed-point resolution of fixed-point data types is
32,768 elements restricted to 53 bits.
MicroLabBox II: 64-bit fixed-point data types are converted to
double, except the data type without a binary point (binary point

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 Introduction

Data Data Data Storage Size Data Format

Storage Width
Area
64 bit position = 0). Therefore, the fixed-point resolution of fixed-point
data types with a binary point (binary point position > 0) is restricted
to 53 bits.1)
§ 32-bit floating-point format:
Single precision (IEEE 754 standard) data format with a fraction
width of 24.
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction
width of 53.
1) The default data type of generated processor interface blocks is always double. To use
the full resolution of a 64-bit fixed-point data type, you have to set the data type of the
generated blocks to int64 or uint64.

Basics on the processor The data is exchanged via the communication line between the real-time
communication using processor of the MicroAutoBox II/III and the FPGA module mounted on the
MicroAutoBox II/III DS1514 I/O board. The communication runs via the intermodule bus of the
MicroAutoBox II/IIII.

The 16‑bit parallel data bus enables a complete 16‑bit word to be transferred in
a single operation.

The data is transmitted via the intermodule bus to specific data storage areas.
The implementation details of these storage areas are defined in the framework.

Data Data Data Storage Size Data Format

Storage Width
Area
Register 32 bit 128 32‑bit registers and Can be specified to fixed-point or floating-point format.
64 bit 128 64‑bit registers § Fixed-point format:
Signed or unsigned data format with adjustable binary point
Buffer 32 bit 32 32‑bit buffers and
position
64 bit 32 64‑bit buffers
64-bit fixed-point data types are converted to double. Therefore,
Each buffer with up to
the fixed-point resolution of fixed-point data types is restricted to
32,768 elements
53 bits.
§ 32-bit floating-point format:
Single precision (IEEE 754 standard) data format with a fraction
width of 24
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction
width of 53

Basics on the processor The internal communication between the real-time processor and a SCALEXIO
communication using a FPGA base board runs via IOCNET (I/O carrier network). IOCNET lets you connect
SCALEXIO system more than 100 I/O nodes and even place the parts of your SCALEXIO system

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 Exchanging Data With the Processor Model

long distances apart. IOCNET is dSPACE's proprietary protocol that gives you
real-time performance plus time and angular clocks.

The data is transmitted via IOCNET to specific data storage areas. The
implementation details of these storage areas are defined in the framework.

Data Data Data Storage Size Data Format

Storage Width
Area
Register 32 bit 256 32-bit registers Can be specified to fixed-point or floating-point format.
64 bit and 256 64-bit § Fixed-point format:
registers Signed or unsigned data format with adjustable binary point
Buffer 32 bit 32 32-bit buffers and position.
64 bit 32 64-bit buffers 64-bit fixed-point data types are converted to double, except the
Each buffer with up to data type without a binary point (binary point position = 0).
32,768 elements Therefore, the fixed-point resolution of fixed-point data types with a
binary point (binary point position > 0) is restricted to 53 bits.1)
§ 32-bit floating-point format:
Single precision (IEEE 754 standard) data format with a fraction
width of 24.
§ 64-bit floating-point format:
Double precision (IEEE 754 standard) data format with a fraction
width of 53.
1) The default data type of generated processor interface blocks is always double. To use
the full resolution of a 64-bit fixed-point data type, you have to set the data type of the
generated blocks to int64 or uint64.

Access types You can select different access types for data exchange.

Register access type If you have to exchange certain data and high
performance is not required, it is recommended to use the register access type.

Note

Notes only for MicroLabBox II, MicroAutoBox III, and SCALEXIO:

§ Any specified register that does not belong to a group is automatically
collected in one single group called Ungrouped in the FPGA custom
function built for ConfigurationDesk. There is one group for register input
data and one group for register output data. Independently of the groups
specified in your FPGA model, the ungrouped registers are automatically
grouped in the Simulink model tasks in ConfigurationDesk to increase the
performance of IOCNET transfers.
§ You can access a register group by one task only.

Buffer access type If you have to exchange a lot of data with high
performance, it is recommended to use the buffer access type. However, to
access a specific data item within the buffer, you have to address it explicitly.

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 Introduction

Read/write access in the FPGA The selected FPGA framework provides specific read and write functions that
application exchange data via the board-specific bus to the processor model. For instructions
on implementing these functions, refer to Specifying the FPGA I/O Interface on
page 30. For information on the available read and write functions, refer to
FPGA Programming Handcode Framework - FPGA Interface Reference .

The values in the FPGA application are processed as fixed-point values. The
data exchange with the processor model requires data type conversion between
fixed-point and floating-point values. Data conversion is automatic in these I/O
functions. The fixed-point format to be used can be set as an I/O function
parameter.

Read/write access in the If you use a MicroAutoBox II or a MicroLabBox you can implement the processor
processor model interface with interface blocks of the FPGA Programming Blockset or with data
exchange functions of board-specific Real-Time Libraries (RTLib).

If you use a MicroAutoBox III, MicroLabBox II or SCALEXIO system, you

implement the processor interface in ConfigurationDesk.

Using the FPGA Programming Blockset The Processor Interface library

of the FPGA Programming Blockset provides the PROC_XDATA_READ_BL and
PROC_XDATA_WRITE_BL blocks to read data from and write data to the board-
specific bus. These blocks must be configured as counterparts to the related I/O
functions in the FPGA application. The simplest way to create and configure
these blocks in the processor model is to use the Generate command from the
Interface page in the PROC_SETUP_BL block dialog.
For detailed instructions, refer to How to Generate a Processor Model Interface
on page 44.

Using the Real-Time Library The board-specific RTLib provides C functions

for data exchange to handcode the processor interface in the processor
application.
Refer to the following function references:
§ MicroAutoBox II: Data Exchange Functions (MicroAutoBox II RTLib
Reference )
§ MicroLabBox: Data Exchange Functions (MicroLabBox RTLib Reference )

Using ConfigurationDesk Model port blocks provide the interface to

exchange data between the processor application (behavior model) and the
FPGA application. Refer to Adding FPGA Applications to the Signal Chain
(ConfigurationDesk Real-Time Implementation Guide )

Related topics Basics

Basics on Exchanging Data Between Processor and FPGA......................................................... 11

Components of the FPGA Programming Blockset..................................................................... 10

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 Software Tools for Working With the FPGA Programming Handcode Framework

Software Tools for Working With the FPGA Programming Handcode

Framework

Introduction To work with the FPGA Programming Handcode Framework, several software
tools are necessary.

Tools from MathWorks® MATLAB®, Simulink® and Simulink® CoderTM are used for modeling the
processor application, which can be simulated in Simulink and executed on the
real-time hardware.

For compatibility information, refer to Required MATLAB Releases (Installing

dSPACE Software ).

Tools from AMD AMD provides several tools for designing applications for AMD FPGAs. The
Vivado® Design Suite covers all the aspects of designing FPGAs. Working with
the FPGA Programming Blockset requires the following products:

Vivado Design Suite The Vivado Design Suite provides a logic design
environment for AMD FPGAs. It contains tools and wizards, for example, for I/O
assignment, power analysis, timing-driven design closure, and HDL simulation.
With the Vivado software, you can build the FPGA application according to the
handcoded FPGA design.

Ordering AMD software Currently, you cannot order the AMD software
from dSPACE. Install the AMD software before or after installing dSPACE
software and follow the installation instructions from the AMD manuals.

Supported software versions The following table shows you the supported products and their software
versions for the current version of the FPGA Programming Blockset.

Design Tool Version MATLAB Operating System

Version1)
AMD Vivado 2023.22) MATLAB Windows operating system that is supported by the RCP and HIL software
R2022b of the current Release.
For a list of supported operating systems, refer to Operating System (New
Features and Migration ). The listed Windows Server operating systems
are not supported by AMD.
1) The Processor Interface sublibrary of the FPGA Programming Blockset also supports
MATLAB R2023a, R2023b, and R2024a.
2)
In general, Vivado ML Enterprise edition and the AMD Vitis Model Composer are
needed. The Vivado ML Standard edition with AMD Vitis Model Composer can also be
used for the DS2655 (7K160) and DS6601 FPGA base boards. The AMD Vitis Model
Composer is required only for modeling FPGA applications with the FPGA Programming
Blockset.

For software versions that are compatible with older versions of the FPGA
Programming Blockset, refer to https://www.dspace.com/faq?295.

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 Introduction

MATLAB compatibility The limited MATLAB compatibility reflects the

requirements of the AMD Design Tools and its impacts on the building processes
for creating an FPGA application.
In contrast to the FPGA build process, the blocksets and tools for modeling and
building the processor application support the regular MATLAB compatibility of
a dSPACE Release. Therefore, you can extend the MATLAB compatibility if you
model and build the processor application separately from the FPGA application.
The only requirement is that the same dSPACE Release is used to build the FPGA
application and the processor application.
For example: The FPGA application is created with an installation set containing
the current dSPACE Release, Vivado 2023.2, and MATLAB R2022b. You can
transfer and import the generated FPGA application to an installation set
containing the current dSPACE Release and MATLAB R2024a to continue your
work with ConfigurationDesk or the Processor Interface sublibrary of the FPGA
Programming Blockset.

Required blocksets for the The MicroLabBox II, MicroAutoBox III, and SCALEXIO require the dSPACE Model
processor model Interface Package for Simulink to implement the interface between the real-
time processor and the FPGA. The Model Interface Package for Simulink is the
blockset for specifying all interfaces of processor models (behavior models) used
in ConfigurationDesk.

For the MicroAutoBox II and MicroLabBox the FPGA Programming Blockset

includes a Processor Interface blockset that you can use in the processor
model.

ConfigurationDesk ConfigurationDesk is the required dSPACE implementation tool for the

MicroLabBox II, MicroAutoBox III, or SCALEXIO system. ConfigurationDesk lets
you implement I/O functionality, bus communication, and the connection to
processor models and FPGA applications. ConfigurationDesk is used to build
the real-time application that includes the FPGA application and runs on the
MicroLabBox II/MicroAutoBox III/SCALEXIO.

ControlDesk ControlDesk is the dSPACE software tool for experimenting with a dSPACE
system. It can be used to register the connected hardware, to manage the
simulation platform, to download the real-time application (processor and FPGA
application), and to control the experiment. The great variety of instruments
allows you to access and visualize variables of the processor application.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

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 Supported Hardware

Supported Hardware

Introduction FPGA frameworks are available for the following dSPACE boards.

MicroLabBox Internally, MicroLabBox consists of the two boards DS1202 and DS1302. The
DS1302 board provides the FPGA capabilities.

MicroLabBox's I/O FPGA module provides channels for analog input and
output, digital input and output, and bus communication. The DS1302 board
of MicroLabBox provides an FPGA unit with an AMD FPGA that can be
programmed by using the FPGA Programming Software.

An FPGA application is automatically integrated into a MicroLabBox application

when building.

Note

dSPACE also provides RTI blocksets and real-time libraries (RTLib) for
MicroLabBox. To use I/O functions from the FPGA Programming Blockset
and RTI blocksets/RtLib for MicroLabBox in the same application, you have
to use the flexible I/O framework for MicroLabBox. Refer to Features of the
MicroLabBox Flexible I/O Framework on page 81.

The following table shows the main features of MicroLabBox's I/O FPGA:

Feature Description
Programmable FPGA § AMD® Kintex®-7 XC7K325T
§ 326,080 logic cells
§ 50,950 slices
§ 4,000 kbit distributed RAM (max.)
§ 840 DSP slices
§ 16,020 kbit block RAM
§ 100 MHz hardware clock frequency
Analog input § ADC (Class 1): 24 parallel A/D converters with 16-bit resolution and a sample rate of
1 MS/s.
§ ADC (Class 2): 8 parallel A/D converters with 16-bit resolution and a sample rate of
10 MS/s.
Analog output DAC (Class 1): 16 parallel D/A converters with 16-bit resolution.
Digital I/O § Digital InOut (Class 1): 48 digital bidirectional channels, single‑ended.
§ Digital InOut (Class 2): 8 digital bidirectional channels, differential.
Resolver interface 2 resolver interfaces that support resolvers with an excited single coil.
Serial interface 2 UART (RS232) and 2 UART (RS422/485) interfaces.
The UART (RS422/485) function supports full‑duplex mode and half‑duplex mode.
Feedback elements § Status In: State of the initialization sequence that is started after programming the FPGA.
§ LED Out: 4 customizable LEDs.
§ Proc App Status: Execution state of the loaded executable application.

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For further information on the hardware, refer to General Data (MicroLabBox

Hardware Reference ).

MicroLabBox II Internally, the MicroLabBox II consists of the two boards DS1203 Processor Board
and DS1303 Multi-I/O Board. The DS1303 Multi-I/O Board provides the FPGA
capabilities.

The following table shows the main features of the MicroLabBox II:

Feature Description
Programmable § AMD® Kintex® UltraScale+TM XCKU15P-2FFVE1517E
FPGA § 1,143,450 system logic cells
§ 1,045,440 FlipFlops
§ 1,968 DSP slices
§ 9.8 Mbit maximum distributed RAM
§ 34.6 Mbit block RAM
§ 36.0 Mbit Ultra RAM
§ 125 MHz hardware clock frequency
Analog input § Analog In 23: Input channel to measure differential analog voltage signals in the range ±10 V
with max. 2 MS/s.
Number of channels: 24
§ Analog In 24: Input channel to measure differential analog voltage signals in the range ±1 V
or ±10 V with max. 5 MS/s.
Number of channels: 6
§ Analog In 25: Input channel to measure differential analog voltage signals in the range ±1 V
or ±10 V with max. 5 MS/s. A load can be activated.
Number of channels: 2
Analog output § Analog Out 19: Output channel to generate ground-based analog voltage signals in the range
±10 V with max. 2 MS/s.
Number of channels: 14
§ Analog Out 20: Output channel to generate analog signals. Each channel can be configured
to generate a ground-based signal (±10 V) or a transformer-coupled signal (±20 V AC) with
max. 5 MS/s.
Number of channels: 2
Digital I/O § Digital In/Out 14: Bidirectional channels to measure or generate ground-based digital signals.
Number of channels: 48
§ Digital In/Out 15: Bidirectional channels to measure or generate differential digital signals.
Number of channels: 12
Feedback § Status In: State of the initialization sequence that is started after programming the FPGA.
elements § LED Out: 1 customizable LED.
§ Proc App Status: Execution state of the loaded executable application.

For further information on the hardware, refer to MicroLabBox II Data Sheet

(MicroLabBox II Hardware Installation and Configuration ).

MicroAutoBox II/III The MicroAutoBox II/III consists of a board with the real-time processor and at
least one I/O board. An FPGA base board provides the FPGA and the interfaces
for adding different I/O modules.

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DS1514 FPGA Base Board The DS1514 FPGA Base Board provides an FPGA.
The following table shows the main features of the DS1514 FPGA Base Board.

Feature Description
Programmable FPGA § AMD Kintex®-7 XC7K325T
§ 326,080 logic cells
§ 50,950 slices
§ 4,000 kbit distributed RAM (max.)
§ 840 DSP slices
§ 80 MHz hardware clock frequency.
I/O interfaces I/O interfaces are provided by I/O modules that are installed to the FPGA base board. Refer to
I/O modules available for MicroAutoBox II/III on page 21.
Feedback elements § Status In: State of the initialization sequence that is started after programming the FPGA.
§ Temperature: Sensor to measure the FPGA's die temperature.
§ LED Out: 1 FPGA Status LED.

For further information on the hardware, refer to the following data sheets:
§ MicroAutoBox II 1401/1511/1514: General Data (MicroAutoBox II Hardware
Reference )
§ MicroAutoBox II 1401/1513/1514: General Data (MicroAutoBox II Hardware
Reference )
§ MicroAutoBox III: DS1514 FPGA Base Board Data Sheet (MicroAutoBox III
Hardware Installation and Configuration )

I/O modules available for I/O modules provide the I/O interface for the DS1514 FPGA Base Board. The
MicroAutoBox II/III following table shows the main features of the supported I/O modules:

Feature DS1552 Multi-I/O Module DS1552B1 Multi-I/O Module DS1554 Engine

Control I/O Module
Analog input § ADC (Type A), Analog In 101): 8 § ADC (Type A), Analog In 111): 8 ADC (Type A), Analog
parallel A/D converters with 16- parallel A/D converters with 16- In 141): 14 parallel
bit resolution and a conversion bit resolution and a conversion A/D converters with 16-
time of 1 µs, conversion can be time of 1 µs, conversion can be bit resolution and a
triggered. triggered. conversion time of 1 µs.
Input voltage range: 0 V ... +5 V Input voltage range: Input voltage range:
§ ADC (Type B), Analog In 121): 16 -10 V ... +10 V -10 V ... +10 V
parallel A/D converters with 16- § ADC (Type B), Analog In 121): 16
bit resolution and a conversion parallel A/D converters with 16-
time of 5 µs. Input voltage range: bit resolution and a conversion
-10 V ... +10 V. time of 5 µs. Input voltage range:
-10 V ... +10 V.
Analog ADC (Type B), Analog Out 131): ‑
output 16 parallel A/D converters with 16-bit resolution and a conversion time of
5 µs.
Input voltage range: -10 V ... +10 V
Digital I/O § Digital In (Type A), Digital In 51): 16 digital input channels. § Digital In (Type
§ Digital In (Type B)/Digital Out (Type B), Digital InOut 61): 8 digital B)/Digital Out (Type
bidirectional channels. B), Digital InOut 81):
§ Digital Out (Type A), Digital Out 5 1): 16 digital output channels.

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Feature DS1552 Multi-I/O Module DS1552B1 Multi-I/O Module DS1554 Engine

Control I/O Module
8 digital bidirectional
channels.
§ Digital Out (Type
A), Digital Out 7:
40 digital output
channels.
Digital 3 digital inputs to read digital camshaft and crankshaft sensors. 5 digital inputs to read
Crank/Cam digital camshaft and
input crankshaft sensors.
Inductive 1 digital input to read an inductive zero voltage detector.
zero voltage
detector
Knock signal ‑ 4 analog inputs to read
input knock sensors.
Serial 2 UART (RS232/422/485) interfaces. RS422/485 supports full‑duplex mode ‑
interface and half‑duplex mode.
UART 1 can be used without modification. To use UART 2, your DS1552
has to be modified by dSPACE.
Sensor supply 1 adjustable supply voltage in the voltage range 2 V ... 20 V. 1 supply voltage
providing 5 V.
1) The channel name depends on the framework.

For further information on the hardware, refer to the following data sheets.
§ MicroAutoBox II:
§ Data Sheet DS1552 Multi-I/O Module (MicroAutoBox II Hardware
Reference )
§ Data Sheet DS1554 Engine Control I/O Module (MicroAutoBox II Hardware
Reference )
§ MicroAutoBox III:
§ DS1552 Multi-I/O Module Data Sheet (MicroAutoBox III Hardware
Installation and Configuration )
§ DS1554 Engine Control I/O Module Data Sheet (MicroAutoBox III Hardware
Installation and Configuration )

SCALEXIO system A SCALEXIO system consists of SCALEXIO processing hardware and a selection
of I/O boards. The SCALEXIO processing hardware, such as a SCALEXIO Real-
Time PC, provides the computation power of the system.

I/O boards are available for the various requirements, for example, for accessing
analog input and output signals, digital input and output signals, and bus
communication.

With the SCALEXIO FPGA base boards, you can integrate an FPGA application
into a SCALEXIO system. The board provides an FPGA that you can program
using the FPGA Programming Blockset.

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The following table shows the main features of the supported SCALEXIO FPGA
base boards.

Feature DS2655 (7K160) DS2655 (7K410) DS6601 DS6602

Programmable AMD® KINTEX®-7-160T AMD® KINTEX®-7-410T AMD® KINTEX® AMD® KINTEX®
FPGA § 162,240 logic cells § 406,720 logic cells UltraScale™ KU035 UltraScale+™ KU15P
§ 600 DSP slices § 1,540 DSP slices § 444,343 system § 1,143,450 system
logic cells logic cells
§ 2,188 kbit maximum § 5,663 kbit maximum
distributed RAM distributed RAM § 1,700 DSP slices § 1,968 DSP slices
§ 11,700 kbit total § 28,620 kbit total § 5,908 kbit § 9,800 kbit
block RAM block RAM maximum maximum
distributed RAM distributed RAM
§ 125 MHz hardware § 125 MHz hardware
clock frequency clock frequency § 19,000 kbit total § 34,600 kbit total
block RAM block RAM
§ 125 MHz hardware § 36,000 kbit
clock frequency UltraRAM
§ 125 MHz hardware
clock frequency
I/O interfaces I/O interfaces are provided by up to 5 I/O modules that are installed to the SCALEXIO FPGA base
board. Refer to I/O modules available for SCALEXIO FPGA base board on page 23.
Angular § APU Master: You can write angle-based time base values to the IOCNET bus with up to 6
processing units angular processing units of the SCALEXIO FPGA base board. Other boards connected to the
APU bus as APU slaves can read the corresponding time base value.
§ APU Slave: You can read angle-based time base values from the IOCNET with up to 6 angular
processing units of the SCALEXIO FPGA base board. Another board connected to the IOCNET is
specified as the APU master and writes the time base value.
MGT interface ‑ 1 Multi-Gigabit Transceiver (MGT) interface
with 4 bidirectional lanes that can be used for
communication with external devices or with
other DS6601/DS6602 FPGA Base Boards.
To support MGT communication, an MGT
module must be installed to the FPGA base
board.
Inter-FPGA Direct data exchange with other SCALEXIO FPGA base boards via inter-FPGA communication bus.
communication
Interrupt lines 8 16
Feedback § Status In: State of the initialization sequence that is started after programming the FPGA.
elements § CN App Status: Execution state of the loaded executable application on the computation node.
§ IOCNET Global Time: Time that is specified for all modules connected to IOCNET.
§ LED Out: 1 FPGA Status LED.

For further information on the hardware, refer to Hardware for FPGA

Applications (SCALEXIO Hardware Installation and Configuration ).

I/O modules available for I/O modules provide the I/O interface for the SCALEXIO FPGA base boards
SCALEXIO FPGA base board DS2655, DS6601, and DS6602. The following table shows the main features
of the supported I/O modules:

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Feature DS2655M1 DS2655M2 DS6651

Analog Analog In: 5 analog ‑ A total of 6 analog input channels with
input input channels with 14‑bit 16‑bit resolution and 5 MS/s sample rate:
resolution and 4 MS/s § 4 Analog In channels
sample rate.
§ 2 Analog In-L channels with a
switchable load.
All channels can be triggered by different
trigger sources.
Analog Analog Out: 5 analog ‑ A total of 6 analog output channels with
output output channels with 16‑bit resolution and 10.417 MS/s update
14‑bit resolution and rate:
7.8125 MS/s update rate. § 4 Analog Out channels
§ 2 Analog Out-T channels that can
output the voltage signal via a
transformer.
Digital 10 digital I/O channels 32 versatile digital I/O channels 16 versatile digital I/O channels that
I/O that can be used as that can handle bit-wise data can handle bit-wise data or serial
follows: or serial communication. The communication. The main features are I/O
§ Digital In main features are I/O functions functions that use the digital channels to
that use the digital channels implement a specific I/O functionality.
§ Digital Out
to implement a specific I/O § Digital In: Up to 16 digital input
§ Digital InOut
functionality. functions that provide bit-wise access.
(bidirectional): An
§ Digital In: Up to 32 digital § Digital In/Out-Z: Up to 4 digital I/O
external signal is only
input functions that provide functions that provide bit-wise access
available if the direction
bit-wise access. and a high-impedance output state
of a channel is set to
In, otherwise the input § Digital Out: Up to 32 digital (tristate).
signal is consistent with output functions that provide § Digital Out: Up to 16 digital output
the output signal. bit-wise access. functions that provide bit-wise access.
§ Digital Out-Z: Up to 16 § Digital Out-Z: Up to 8 digital output
digital output functions that functions that provide bit-wise access
provide bit-wise access and a and a high-impedance output state
high-impedance output state (tristate).
(tristate).
§ RS485 Tx: Up to 8 serial functions that
§ RS232 Rx: Up to 8 serial transmit data values to RS485 networks
functions that receive data in simplex mode.
values from RS232 networks.
§ RS485 Rx: Up to 8 serial functions
§ RS232 Tx: Up to 8 serial that receive data values from RS485
functions that transmit data networks in simplex mode.
values to RS232 networks.
§ RS485 Rx/Tx: Up to 4 serial functions
§ RS485 Rx: Up to 8 serial that exchange data values with RS485
functions that receive data networks in half-duplex mode.
values from RS485 networks
in simplex mode.
§ RS485 Rx/Tx: Up to 8 serial
functions that exchange data
values with RS485 networks
in half-duplex mode.
§ RS485 Tx: Up to 8 serial
functions that transmit data

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 Typical Workflow for FPGA Handcoding

Feature DS2655M1 DS2655M2 DS6651

values to RS485 networks in
simplex mode.

For further information on the hardware, refer to the following:

§ Data Sheet of the DS2655M1 Multi-I/O Module (SCALEXIO Hardware
Installation and Configuration )
§ Data Sheet of the DS2655M2 Digital I/O Module (SCALEXIO Hardware
Installation and Configuration )
§ Data Sheet of the DS6651 Multi-I/O Module (SCALEXIO Hardware Installation
and Configuration )

Typical Workflow for FPGA Handcoding

Introduction There is a typical workflow you must follow, if you want to integrate a
code‑based FPGA application in a dSPACE hardware and software environment.

Workflow steps The workflow for the FPGA Programming Handcode Framework consists of the
following steps, which are explained in detail later on.
1. Copy a dSPACE FPGA framework from the dSPACE installation folder to a
custom folder.
For further information, refer to Preparing Your Environment on page 30.
2. Handcode the functionality of the FPGA application by changing the
contents of a customizable VHDL or Verilog file included in the dSPACE
FPGA framework.

Note

For SCALEXIO and MicroLabBox II systems, only VHDL‑coded projects

are available.

For further information, refer to Specifying the FPGA Functionality on

page 33.
3. Specify the I/O interface of the FPGA application in a MATLAB M file
included in the FPGA Programming Handcode Framework (Handcode FPGA
framework INI file).
For further information, refer to Specifying the FPGA I/O Interface on
page 30.
4. Write the I/O interface configuration to the VHDL or Verilog code
automatically via a MATLAB function provided by the FPGA Programming
Software Script Interface.
For further information, refer to Configuring the FPGA Code With the
Specified I/O Interface on page 32.
5. Use AMD Vivado to build the FPGA application. A preconfigured AMD
Vivado project is part of the FPGA Programming Handcode Framework.

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For further information, refer to How to Build the FPGA Application on

page 37.
6. Build a dSPACE FPGA model INI file/FPGAC file from the AMD Vivado results
via a MATLAB function provided by the FPGA Programming Software Script
Interface.
For further information, refer to Generating an FPGA Model INI File/FPGAC
File on page 39.
7. The following steps depend on the hardware used.
For a MicroAutoBox III, MicroLabBox II, or SCALEXIO system:
§ Add the FPGAC file as an FPGA custom function to ConfigurationDesk.
Refer to Adding FPGA Applications to the Signal Chain
(ConfigurationDesk Real-Time Implementation Guide ).
You implement the communication between the FPGA application and the
processor application via model ports in ConfigurationDesk.
For a MicroAutoBox II or a MicroLabBox:
§ Add the processor interface to your processor model. Perform one of the
following methods:
§ Use the Processor Interface blocks from the FPGA Programming Blockset
combined with the FPGA model INI file to program and access the FPGA
board.
For further information, refer to How to Build a Processor Application
on page 48.
§ Add data exchange functions of the Real-Time Library to your processor
application. Refer to Handcoding the Processor Interface on page 54.

Related topics Basics

Detailed Instructions on the Handcode Workflow..................................................................... 29

Software Tools for Working With the FPGA Programming Handcode Framework...................... 17

Modeling Aspects

Introduction Describes general modeling aspects that have no particular context.

General notes Code generation and the build process are managed by the FPGA Programming
Software. The software uses the AMD Vitis Model Composer to generate
VHDL code and starts the Vivado implementation process, including synthesis,
mapping, routing, and generating the bitstream file.

Notes on the build process The effort required to successfully place and
route an FPGA handcode increases with the FPGA handcode content. Starting
with an FPGA utilization of approx. 70%, the probability that an FPGA model
cannot be placed and routed increases exponentially. High FPGA utilization
can lead to unpredictable build aborts. Even the smallest change can lead to

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an abort. Therefore, dSPACE recommends to leave enough FPGA resources for

changes in the FPGA handcode, libraries, or dSPACE FPGA framework.
There are several aspects that determine whether an FPGA handcode can be
successfully placed and routed. These include:
§ The effectiveness of optimization methods during the build process. The
performance of different versions of the AMD Design Tools increases in
general, but optimizing most FPGA handcodes can impair the performance
of a specific FPGA handcode.
§ The design of the FPGA handcode itself:
§ Used libraries might be changed and need more FPGA resources.
§ The FPGA handcode cannot be mapped to the FPGA architecture efficiently.
For more information, refer to Measuring Device Performance and Utilization: A
Competitive Overview (https://docs.xilinx.com/v/u/en-US/wp496-comp-perf-util)
and UG906 Design Analysis and Closure Techniques (https://docs.xilinx.com/r/en-
US/ug906-vivado-design-analysis).

Notes on the build results Even if no errors occurred during handcoding,

simulating, and building, your FPGA application is not guaranteed to work
correctly. Some combination of factors might prohibit the execution of your
FPGA application, e.g., combinations of the operating temperature, the power
of the entire hardware system, technological limitations of the FPGA, the sample
rate, etc. Some FPGA applications do not start at all, others start correctly but fail
during operation.
Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA code.
To solve the problem, you have to modify the FPGA code and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable
FPGA application (refer to Audience profile on page 5). For more information,
contact dSPACE Support.

Synchronizing FPGA data If different data paths have different length, the data is valid at different points
in time and the outputs are asynchronous. This might cause an unexpected
behavior of your application. Make sure that the data paths are synchronized.

Unsupported features of the The FPGA Programming Handcode Framework does not support all features
FPGA Handcode Framework that are provided by the FPGA Interface sublibrary of the FPGA Programming
Blockset. For more information, refer to Unsupported Features of the FPGA
Programming Handcode Framework (FPGA Programming Handcode Framework -
FPGA Interface Reference ).

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

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 Detailed Instructions on the Handcode Workflow

Detailed Instructions on the Handcode Workflow

Introduction Provides detailed descriptions of each of the workflow steps.

Where to go from here Information in this section

Preparing Your Environment.................................................................... 30

The FPGA framework defines the available I/O functions and all their
parameters required to configure and use a specific FPGA board.

Specifying the FPGA I/O Interface............................................................ 30

The specified FPGA framework contains a handcode FPGA framework INI
file that you must customize according to the I/O functions used.

Configuring the FPGA Code With the Specified I/O Interface................... 32

Before you can build the FPGA application, you must configure the FPGA
code with the I/O interface.

Specifying the FPGA Functionality............................................................ 33

To implement FPGA functionality, you must customize a specific file from
the AMD Vivado project.

How to Build the FPGA Application......................................................... 37

The AMD Vivado project is used to start the build process of the FPGA
application.

Generating an FPGA Model INI File/FPGAC File........................................ 39

In this step, you will generate adSPACE file that will contain the
generated bitstream and relevant information on implementing the
processor communication.

Using the FPGA Model INI File for the Processor Interface........................ 40
Using the FPGA Model INI file to implement the processor interface of
the processor application for the MicroAutoBox II or the MicroLabBox.

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Preparing Your Environment

Introduction The FPGA framework defines the available I/O functions and all their parameters
required to configure and use a specific FPGA board.

Specifying the FPGA Before you start integrating your FPGA application into the dSPACE hardware,
framework you must specify the FPGA framework that corresponds to your FPGA board.
This provides information on all the available I/O functions and their parameters,
and further data required to use a specific FPGA board.

You will find the available FPGA frameworks in

<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks. You must
choose one of the subfolders and copy it to a user-defined location where you
have modify rights. The path to the destination folder will now be referenced as
<FPGA_Framework>.

Next step Now, you must specify the FPGA functionality, refer to Specifying the FPGA I/O
Interface on page 30.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

Specifying the FPGA I/O Interface

Introduction The specified FPGA framework contains a handcode FPGA framework INI file
that you must customize according to the I/O functions used.

Handcode FPGA framework The handcode FPGA framework INI file is a MATLAB M file.
INI file It is included in the selected FPGA framework folder and
is called hc_fpga_framework_ini_<Framework_Name>.m, for example,
hc_fpga_framework_ini_FPGA1403Tp1_DS1554_XC7K325T.m. The file
contains configuration parameters for the first and the last channel of all the
available I/O functions of the selected FPGA framework. Each I/O function used
in your FPGA application must be specified according to the example code in
the file. I/O functions that are not used should be commented out to minimize
the required FPGA resources, by entering %. The file is pre-initialized for the
handcoding example application described in Specifying the FPGA Functionality
on page 33. You have to configure the file within the section enclosed by
BEGIN USER CODE and END USER CODE.

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A detailed description of all the available I/O functions including their parameters
and the interface can be found in FPGA Programming Handcode Framework -
FPGA Interface Reference .

Additional instructions when When you use a SCALEXIO system, you have to specify the slot positions
using a SCALEXIO system of the mounted I/O modules (up to five modules). If you use inter-FPGA
communication, you must also specify the I/O module slots that provide the
inter-FPGA communication interface.
% ====== <FPGA Base Board> IO Modul Selection =======
...
% IO Frameworks to choose from:
% - IO_fpga_framework_ini_DS2655M1
% - IO_fpga_framework_ini_DS2655M2
% - IO_fpga_framework_ini_DS2655_InterFPGA
% - IO_fpga_framework_ini_DS6651
ioFrmIni = { ...
'IO_fpga_framework_ini_DS2655M1', ... % IO Module in slot 1
'', ... % IO Module in slot 2
'', ... % IO Module in slot 3
'', ... % IO Module in slot 4
'', ... % IO Module in slot 5
};
...

For each I/O module and inter-FPGA interface used, you have to copy the entire
I/O function section and modify it, for example, you have to adapt the I/O
module number ioModuleNr.
%>>>>>>>> DS2655M1 IO Module >>>>>>>>
% ====== IO-Module Number: =======
ioModuleNr = 1; % IO-Module Number (used Slot of IO Module)
%----------------------------------
% ------ Digital Out -------
%----------------------------------
hcfw.IOProperties.Out.Fct(1 + ioOutOffset(ioModuleNr)).Parameter(7).Init
= {'1'}; % High supply (0 for 5V, 1 for 3.3V)
...

Example If you use the FPGA1403Tp1_DS1554_XC7K325T framework (MicroAutoBox III,

the corresponding handcode FPGA framework INI file is called
hc_fpga_framework_ini_FPGA1403Tp1_DS1554_XC7K325T.m.

The following example shows that 128 channels of the I/O function Register
Out are available, but only the first and second channels are used. The entries
for the second channel have been added by copying one of the existing function
configurations and adapting them. The channel number has been changed and
the parameter values have been adapted. The entries for the last channel have
been commented out. For an I/O function that you want to use in your custom
code, you must set its HcUsed parameter to '1'.

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 Detailed Instructions on the Handcode Workflow

Note

If you only specify the HcUsed property of an I/O function in the

board‑specific hc_fpga_framework_ini file, all the parameters of this
function are set to their initial values. To overwrite a value, you have to
explicitly specify the related parameter.
If you set the HcUsed property to '0', you have to comment out the
specified parameters.

1 %----------------------------------
2 % ------ Register Out 1 -------
3 %----------------------------------
4 hcfw.PHSProperties.Out.Fct(1).HcUsed = {'1'}; % IO function is used in custom code
5 hcfw.PHSProperties.Out.Fct(1).HcCustomName = {'Inverted Data'}; % Custom name of the IO function
6 hcfw.PHSProperties.Out.Fct(1).Parameter(1).Init = {'0'}; % Binary Point position (0..32)
7 hcfw.PHSProperties.Out.Fct(1).Parameter(2).Init = {'signed'}; % Data Format (signed/unsigned/floating-point)
8 hcfw.PHSProperties.Out.Fct(1).Parameter(3).Init = {'0'}; % Register Group ID (0..63), 0 for ungrouped
9
10 %----------------------------------
11 % ------ Register Out 2 -------
12 %----------------------------------
13 hcfw.PHSProperties.Out.Fct(2).HcUsed = {'1'}; % IO function is used in custom code
14 hcfw.PHSProperties.Out.Fct(2).HcCustomName = {'Diagnostic Flag'}; % Custom name of the IO function
15 hcfw.PHSProperties.Out.Fct(2).Parameter(1).Init = {'0'}; % Binary Point position (0..32)
16 hcfw.PHSProperties.Out.Fct(2).Parameter(2).Init = {'signed'}; % Data Format (signed/unsigned/floating-point)
17 hcfw.PHSProperties.Out.Fct(2).Parameter(3).Init = {'0'}; % Register Group ID (0..63), 0 for ungrouped

Next step Now you must configure the FPGA code with the specified I/O interface, refer to
Configuring the FPGA Code With the Specified I/O Interface on page 32.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

Configuring the FPGA Code With the Specified I/O Interface

Introduction Before you can build the FPGA application, you must configure the FPGA code
with the I/O interface.

Configuring the FPGA code After you have specified the I/O interface in the handcode FPGA framework INI
using the script interface file (refer to Specifying the FPGA I/O Interface on page 30) and saved it, you can
use the script interface to initialize the framework. This means, that the FPGA
code is automatically configured with the specified I/O interface.

The script interface can be used in the MATLAB Command Window or in an M

file.

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The syntax is:

rtifpga_scriptinterface('HCFPGAFrameworkInit', ‘<FPGA_Framework>’, ‘<HC_FPGA_Framework_INI>’)

§ <FPGA_Framework>: Path to the specified FPGA framework

§ <HC_FPGA_Framework_INI>: Name of the handcode FPGA framework INI file
without file name extension

The script interface generates a unique ID for this application and modifies the
cm.v file accordingly.

Example If you have specified the FPGA1403Tp1_DS1554_XC7K325T framework that

you have copied to D:\Work\FPGAApplications, the command looks like this:
rtifpga_scriptinterface('HCFPGAFrameworkInit',
'D:\Work\FPGAApplications\DS1554',
'hc_fpga_framework_ini_FPGA1403Tp1_DS1554_XC7K325T')

Additional instructions when If you use DS2655M2 Digital I/O Modules and/or DS6651 Multi-I/O Modules, you
using DS2655M2 or DS6651 have to add files from the RTL folder of your handcode project folder to the
I/O modules Vivado handcode project.
§ Open AMD Vivado and add the following module-specific HDL files to your
handcode project via File - Add Sources:
input_spikefilter.vhd
IO_custom_drv_ctrl_CONST_[n].vhd
IO_custom_drv_ctrl_[n].vhd
IO_custom_drv_ctrl_[n].xdc
n=1…5

Next step Now, you can specify the FPGA functionality, refer to Specifying the FPGA
Functionality on page 33.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

Specifying the FPGA Functionality

Introduction To implement FPGA functionality, you must customize a specific file from the
AMD Vivado project.

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Customizing the architecture There are different projects available for coding with VHDL and Verilog.
section
Note

For SCALEXIO and MicroLabBox II systems, only VHDL‑coded projects are

available.

Using VHDL code Open the following AMD Vivado project:

<FPGA_Framework>\HC_Vivado\HC_Vivado.xpr

In the Sources pane, double-click the cm.vhd file.

The following illustration shows the cm.vhd file of the MicroLabBox II.

The Project Manager opens the file.

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At the end of the file you will find the architecture section that has to be
customized to implement the FPGA functionality.

Using Verilog code Open the following AMD Vivado project with the Vivado
Project Manager: <FPGA_Framework>\HC_Vivado\HC_Vivado_verilog.xpr

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Open the cm.v file from the project’s source files.

At the end of the file you will find the architecture section that has to be
customized to implement the FPGA functionality.

To connect your FPGA application to the I/O of the FPGA board and to the
processor application, you have to use the I/O functions defined in the specified
FPGA framework. These I/O functions provide several channels for Register In,
Buffer Out, Digital Out, Interrupt, etc. The I/O functions and their parameters,
and the number of channels, depend on the specified FPGA framework.

The signals of the cm entity form the interface to all the available I/O functions.
A detailed description of all the available I/O functions including their parameters
and the interface can be found in FPGA Programming Handcode Framework -
FPGA Interface Reference .

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You can use this information to customize the architecture section of the cm file
to implement your FPGA functionality.

Next step You can build the FPGA application, refer to How to Build the FPGA Application
on page 37.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

How to Build the FPGA Application

Objective The AMD Vivado project is used to start the build process of the FPGA
application.

Precondition The built FPGA application can be integrated into the dSPACE environment
only, if you have configured the I/O interface correctly. The required steps are
described in Detailed Instructions on the Handcode Workflow on page 29.

Method to use The method to build the FPGA application depends on the used dSPACE
hardware.
§ DS1303 Multi-I/O Board (MicroLabBox II):
You use a Tcl script. Refer to Method 1.
§ All dSPACE FPGA boards and MicroLabBox:
You use the GUI of Vivado. Refer to Method 2.

Method 1 To build the FPGA application using a Tcl script

1 In the Tcl Console pane, change to the CM file location.

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2 Enter source DS1303_FPGA_Build.tcl.

Vivado starts to generate the bitstream.

Method 2 To build the FPGA application using the AMD Vivado GUI
1 In the Flow Navigator, click Generate Bitstream.
2 If the No Implementation Results Available dialog appears, click Yes.

Result If no error messages are displayed, the build process has been successfully
finished and the FPGA bitstream has been created.

Note

If you use a DS6602 FPGA Base Board, the build process issues a critical
warning about a specific timing requirement.
For more information, refer to Problems and Their Solutions on page 93.

Even if no errors occurred during handcoding, simulating, and building, your

FPGA application is not guaranteed to work correctly. Some combination
of factors might prohibit the execution of your FPGA application, e.g.,
combinations of the operating temperature, the power of the entire hardware
system, technological limitations of the FPGA, the sample rate, etc. Some FPGA
applications do not start at all, others start correctly but fail during operation.

Due to the complexity of FPGA applications and their dependency on the used
FPGA hardware, the AMD Design Tools cannot ensure that all possible design
problems are detected during the analysis and simulation of the FPGA code.

To solve the problem, you have to modify the FPGA code and make sure that
you consider generally accepted FPGA design rules to ensure a stable and reliable
FPGA application (refer to Audience profile on page 5). For more information,
contact dSPACE Support.

Next step Now you must generate a corresponding FPGA model INI file/FPGAC file, refer
to Generating an FPGA Model INI File/FPGAC File on page 39. This includes
generating the files required for an FPGA custom function to be loaded in
ConfigurationDesk for systems that does not use RTI/RTlib to implement the
FPGA application.

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Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

Generating an FPGA Model INI File/FPGAC File

Introduction In this step, you will generate a file that will contain the generated bitstream and
relevant information on implementing the processor communication.

Depending on the platform, the generated file is an FPGA model INI file or an
FPGAC file.

Generating the FPGA model After you have built the bitstream, you can use the script interface to create
INI file/FPGAC file using the a new FPGA model INI file/FPGAC file that is application-specific because it
script interface includes a bitstream.

The script interface can be used in the MATLAB Command Window or in an M

file.

The syntax is:

rtifpga_scriptinterface('HCFPGAModelIniGenerate',
‘<FPGA_Framework>’,
‘<HC_FPGA_Framework_INI>’)
§ <FPGA_Framework>: Path to the specified FPGA framework
§ <HC_FPGA_Framework_INI>: Name of the handcode FPGA framework INI file
without file extension

Result The result depends on the platform used:

§ For SCALEXIO, MicroAutoBox III, and MicroLabBox II, the script generates an
FPGAC file with the file extension fpgac.
§ For MicroAutoBox II and MicroLabBox, the script generates an FPGA model INI
file with the file extension ini.

The generated file can be found in the current MATLAB working directory. It
is called <HcApplIDString>_<ApplicationID> where <HcApplIDString> is
the application name specified in the handcode FPGA framework INI file and
<ApplicationID> is the unique ID generated by the HCFPGAFrameworkInit
function of the script interface, refer to Configuring the FPGA Code With the
Specified I/O Interface on page 32.

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Example If you have specified the FPGA1403Tp1_DS1554_XC7K325T framework that

you have copied to D:\Work\FPGAApplications, the command looks like this:
rtifpga_scriptinterface('HCFPGAModelIniGenerate',
'D:\Work\FPGAApplications\DS15554',
FPGA1403Tp1_DS1554_XC7K325T')

Next step If you use a MicroAutoBox II or a MicroLabBox, you must implement the
processor interface based on the generated FPGA model INI file, refer to Using
the FPGA Model INI File for the Processor Interface on page 40.

If you use SCALEXIO, MicroAutoBox III, or MicroLabBox II, you can add the
FPGA application to ConfigurationDesk as an FPGA custom function. Refer to
How to Import FPGA Custom Function Block Types Provided by an FPGAC File
(ConfigurationDesk I/O Function Implementation Guide ).

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

Using the FPGA Model INI File for the Processor Interface

Introduction Using the FPGA Model INI file to implement the processor interface of the
processor application for the MicroAutoBox II or the MicroLabBox.

Generating RTI interface To implement the communication between the FPGA board and the
blocks processor board, you can implement a processor model containing RTI blocks
corresponding to the implemented FPGA I/O interface. These blocks are provided
by the Processor Interface of the FPGA Programming Blockset.

The processor board also controls the download of the bitstream.

All this information is contained in the generated FPGA model INI file, which
has to be imported to the processor model. For further information, refer to
Modeling the Processor Communication on page 44.

Including the bitstream to the The generated FPGA model INI file includes the bitstream to implement the
real-time application functionality of the FPGA application. If you use the Processor Interface of the
FPGA Programming Blockset to build the processor application, the bitstream
is automatically included to the real-time application. Refer to How to Build a
Processor Application on page 48.

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If you use RTLib to model the processor application, you must copy the bitstream
out of the FPGA model INI file and include it to the real-time application. Refer to
How to Extract Bitstream Files from FPGA Model INI Files on page 56.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

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Using RTI to Implement the Processor Interface

Introduction You can use the Processor Interface sublibrary of the FPGA Programming
Blockset to implement the processor model and the handcoded FPGA application
to the MicroAutoBox II or the MicroLabBox.

Where to go from here Information in this section

Modeling the Processor Communication.................................................. 44

The communication between the FPGA application and the processor
application must be implemented in a corresponding processor model.

Working with the Processor Model.......................................................... 47

If you have implemented the processor model, you can simulate its
behavior and build the processor application.

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Modeling the Processor Communication

Introduction The communication between the FPGA application and the processor application
must be implemented in a corresponding processor model.

Where to go from here Information in this section

How to Generate a Processor Model Interface......................................... 44

The RTI interface blocks in the processor model for exchanging data with
the FPGA application can be generated with all the relevant settings.

How to Trigger Interrupt-Driven Tasks...................................................... 46

You can use an output signal from the FPGA application to trigger an
asynchronous task in the processor model.

How to Generate a Processor Model Interface

Objective The RTI interface blocks in the processor model for exchanging data with the
FPGA application can be generated with all the relevant settings.

Basics Usually, you implement the FPGA application first, and then the interface to the
processor model. This means that all information required for the data exchange
is already specified in the FPGA model INI file. It therefore makes sense to
generate the corresponding preconfigured interface blocks automatically instead
of adding them to the processor model and configuring them manually.

Note

This step is totally different when you use a MicroAutoBox III/SCALEXIO

system. Refer to the ConfigurationDesk user documentation to inform
about generating the model interface.

Preconditions § Your platform is a MicroAutoBox II or a MicroLabBox.

§ The I/O functions for reading data, writing data, and interrupt handling in the
FPGA application should be completely configured before the corresponding
blocks are generated for the processor model.

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Method To generate a processor model interface

1 Add a PROC_SETUP_BL block to the processor model.
2 Double-click the block to open its dialog.
3 Switch to the Advanced page and add the generated FPGA model INI file to
the file list.
4 Switch to the Unit page and select the FPGA model INI file whose model
interface you want to generate.
5 Switch to the Interface page and click Generate to generate the RTI blocks
required for the processor model interface.

Result You have created a new model containing RTI blocks from the Processor
Interface library which are required to exchange data with the FPGA
application. The blocks are configured with all the relevant settings of their
counterparts in the FPGA application. Your FPGA application will contain
PROC_XDATA_WRITE_BL blocks for input I/O functions, such as Register In or
Buffer In, and PROC_XDATA_READ_BL blocks for output I/O functions, such
as Register Out or Buffer Out.

I/O functions that are only relevant on the FPGA board, for example, ADC or DAC
functions, are not given counterparts in the processor model interface.

You can now copy the generated blocks to your processor model and connect
them to the other Simulink blocks. You must not reconfigure these blocks
manually. The settings for data type conversion (floating-point to fixed-point
and vice versa) are implicit and can only be modified in the appropriate FPGA I/O
functions.

If you already implemented the processor model interface in the processor

model, and you want to assign the FPGA application to another FPGA board,
you must use the Adapt command on the Interface page of the block dialog
to set the new board number in the related processor interface blocks. You can
also check compatibility with the current FPGA application by using the Adapt
command. This will create a copy of the processor model that you can modify
manually according to the displayed messages.

Note

If you use the Adapt command, the processor model must contain only
processor interface block for one FPGA application. Otherwise the FPGA
board number will be replaced in any processor interface block used
anywhere in the model.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

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How to Trigger Interrupt-Driven Tasks

Objective You can use an output signal from the FPGA application to trigger an
asynchronous task in the processor model.

Basics You need an interrupt I/O function in the FPGA application and its counterpart in
the processor model to trigger a function-call subsystem by a value coming from
the FPGA.

Preconditions § Your platform is a MicroAutoBox II or a MicroLabBox.

§ You have implemented an Interrupt I/O function from the handcode FPGA
framework in your FPGA application. You must specify a channel and a
descriptive name for the interrupt channel used as parameters.

Method To trigger an interrupt-driven task

1 Add a PROC_INT_BL block to the processor model. You can do this
by instantiating this block from the Processor Interface library in the
processor model or by generating the processor model interface via the
PROC_SETUP_BL block and moving it from the temporary interface model to
the processor model. For detailed instructions, refer to How to Generate a
Processor Model Interface on page 44.
The PROC_INT_BL block must have the same channel number as the related
Interrupt I/O function in the FPGA application.

Result When the Interrupt I/O function in the FPGA application requests an interrupt,
the function-call subsystem is triggered that is connected to the PROC_INT_BL
block in the processor model.

Related topics HowTos

How to Generate a Processor Model Interface.......................................................................... 44

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Working with the Processor Model

Introduction When you have implemented the processor model, you can simulate its behavior
and build the processor application.

Where to go from here Information in this section

Simulating a Processor Model.................................................................. 47

Before you execute the processor application on the real-time hardware,
you should test its behavior in a simulated environment.

How to Build a Processor Application....................................................... 48

Before you can execute the processor model on the real-time hardware,
you must build an application from its generated code.

How to Create Burn Applications for MicroAutoBox II.............................. 49

You can explicitly program the FPGA with a burn application.

Simulating a Processor Model

Introduction Before you execute the processor application on the real-time hardware, you
should test its behavior in a simulated environment.

Simulating in different model You can simulate the processor model in these model modes:
modes § FPGA-Build / Offline simulation
§ Processor-Build

In both model modes, the processor model only contains the blocks from the
processor model. The simulation can therefore be used only to test the behavior
of the processor model, and there is no simulated data exchange with the FPGA
applications.

Note

When you use a MicroAutoBox III or SCALEXIO system, the simulation

behavior of the processor model is different to processor models for a
MicroAutoBox II or a MicroLabBox. For further information, refer to Model
Port Block Behavior During Simulink Simulation and Real-Time Execution
(Model Interface Package for Simulink - Modeling Guide ).

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Starting the simulation You can start the simulation in the model window of the processor model by
clicking the Start simulation toolbar button, choosing Simulation - Start from
the menu bar or using the Ctrl+T shortcut.

The simulation is executed for the specified simulation time or until you stop it.

How to Build a Processor Application

Objective Before you can execute the processor model on the real-time hardware, you
must build an application from its generated code.

Basics The code generation and the build process are managed by the Simulink Coder.
When you specify the system target file that corresponds to your hardware, for
example, rti1202.tlc for a MicroLabBox, most of the relevant configuration
parameters are set automatically, and many others can be customized. For
general information, refer to Building and Downloading the Model (RTI and
RTI-MP Implementation Guide ).

When you use a SCALEXIO/MicroAutoBox III/MicroLabBox II system, the

build process of the configured processor application is managed by
ConfigurationDesk. Model separation is not relevant.

Preconditions § The working folder must be set to the model path.

§ The processor model to be built must be opened in MATLAB.
§ If you want to download after the build process, the real-time hardware must
be registered, for example via the Platform Manager in ControlDesk.

Method To build a processor application

1 Switch the model mode to Processor-Build in the PROC_SETUP_BL block.
2 On the Unit page of the PROC_SETUP_BL block, select the required
programming option. If you specify not to program the related FPGA
application into flash or RAM, the FPGA application must be available in
the FPGA board's flash memory. Otherwise, the processor application will
terminate after the FPGA board's initialization phase.
3 Choose Tools - Code Generation - Options from the menu bar of the
model to open the Code Generation dialog.
4 Specify the required build options in the Configuration Parameters dialog.
Check the configuration, for example, the selected system target file and the
specified fixed step size.

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5 Click Build in the Code Generation dialog to start the build process.

Tip

If the build options were already specified, you can also start the
build process directly via the Ctrl+B shortcut or via the Tools - Code
Generation - Build Model command from the menu bar of the
model.

Result If the build process finished successfully, you will find the build results, such as
the processor application file and the variable description file, in the working
folder. If you have specified to program the FPGA application into flash or
RAM, the flash or the FPGA is automatically programmed when the processor
application is loaded. For further information on programming the FPGA, refer to
How to Create Burn Applications for MicroAutoBox II on page 49.

For example, if you built the MyDemo application for a MicroLabBox, you
will find the executable PPC file in the working folder and a subfolder called
MyDemo_rti1202 containing the generated code and all the intermediate build
results.

Related topics HowTos

How to Create Burn Applications for MicroAutoBox II............................................................... 49

How to Create Burn Applications for MicroAutoBox II

Objective You can explicitly program the FPGA of the MicroAutoBox II with a burn
application.

Basics A burn application is used to load an FPGA application to the FPGA. Usually, the
FPGA programming is included in the processor application and there is no need
to use a burn application. But in some cases, it is useful to program the FPGA
explicitly.

Note

If you load a processor application that was built without specifying a

programming option for the real-time hardware, and there is no application
running on the FPGA, the processor application is terminated after the
initialization phase of the FPGA board.

Programming into flash If you use the flash memory of the FPGA board,
you must execute the burn application only once. Each time you start the FPGA

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board, the FPGA application is loaded to the FPGA automatically. In this case, the
processor application should be built without specifying a programming option.
This gives you the shortest startup time for your system. If you want to load a
new FPGA application to the flash, you must execute the burn application to
replace the flash contents and restart the system to program the FPGA from the
flash with the new application.

Note

When programming into flash, you must consider the Autoboot features of
your hardware.
§ The Autoboot feature can be enabled and
disabled via the MicroAutoBox Configuration Tool
(<RCP_HIL_InstallationPath>/Exe/DS1401_ConfigGUI.exe) or via
RTLib, refer to fpga_tp1_enable_autoboot (MicroAutoBox II RTLib
Reference ) and fpga_tp1_disable_autoboot (MicroAutoBox II RTLib
Reference ).

Programming into RAM If you use the RAM memory of the FPGA board,
the FPGA must be programmed every time you start the system. It is therefore
recommended to build the processor application with the RAM programming
option to program the FPGA application automatically when loading the
processor application. A burn application for the RAM is useful if you want
to test the FPGA application only. If you program into the RAM memory, any
running FPGA application is immediately stopped and replaced with the new
FPGA application, unlike flash programming, where you must restart the board
to activate the new FPGA application.

Preconditions § Your platform is a MicroAutoBox II.

§ The model must be in the Processor-Build model mode.

Method To create a burn application

1 Double-click the PROC_SETUP_BL block in the processor model to open its
dialog.
2 On the Unit page, choose a programming option for each of the specified
FPGA applications.
3 Click Create burn application to start the build process for the burn
application. The Simulink Coder is used to manage the build process.

Result If the build process succeeded, the build result can be found in
<ModelName>_rtiFPGA/burnapplication. The executable is not
automatically downloaded to the processor board. The intermediate build results
can be found in
<ModelName>_rtiFPGA/burnapplication/<ModelName>_burnapplication
_rti1401.

For example, if you built the burn application for the

MyDemo model, you will find the executable PPC file in

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MyDemo_rtiFPGA/burnapplication and the intermediate build results in

MyDemo_rtiFPGA/burnapplication/MyDemo_burnapplication_rti1401.

For information how to load a burn application, refer to Experimenting with an

FPGA Application on page 61.

Related topics Basics

Experimenting with an FPGA Application.................................................................................. 61

References

CreateBurnApplication (FPGA Programming Software Script Interface Reference )

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Using RTLib to Implement the Processor Interface

Introduction You can use board-specific C functions to implement the processor application
and the handcoded FPGA application on the MicroAutoBox II or the
MicroLabBox.

Where to go from here Information in this section

Handcoding the Processor Interface......................................................... 54

RTLib functions let you implement the processor interface and handle the
FPGA interrupts.

How to Extract Bitstream Files from FPGA Model INI Files......................... 56

Extracting bitstream file from the FPGA model INI file to include the
bitstream file to the processor application.

How to Include Bitstream Files to Handcoded Processor

Applications............................................................................................ 57
You must include the bitstream file of the FPGA model INI file in the
processor application so the processor application is able to program the
FPGA.

How to Download FPGA Applications and Program the FPGA.................. 58

The processor application handles the download of the FPGA application
and the programming of the FPGA.

Information in other sections

MicroAutoBox II:
Compiling, Linking and Downloading an Application
(MicroAutoBox II RTLib Reference )
Information about the batch files, makefiles, and linker command files
that support your program development.

Board Initialization (MicroAutoBox II RTLib Reference )

Before you can use the FPGA Type 1 module, you have to perform the
initialization process.

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MicroLabBox:
Compiling, Linking and Downloading an Application
(MicroLabBox RTLib Reference )
Information about the batch files, makefiles, and linker command files
that support your program development.

FPGA Initialization (MicroLabBox RTLib Reference )

Before you can use the I/O FPGA application, you have to perform the
initialization process.

Handcoding the Processor Interface

Objective RTLib functions let you implement the processor interface and handle the FPGA
interrupts.

Data exchange With RTLib, you can implement the processor's read and write access to the
FPGA data storage via data exchange functions.

Accessing FPGA data storage Depending on the platform, FPGA data

storage, data direction, and bit width, you have to use different data exchange
functions to exchange data. The data exchange functions have the following
naming convention for the different use cases:
<FPGA_board>_<data_direction>_<data_storage>

Placeholder Possible Entry Meaning

FPGA_board fpga_tp1 MicroAutoBox II
IoFpga MicroLabBox
data_direction read Reading data from the FPGA application
write Writing data to the FPGA application
data_storage reg Accessing a 32-bit register
reg_grp Accessing a 32-bit register group
reg_grp_mixed Accessing one of the following register
groups:
§ 64-bit register group
§ Register group with 32-bit and 64-bit data
values
buf Accessing a 32-bit buffer
buf64 Accessing a 64-bit buffer

Data type conversion Data exchange with the FPGA application requires
data type conversion, which is configured by the scaling and mode parameters.

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The scaling parameter correlates with the binary point position parameter
of the FPGA application for signed and unsigned data types. The scaling
parameter is ignored if the FPGA application uses floating-point data. Predefined
symbols let you configure the scaling parameter. The following table shows
examples of predefined symbols for reading a register of an FPGA application
implemented on the MicroLabBox.

Processor Application FPGA Application

Symbol of the Scaling Parameter Meaning Binary point
position
IOFPGA_READ_SCALE_BIN_PT_0 Scaling factor: 0
1/20=1.00
IOFPGA_READ_SCALE_BIN_PT_3 Scaling factor: 3
1/23=0.125

The mode parameter lets you configure the data type used in the FPGA
application with predefined symbols.

Data exchange example This example shows how to write data in signed
mode with a scaling factor of 216 (Binary point position = 16) to register 1 of a
MicroLabBox:
Float64 scaling_factor = IOFPGA_WRITE_SCALE_BIN_PT_16;
IoFpga_write_reg(
1, //number of the register
&data, //pointer to data variable
&scaling_factor,
IOFPGA_DATA_MODE_SIGNED); // data processing mode (data type)

Interrupt handling The FPGA boards provide interrupt channels that you can handle by using
the RTLib interrupt functions. The handling of the interrupts depends on the
platform you use.

MicroAutoBox II You must enable the interrupt channel for the FPGA. To
do this, call fpga_tp1_enable_int. The interrupt handling is performed by the
interrupt controller on the MicroAutoBox II base board.

MicroLabBox Before interrupts can be read from the FPGA application,

you must enable the interrupt channel for the FPGA. To do this, call
IoFpga_enable_int. You must register the interrupt channels of the FPGA
application to connect them to the interrupt service routine (ISR) of MicroLabBox.
To do this, call IoFpga_register_isr. Pending interrupts are automatically
acknowledged to reset the associated flag in the interrupt flag register.
The following example shows you how to use interrupts with MicroLabBox:
/*
Compile and download with down1202:
down1202 ds1202_test.c ds1202_123456789A0002.c
*/
#include <brtenv.h>
static UInt32 isr_counter;
void isr_0(void)
{
isr_counter++;
}

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int main(void)
{
ULong64 applId = 0x123456789A0002ULL;
/* init RTLib and IoFpga */
RTLIB_INIT();
IoFpga_init(&applId);
/* register interrupt handler */
IoFpga_register_isr(isr_0, IOFPGA_INT_SRC_1);
/* RTLib global interrupt enable */
RTLIB_INT_ENABLE();
IoFpga_enable_int(IOFPGA_INT_SRC_1);
while(1)
{
RTLIB_BACKGROUND_SERVICE();
}
return 0;
}

Reference information MicroAutoBox II:

§ Data Exchange Functions (MicroAutoBox II RTLib Reference )
§ Interrupt Functions (MicroAutoBox II RTLib Reference )

MicroLabBox:
§ Data Exchange Functions (MicroLabBox RTLib Reference )
§ Interrupt Functions (MicroLabBox RTLib Reference )

How to Extract Bitstream Files from FPGA Model INI Files

Objective Extracting bitstream file from the FPGA model INI file to include the bitstream file
to the processor application.

Preconditions § The FPGA model INI file is generated.

§ A tool to extract ZIP files is installed.

Method To extract a bitstream file from an FPGA model INI file

1 Change the file-type extension of the FPGA model INI file from .ini
to .zip.
For example: FPGA_73536B10F7204F.ini to FPGA_73536B10F7204F.zip.
2 Extract the ZIP file. The C file with the name of the FPGA model INI file is the
bitstream file of your FPGA application.
3 Copy the bitstream file to the project folder of your processor application.
For example: Copy FPGA_73536B10F7204F.c to a local folder.

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Result You extracted the bitstream file.

Next step You can now include the bitstream file to the processor application. Refer
to How to Include Bitstream Files to Handcoded Processor Applications on
page 57.

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

How to Include Bitstream Files to Handcoded Processor Applications

Objective You must include the bitstream file of the FPGA model INI file in the processor
application so the processor application is able to program the FPGA.

Precondition The bitstream file is extracted from the FPGA model INI file.

Possible methods § You can edit a custom makefile to include the bitstream file. Refer to Method
1.
§ You can copy the C code of the bitstream file to the processor application
code. Refer to Method 2.

Method 1 To include a bitstream file by editing a custom makefile

1 Copy the DsBuildTemplate.mk makefile of your processor
board's RTLib to your application folder. For example, copy
<RCP_HIL_InstallationPath>\DS1202\DsBuildTemplate.mk of the
MicroLabBox.
2 Rename the makefile <application_name>.mk.
3 Edit the CUSTOM_SRC_FILES section of the makefile by adding the name of
the bitstream file. For example:
CUSTOM_SRC_FILES = FPGA_73536B10F7204F.c

Method 2 To include a bitstream file by copying C code

1 Copy the C code of the bitstream file to the handcoded processor
application.

Result You included the bitstream file to the handcoded processor application.

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Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

How to Download FPGA Applications and Program the FPGA

Objective The processor application handles the download of the FPGA application and the
programming of the FPGA.

Basics If you handcode the processor application for a MicroAutoBox II, you have to call
an RTLib function to download the bitstream and program the FPGA. You must
call the FPGA programming function after the processor board was initialized
and before the FPGA is initialized.

Note

Due to MicroLabBox's loading mechanism, no function is required for

downloading and programming the FPGA module. If the bitstream
file is included, the FPGA is programmed during the initialization of
MicroLabBox. To initialize MicroLabBox, call the functions RTLIB_INIT()
and IoFpga_init(&appID).

Method To download FPGA application and program the FPGA of the

MicroAutoBox II
1 Initialize the processor board by calling init().
2 Download the FPGA application and program the FPGA by calling
fpga_tp1_program.
3 Initialize the FPGA board by calling fpga_tp1_init.
4 If you want to enable or disable that the FPGA application
stored in the flash memory starts automatically after power‑up,
call fpga_tp1_enable_autoboot or fpga_tp1_disable_autoboot,
respectively. The functions overwrite the settings of the MicroAutoBox II
Configuration Tool.
FPGA applications stored in the RAM/SRAM cannot start automatically after
power‑up.

Result After you build the real-time application, the real-time application can download
the FPGA application and program the FPGA.

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Example This example shows you how to use the FPGA programming function for a
MicroAutoBox II in general:
extern void *fpga_prgrm_data_ptr_<AppID>;
fpga_tp1_prgr_dat *datastruct = (fpga_tp1_prgr_dat*)fpga_prgrm_data_ptr_<AppID>;
fpga_tp1_program(base, datastruct);

Assuming that the created model INI file contains

FPGA_TP1_MAIN_84303E38761313.c, the program function and the data
structure look like the following example.

Extract from the above-mentioned C file:

#include <dstypes.h>
UInt8 bitstream_84303E38761313[];
UInt32 compat_boards_maj_84303E38761313[];
UInt32 compat_boards_min_84303E38761313[];
struct
{
UInt32 model_blkst_major;
UInt32 model_blkst_minor;
UInt32 model_blkst_maintenence;
UInt8 *bitstream_pt;
UInt32 length;
UInt32 length_unpckd;
UInt32 *compatible_boards_list_maj_pt;
UInt32 *compatible_boards_list_min_pt;
UInt32 compatible_boards_list_length;
UInt32 fw_id;
UInt32 mode;
} prgr_dat_84303E38761313 =
{
1, /* blockset major version */
1, /* blockset minor version */
0, /* blockset maintenance version */
(UInt8*) &bitstream_84303E38761313, /* pointer to bitstream */
0x3199e, /* length compressed (= 203,166 bytes) */
0x441f80, /* length decompressed (= 4,464,512 bytes) */
(UInt32*) &compat_boards_maj_84303E38761313, /* pointer to comp boards major */
(UInt32*) &compat_boards_min_84303E38761313, /* pointer to comp boards minor */
1, /* number of compatible boards */
1, /* framework identifier */
(0x02 | 0x04 | 0x08)
/* programming mode: FPGA_TP1_PRGRM_SRM | FPGA_TP1_PRGRM_COM |
FPGA_TP1_PRGRM_DBGOUT */
};
void *fpga_prgrm_data_ptr_84303E38761313 = (void*) &prgr_dat_84303E38761313;
UInt32 compat_boards_maj_84303E38761313[] =
{
2
};
UInt32 compat_boards_min_84303E38761313[] =
{
0
};

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UInt8 bitstream_84303E38761313[] =
{
249,255,255,255,255,249,4,4,
249,8,8,249,16,16,0,0,
0,187,17,34,0,68,249,8,
...
}
...

Extract from the main program:

extern void *fpga_prgrm_data_ptr_84303E38761313;
fpga_tp1_prgr_dat *datastruct = (fpga_tp1_prgr_dat*)
fpga_prgrm_data_ptr_84303E38761313;
fpga_tp1_program(base, datastruct);

Related topics Basics

Typical Workflow for FPGA Handcoding.................................................................................... 25

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Running Processor and FPGA Applications on the

Real-Time Hardware

Introduction When you have built the executable applications for the processor and the FPGA
board, you can load them to the real-time hardware for experimenting.

Experimenting with an FPGA Application

Introduction You can observe the behavior of the real-time application and change
application‑specific parameters by using ControlDesk.

Downloading processor and To run a processor application, the built executable file must only be
FPGA application downloaded to the real-time hardware. The real-time hardware must be
registered beforehand, for example, via the Platform Manager in ControlDesk
or ConfigurationDesk. Any running application is stopped and overwritten by the
newly loaded application. If the processor application contains the programming
of the FPGA, the FPGA application is loaded to the FPGA automatically. If it does
not, and there is no FPGA application running, you must first download the burn
application to program the FPGA and afterwards the processor application.

Note

Before you download the processor application, the flash process started
by the burn application must be finished. For more information on burn
applications, refer to How to Create Burn Applications for MicroAutoBox II
on page 49.

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Note

Even if no errors occurred during handcoding, simulating, and building, your

FPGA application is not guaranteed to work correctly. Some combination
of factors might prohibit the execution of your FPGA application, e.g.,
combinations of the operating temperature, the power of the entire
hardware system, technological limitations of the FPGA, the sample rate,
etc. Some FPGA applications do not start at all, others start correctly but fail
during operation.
Due to the complexity of FPGA applications and their dependency on the
used FPGA hardware, the AMD Design Tools cannot ensure that all possible
design problems are detected during the analysis and simulation of the
FPGA code.
To solve the problem, you have to modify the FPGA code and make sure
that you consider generally accepted FPGA design rules to ensure a stable
and reliable FPGA application (refer to Audience profile on page 5). For
more information, contact dSPACE Support.

Required files For experimenting, i.e., changing application-specific parameters during run time
and displaying the behavior, you need files that are created during the build
process, for example, the processor application (.x86, .ppc or .rta), the variable
description file (.trc), the system description file (.sdf), and the mapping file
(.map).

Note

If you want to access an FPGA signal, you must provide it to the processor
model.

Related documents § ControlDesk Introduction and Overview for information on working with
ControlDesk.
§ ConfigurationDesk Real-Time Implementation Guide for detailed
information on working with ConfigurationDesk.

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Features Provided by Specific FPGA Boards

Introduction The following features are provided only by specific FPGA boards.

Where to go from here Information in this section

Handcoding Inter-FPGA Communication.................................................. 64

The SCALEXIO FPGA base boards support inter‑FPGA communication.

MicroLabBox: Using Remaining I/O Channels with RTI/RTLib.................... 81

Only the DS1202 FPGA I/O Type 1 (Flexible I/O) framework lets you use
remaining I/O channels with RTI blocksets/RTLib for MicroLabBox.

DS6602: Accessing the DDR4 RAM.......................................................... 84

The DS6602 (KU15P) FPGA Base Board framework lets you access the
DDR4 RAM of the FPGA base board.

DS6601, DS6602: Coding a Customized MGT Protocol .......................... 87

The DS6601 (KU035) FPGA Base Board and the DS6602 (KU15P) FPGA
Base Board frameworks let you customize MGT protocols.

DS6601, DS6602: Configuring the Timeout of a Watchdog I/O

Function.................................................................................................. 89
The DS6601 (KU035) FPGA Base Board and the DS6602 (KU15P) FPGA
Base Board frameworks provide a watchdog I/O function to check if the
processor application is alive.

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Handcoding Inter-FPGA Communication

Introduction The SCALEXIO FPGA base boards support inter‑FPGA communication.

Where to go from here Information in this section

Introduction to Inter-FPGA Communication............................................. 64

Different types of inter-FPGA communication buses.

Handcoding Inter-FPGA Communication via IOCNET................................ 66

Implementing inter-FPGA communication by using the board-specific bus
of SCALEXIO systems.

Handcoding Inter-FPGA Communication via MGT Modules...................... 69

Implementing inter-FPGA communication by using MGT modules that
are installed to the DS6601/DS6602 FPGA Base Boards.

Handcoding Inter-FPGA Communication via I/O Module Slots.................. 70

Implementing inter-FPGA communication by using the I/O module slots
of SCALEXIO FPGA base boards.

Introduction to Inter-FPGA Communication

Overview of Inter-FPGA Communication

Platforms supporting inter- The following platforms support inter-FPGA communication:

FPGA communication § SCALEXIO systems with SCALEXIO FPGA base boards DS2655, DS6601, or
DS6602.
SCALEXIO provides different types of inter-FPGA communication. Refer
to Overview of inter-FPGA communication between SCALEXIO boards on
page 65.

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Overview of inter-FPGA The following table shows the different types of inter-FPGA communication
communication between between SCALEXIO FPGA base boards.
SCALEXIO boards

Inter-FPGA via I/O Module Inter-FPGA via MGT Inter-FPGA via IOCNET
Slots Module
Topology 1:1 1:1 1:n
FPGA stack1) Next to each other No restriction § Within the same IOCNET
location segment2)
§ Other I/O boards must not
be connected to this IOCNET
segment.
Number of direct 2 4 Not directly limited
connections
Data rate Max. 582.3 Mbit/s with default Max. 10.3125 Gbit/s with § 1.25 Gbit/s IOCNET:
values Aurora 64b66b 128 Bit Approx. 800 Mbit/s
I/O function § 2.5 Gbit/s IOCNET:
Typ. 1 Gbit/s, max.
1.6 Gbit/s3)
Latency 72 ns … 96 ns with default Typ. 384 ns, max. 472 ns Typ. 1.0 µs per network hop,
values for single words including onboard hops
Supported FPGA § DS2655 § DS6601 § DS2655
base boards § DS6601 § DS6602 § DS6601
§ DS6602 § DS6602
Required accessory SCLX_INT_FPGA_CAB1 DS6601_MGT1 or –
DS6602_MGT1
1) FPGA base board with installed I/O modules.
2) Refer to Implementing Inter-FPGA Communication via IOCNET on page 66.
3) Theoretical maximum

Implementing the inter-FPGA To implement an inter-FPGA communication bus, you have to implement the
interface functionality to the FPGA code.

Depending on the used hardware, refer to one of the following topics:

§ Implementing Inter-FPGA Communication via IOCNET on page 66
§ Implementing Inter-FPGA Communication via MGT Modules on page 69
§ Implementing Inter-FPGA Communication via I/O Module Slots on page 70

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Handcoding Inter-FPGA Communication via IOCNET

Where to go from here Information in this section

Implementing Inter-FPGA Communication via IOCNET............................. 66

IOCNET can be used to transfer data directly between FPGA boards of a
SCALEXIO system.

Calculating the Latency (IOCNET)............................................................. 67

Calculating the latency of an inter-FPGA connection via IOCNET.

Implementing Inter-FPGA Communication via IOCNET

Introduction IOCNET can be used to transfer data directly between FPGA boards of a
SCALEXIO system.

Basic interface characteristics You have to consider the following interface characteristics if you implement
inter-FPGA communication via IOCNET.
§ Up to 32 channels to transmit 32-bit values and up to 32 channels to transmit
64-bit values can be implemented.
§ The data rate depends on the IOCNET data rate:
§ 1.25 Gbit/s IOCNET:
About 800 Mbit/s
§ 2.5 Gbit/s IOCNET:
Typ. 1 Gbit/s, max. 1.6 Gbit/s theoretical
§ The latency is typ. 1 µs per network hop. Refer to Calculating the Latency
(IOCNET) on page 67.
§ Each 32-bit channel can address up to 1024 data values.
§ Each 64-bit channel can address up to 512 data values.
§ The data type is a raw data type: UFix_32_0 or UFix_64_0.
You can transfer any data type with a matching bit width via inter-FPGA over
IOCNET. Use the Reinterpret block from the HDL library of the AMD Vitis
Model Composer to change your data type to UFix_32_0 or UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.

Restrictions on the IOCNET Inter-FPGA via IOCNET can only be used for FPGA base boards if the following
topology requirements on the IOCNET topology are fulfilled:
§ The boards are installed to the same IOCNET segment. An IOCNET segment
are the IOCNET nodes (I/O unit/LabBox/AutoBox) that are linked in serial to the
processing hardware. The following illustrations shows an example.

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Downlink

Downlink

IOCNET segment

Tip

In ConfigurationDesk, switch the Platform Manager to the network

view via the context menu.

§ Other I/O boards must not be connected to the used IOCNET segment.

Adding the inter-FPGA The frameworks of the FPGA base boards provide inter-FPGA blocks to add the
communication functionality inter-FPGA communication functionality to the FPGA application.
to the FPGA application

Specifying the inter-FPGA After you added the FPGA application to the signal chain in ConfigurationDesk,
connections you can reference the Inter-FPGA In blocks to the Inter-FPGA Out blocks to
specify the communication bus.

For more information, refer to Configuring the Basic Functionality (FPGA)

(ConfigurationDesk I/O Function Implementation Guide ).

Related topics Basics

Overview of Inter-FPGA Communication................................................................................... 64

Calculating the Latency (IOCNET)

Latency calculation The latency depends on the network hops between the FPGA base boards. A
network hop occurs when a data packet is passed from one network connection
to the next. Each hop takes about 1.0 µs.

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To calculate the latency, you have to count the IOCNET routers between the
FPGA base boards, including the onboard routers.

Tip

In ConfigurationDesk, switch the Platform Manager to the network view

via the context menu.

Example #1 The following illustration shows a topology with 3 network hops between the
FPGA base boards.

These are the network hops:

§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 3)
§ Onboard IOCNET router of the DS6001 Processor Board
§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 4)

Latency = 3 hops · 1.0 µs/hop (typ.) ≈ 3 µs

Example #2 The following illustration shows a topology with 5 network hops between the
FPGA base boards.

These are the network hops:

§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 2)
§ IOCNET router of the DS2703 6-Slot I/O Unit (1)
§ IOCNET router of the Processing Unit
§ IOCNET router of the DS2703 6-Slot I/O Unit (2)
§ Onboard IOCNET router of the DS6601 FPGA Base Board (Slot 4)

Latency = 5 hops · 1.0 µs/hop (typ.) = 5.0 µs

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Handcoding Inter-FPGA Communication via MGT Modules

Implementing Inter-FPGA Communication via MGT Modules

Introduction Multi-gigabit transceiver (MGT) modules can be used to transfer data directly
between FPGA boards of a SCALEXIO system.

Basic interface characteristics You have to consider the following interface characteristics if you implement
inter-FPGA communication via MGT modules.
§ MGT modules are optional modules that must be installed to the FPGA base
board.
§ Up to 4 channels to transmit data values to up to 4 FPGA base boards.
§ The maximum data rate is 10.3125 Gbit/s if you use an Aurora 64b66b 128
Bit I/O function.
§ The typical latency is 384 ns for single words. The maximum latency is 472 ns.
§ Each 64-bit channel can address up to 512 data values.
§ The data type is a raw data type: UFix_32_0 or UFix_64_0.
You can transfer any data type with a matching bit width via inter-FPGA over
IOCNET. Use the Reinterpret block from the HDL library of the AMD Vitis
Model Composer to change your data type to UFix_32_0 or UFix_64_0 and
vice versa. Reinterpreting data types does not cost any hardware or latency.

Adding the inter-FPGA The DS660X_MGT framework provides I/O functions to transmit and receive data
communication functionality via an installed MGT module using the Aurora protocol, but you can also use
to the FPGA application customized protocols.

Preventing additional latencies for data streams Latency can increase if

the transmission must pause to prevent the RX-FIFO buffer from overflowing
due to clock drift between the different FPGA boards. When data is sent with
every FPGA clock cycle, a pause can happen despite the high precision clocks
of the DS6202 FPGA Base Boards. The latency is about 5.4 µs for 64‑bit data
transmission and 10.4 µs for 128‑bit data transmission.
To transfer data without latency due to clock domain crossing, use the
mgt_user_clk_156 port of the Aurora 64b66b I/O functions to implement the
part for inter-FPGA communication synchronous with the clock frequency of the
MGT module, i.e. with 156.25 MHz.
The Aurora protocol automatically synchronizes the different clocks and there is
no need for clock compensation. Therefore, you will not see clock drift in the
156.25 MHz systems between FPGA boards that communicate using the Aurora
protocol.

Further information For more information, refer to I/O Functions of the

DS660X_MGT Framework (FPGA Programming Handcode Framework - FPGA
Interface Reference ).

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Related topics Basics

Overview of Inter-FPGA Communication................................................................................... 64

Handcoding Inter-FPGA Communication via I/O Module Slots

Where to go from here Information in this section

Implementing Inter-FPGA Communication via I/O Module Slots............... 70

Aspects on implementing inter-FPGA communication between SCALEXIO
FPGA base boards via I/O module slots.

How to Determine the Bit Ranges for Inter-FPGA Subbuses

Between SCALEXIO FPGA Base Boards.................................................... 75
When you specify subbuses to send and receive data, you must observe
limitations for the bit ranges of subbuses.

Calculating the Data Rate and Latency (SCALEXIO).................................. 78

Optimizing the bus settings for the inter-FPGA communication bus via I/O
module ports.

Implementing Inter-FPGA Communication via I/O Module Slots

Introduction With the Inter-FPGA Interface framework, the I/O module slots of the SCALEXIO
FPGA base boards can be used to establish an inter-FPGA communication bus.

Avoiding damage to the NOTICE

board
The improper assembly of inter-FPGA communication buses will
damage the FPGA boards
For inter-FPGA communication buses, special inter-FPGA communication
cables must be used. Other cables, such as the cables used for connecting
the I/O modules, will damage the FPGA boards. Furthermore, special rules
for attaching the FPGA boards must be observed to ensure proper bus
communication.
§ Use the SCLX_INT_FPGA_CAB1 inter-FPGA cables and observe the
enclosed documentation for assembling.
§ Do not connect FPGA boards via inter-FPGA cables if the FPGA boards are
connected to different processors via IOCNET.

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Basic interface characteristics You have to consider the following interface characteristics if you implement
inter-FPGA communication via I/O module slots.
§ The inter-FPGA communication bus is a point-to-point one-way
communication. It is implemented directly between the connected FPGA
boards without using IOCNET.
§ An inter-FPGA communication cable can only connect FPGA base boards that
are installed next to each other. Therefore, up to two FPGA base boards can be
directly connected to an FPGA base board. For an example, refer to Inter-FPGA
communication between multiple SCALEXIO FPGA base boards on page 74.
§ The maximum data rate is 582.3 Mbit/s with default values. Refer to
Calculating the Data Rate and Latency (SCALEXIO) on page 78.
§ The latency is 72 ns … 96 ns with default values. Refer to Calculating the Data
Rate and Latency (SCALEXIO) on page 78.
§ The maximum data width for inter-FPGA communication with bus
synchronization is 27 bits.
The interface provides a 28‑bit parallel data bus. One data bit of each subbus
is reserved for synchronization purposes.
In expert mode, the Inter-FPGA Interface framework provides inter-FPGA
communication without bus synchronization. In this mode, the maximum data
width for inter-FPGA communication is 28 bits.
§ You can configure up to eight subbuses for each inter-FPGA communication
bus.
§ Inter-FPGA communication between different types of SCALEXIO FPGA boards
is supported. For example: A DS2655 FPGA Base Board can be connected to a
DS6601 FPGA Board and a DS6602 FPGA Base Board.

Adding the inter-FPGA You add the inter-FPGA functionality to the FPGA application by configuring
communication functionality the hc_fpga_framework_ini_<SCALEXIO FPGA base board>.m file of the
to the FPGA application SCALEXIO FPGA base board framework.

Refer to Specifying the FPGA I/O Interface on page 30.

Location of SCALEXIO FPGA base board frameworks with inter-FPGA

communication:
§ DS2655 (7K160) FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS2655_XC7K160T
§ DS2655 (7K410) FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS2655_XC7K410T
§ DS6601 FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6601_XCKU035
§ DS6602 FPGA Base Board:
<RCP_HIL_InstallationPath>\MATLAB\RTIFPGA\Frameworks\
DS6602_XCKU15P

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Specifying the inter-FPGA The I‑FPGA In and I‑FPGA Out I/O functions let you specify the inter-FPGA
communication communication.

You can implement an inter-FPGA communication bus without bus

synchronization or you can change the default values for clock, bit length,
and filter depth. It is not recommended to implement a bus without bus
synchronization or to change the default bus parameter values if you do not
have enough experience with configuring buses and knowledge of checking
whether the configured transmission is correct with regard to the observed signal
integrity at the applicable temperature range.

For more information on the inter-FPGA I/O functions, refer to I/O Functions of
the Inter-FPGA Interface Framework (FPGA Programming Handcode Framework -
FPGA Interface Reference ).

Configuring subbuses Eight communication channels let you use up to eight subbuses. If you configure
subbuses, you can access a specific subbus by specifying a bit range with
the related start bits and end bits in the inter-FPGA I/O functions. The bit
ranges of the subbuses must not overlap. One bit has to be reserved for
synchronization purposes for each configured subbus. The maximum data width
of a synchronized subbus is therefore Endbit ‑ Startbit.

You cannot use two I/O functions that use the same communication channel
within the same FPGA application. For example, you cannot use an I‑FPGA In
function on channel number 1 if there is already an I‑FPGA Out function on this
channel, but you can use an I‑FPGA In function on channel number 2.

Note

If you send and receive data with the same inter-FPGA interface, you have
to consider limitations on the bit ranges for the subbuses. Refer to How
to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO
FPGA Base Boards on page 75.

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General configuration aspects NOTICE

An incorrect configuration might damage the electrical interface.

If you configure both ends of an inter-FPGA connection bus to write on the
bus, the connection results in a short circuit. This short circuit might damage
the electrical interface of the used I/O module slots. In multiprocessor
applications, an incorrect configuration cannot be detected automatically
to beware hardware damage.
§ Make sure that you implement for each I‑FPGA Out function an
I‑FPGA In function as counterpart on the other FPGA board.
§ Make sure that the inter-FPGA I/O functions implemented on the other
FPGA board uses the same Startbit and Endbit to send or receive the
data.
§ Do not use inter-FPGA communication in a multiprocessor application
to transmit data between FPGA boards that are connected to different
processors via IOCNET.

Application examples The hardware connections, the implemented FPGA code, and the function
settings for the bus configuration have to match to get the required data
transfer.

Inter‑FPGA communication in one direction without a subbus In the

following example with two FPGA base boards, the FPGA application that runs
on board 1 uses the entire data width of the bus to send data to board 2.

Inter-FPGA
Board 1 communication Board 2

I-FPGA I-FPGA
Start bit: 0 Master 1 Slave 1 Start bit: 0
27 bit data + 1 bit sync.
End bit: 27 End bit: 27

Inter‑FPGA communication in both directions with two subbuses In the

following example, the FPGA applications can exchange data with a data width
of 8 bits in both directions. At the inports and outports of an I-FPGA Block, the
position of the LSB is always 0. The offset configured by the start bit for an
Inter-FPGA subbus does only apply to the arrangement of bits on the Inter-FPGA
bus.
The master and the slave which are communicating have to be configured with
the same communication settings. For example, it is not allowed to specify the
slave settings to receive only a subrange of the transmitted data.

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Inter-FPGA
Board 1 communication Board 2

I-FPGA Subbus 1 I-FPGA

Start bit: 0 Master 1 Slave 1 Start bit: 0
8 bit data + 1 bit sync.
End bit: 8 End bit: 8

I-FPGA Subbus 2 I-FPGA

Start bit: 14 Slave 2 Master 2 Start bit: 14
8 bit data + 1 bit sync.
End bit: 22 End bit: 22

Inter-FPGA communication between multiple SCALEXIO FPGA base

boards In the following example with three SCALEXIO FPGA base boards,
the FPGA application of board 2 can directly send data to board 1 and board 3.
The FPGA application that runs on board 2 uses two inter-FPGA interfaces, one
interface for each connected board.
Inter-FPGA
Board 2 communication Board 1

I-FPGA Bus 1 I-FPGA

Start bit: 0 Master 1 Slave 1 Start bit: 0
End bit: 27 End bit: 27

I-FPGA Bus 2
Start bit: 0 Master 2 Board 3
End bit: 27
I-FPGA
Slave 2 Start bit: 0
End bit: 27

More than three boards can be connected via inter-FPGA communication cables,
but only the boards that are located next to each other can be connected with
an inter-FPGA communication cable.

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The following illustration shows the assembly of four FPGA stacks (FPGA base
board with I/O modules) that are used for inter-FPGA communication.
Inter-FPGA communication cables
Rear

5 5 5 5
4 4 4 4
3 3 3 3
2 2 2 2

One or more I/O modules

One or more I/O modules

One or more I/O modules

One or more I/O modules

1 1 1 1

Base board 1
...
Base board 2

Base board 3

Base board 4
...
Stack 1 Stack 2 Stack 3 Stack 4

Front

Related topics Basics

Overview of Inter-FPGA Communication................................................................................... 64

HowTos

How to Determine the Bit Ranges for Inter-FPGA Subbuses Between SCALEXIO FPGA
Base Boards.............................................................................................................................. 75

References

I/O Functions of the Inter-FPGA Interface Framework (FPGA Programming

Handcode Framework - FPGA Interface Reference )

How to Determine the Bit Ranges for Inter-FPGA Subbuses Between

SCALEXIO FPGA Base Boards

Objective When you implement subbuses to send and receive data via an inter-FPGA
communication bus between SCALEXIO FPGA base boards, you must observe
limitations for the bit ranges of subbuses.

Limitations For a robust communication, the wires of the interface cable are grouped to six
cable segments. Within a cable segment, data can only be sent in one direction.

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That means, you cannot use the same cable segment to send and receive data.
Furthermore, the interface cable supports only two cable segment ranges that
transmit data as shown in the example below.

Inter-FPGA Interface Inter-FPGA

interface 1 cable interface 2
Data Data
Subbus 1 Cable segment 1...2 Subbus 1

Data Data
Subbus 2 Cable segment 3...6 Subbus 2

The following example shows an unsupported subbus configuration, because the

subbuses use three cable segment ranges.
Inter-FPGA Interface Inter-FPGA
interface 1 cable interface 2
Data Data
Subbus 1 Cable segment 1...2 Subbus 1

Data Data
Subbus 2 Cable segment 3...4 Subbus 2

Data Data
Subbus 3 Cable segment 5...6 Subbus 3

Note

If you use the inter-FPGA communication bus only in one direction, you can
specify the bit ranges of subbuses without limitations. You must consider
the limitations only if you send and receive data with the same inter-FPGA
interface.

Bit ranges supported by the The following table shows which cable segment supports which bit range:
cable segments
Cable Segment Bit range
1 0 ... 5
2 6 ... 7
3 8 ... 13
4 14 ... 19
5 20 ... 21
6 22 ... 27

Method To determine the bit ranges for inter-FPGA subbuses between SCALEXIO
FPGA base boards
1 Choose one continuous range of cable segments that can be used to send
data and one continuous range that can be used to receive data. The
ranges must not overlap. For examples, refer to Configuration examples on
page 77.

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2 Identify the bit range that is supported by the chosen cable segment range
for sending data. This bit range can be used by subbuses to send data.
For example: The cable segments 1 ... 3 support the bit range 0 ... 13.
3 Use the identified bit range to determine the bit ranges of subbuses to
send data. You can determine multiple subbuses, as shown by Example 2 on
page 77.
4 Identify the bit range that is supported by the chosen cable segment range
for receiving data. This bit range can be used by subbuses to receive data.
5 Use the identified bit range to determine the bit ranges of subbuses to
receive data.

Result You determined the bit ranges of the subbuses.

Next step Add the I-FPGA In and I-FPGA Out functions to the FPGA code to implement
the inter-FPGA communication and configure their start and end bits with the
determined bit ranges.

Configuration examples The examples help you configure the bit ranges of your subbuses and show you
possible configuration errors.

Example 1 The following table shows you an example for bit ranges of two
subbuses.

Bus Direction Chosen Cable Segments Configured Subbuses

Segment Range Resulting Bit range for Subbuses I/O Function Start Bit End Bit
Sending data 1 ... 3 0 ... 13 I-FPGA Out 0 8
Receiving data 4 ... 6 14 ... 27 I-FPGA In 14 22

Example 2 The following table shows you an example for bit ranges of four
subbuses.

Bus Direction Chosen Cable Segments Configured Subbuses

Segment Range Resulting Bit range for Subbuses I/O Function Start Bit End Bit
Sending data 1 ... 2 0 ... 7 I-FPGA Out 0 4
I-FPGA Out 5 6
Receiving data 3 ... 6 8 ... 27 I-FPGA In 8 16
I-FPGA In 19 27

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Example 3 (unsupported configuration) The following table shows you an

example of an unsupported configuration of two subbuses.

Configured Subbuses Bus Affected Resulting Conflict

Direction Cable
I/O Function Start End
Segments
Bit Bit
I-FPGA Out 0 8 Sending data 1 ... 3 Cable segment 3 is used in both directions, but
I-FPGA In 9 17 Receiving 3 ... 4 one cable segment can be used either to send
data data or to receive data.
Remedy: Use the bit range 14 ... 22 for the
I‑FPGA In function.

Example 4 (unsupported configuration) The following table shows you an

example of an unsupported configuration of three subbuses.

Configured Subbuses Bus Affected Resulting Conflict

Direction Cable
I/O Function Start End
Segments
Bit Bit
I-FPGA Out 0 4 Sending 1 More than two segment ranges are affected by the
data subbuses.
I-FPGA In 8 12 Receiving 3 Remedy: Use cable segment 6 for the I‑FPGA In
data function and cable segment 3 for the I‑FPGA Out
function. Thus cable segment range 1 ... 3 is used to
I-FPGA Out 22 26 Sending 6
send data and cable segment 6 is used to receive data.
data

Related topics References

I/O Functions of the Inter-FPGA Interface Framework (FPGA Programming

Handcode Framework - FPGA Interface Reference )

Calculating the Data Rate and Latency (SCALEXIO)

Calculating data rate The data rate of an inter-FPGA (sub)bus depends on the function settings for the
clock, the bit length and the data width.

DataRateMax = I-FPGA_Clock · (DataWidth ‑ 1) / BitLength

Resulting data rate for data transfer with bus synchronization The
maximum data rate with the default values is 562.5 Mbit/s for the entire bus
or 20.83 Mbit/s per bit.
DataRateMax,Bus = 125 MHz · (28 ‑ 1) Bit / 6
DataRateMax,Bit = 125 MHz · 1 Bit / 6

Resulting data rate for data transfer without bus synchronization The
maximum data rate with the default values is 582.3 Mbit/s for the entire bus or
20.83 Mbit/s per bit.

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DataRateMax,Bus = 125 MHz · 28 Bit / 6

DataRateMax,Bit = 125 MHz · 1 Bit / 6

Calculating latency The latency consists of a constant value and dependencies on the clock rate of
the inter-FPGA bus, filter depth, and on whether jitters and spikes occur.

General formula for the latency:

Latency = TI-FPGA Out + Tinter-FPGA Master + Tinter-FPGA Slave + TI-FPGA In

The formula use the following parameters:

TI-FPGA Out: Latency of the I‑FPGA Out FPGA function.

TI-FPGA Out = 8 ns

Tinter-FPGA Master: Latency of the inter-FPGA component to write data to the inter-FPGA bus.
Tinter-FPGA Master = ClockPeriodinter-FPGA · 2 ClockCycles

Tinter-FPGA Slave: Latency of the inter-FPGA component to read data from the inter-FPGA bus.

Tinter-FPGA Slave depends on the filter depth, and jitter and spikes on the bus lines:

§ Filter depth = 0, no jitter and spikes on the bus lines:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · 4 ClockCycles

§ Filter depth = 0 and jitter occurs:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · (4 + 1) ClockCycles

§ Filter depth >0, no jitter and spikes on the bus lines:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · (3 ClockCycles + FilterDepth)

§ Filter depth >0 and jitter occurs:

Tinter-FPGA Slave = ClockPeriodinter-FPGA · (3 ClockCycles + (FilterDepth + 1))

§ Filter depth >0 and jitter and spikes on the bus lines:
Tinter-FPGA Slave = ClockPeriodinter-FPGA · (3 ClockCycles +
(FilterDepth + 1 + [0 … FilterDepth]))
With the range [0 … FilterDepth] as the latency caused by spikes.

TI-FPGA In: Latency of the I‑FPGA In FPGA function.

TI-FPGA In = 8 ns

Latency calculation examples The following examples display the resulting latency for different applications.

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Calculation example for an inter-FPGA bus in standard mode The clock

rate of the inter-FPGA bus is 125 MHz in standard mode and the filter depth is
set to 2:
§ Latency = 56 ns + FilterDepth · 8 ns
§ If jitter occurs: Latency = 56 ns + (FilterDepth + 1) · 8 ns
§ If spikes occur: Latency = 56 ns + (FilterDepth +
[0 … FilterDepth]) · 8 ns
§ Maximal: Latency = 64 ns + (2 · FilterDepth) · 8 ns
With the default values, the latency is in the range 72 ns … 96 ns.
LatencyMin = 56 ns + 2 · 8 ns = 72 ns
LatencyMax = 64 ns + (2 · 2)· 8 ns = 96 ns

Calculation example for an inter-FPGA bus in expert mode

Note

Use the expert mode only if you have enough experience of configuring
buses and knowledge of checking the correctness of the configured
transmission with regard to the observed signal integrity at the applicable
temperature range.
The default values for the bit length, clock, and filter depth have been
tested by dSPACE.

The clock rate of the inter-FPGA bus is set to 250 MHz.

§ If the filter depth is set to 0:
Latency = 40 ns
§ If jitter occurs: Latency = 44 ns
§ If the filter depth is set to >0:
Latency = 36 ns + FilterDepth · 4 ns
§ If jitter occurs: Latency = 36 ns + (FilterDepth + 1) · 4 ns
§ If spikes occur: Latency = 36 ns + (FilterDepth +
[0 … FilterDepth]) · 4 ns
§ Maximal: Latency = 40 ns + (2 · FilterDepth) · 4 ns
With the default values and a 250 MHz clock rate, the latency is in the range
44 ns … 56 ns.
LatencyMin = 36 ns + 2 · 4 ns = 44 ns
LatencyMax = 40 ns + (2 · 2)· 4 ns = 56 ns

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 MicroLabBox: Using Remaining I/O Channels with RTI/RTLib

MicroLabBox: Using Remaining I/O Channels with RTI/RTLib

Introduction Only the DS1202 FPGA I/O Type 1 (Flexible I/O) framework lets you use
remaining I/O channels with the RTI blocksets/Real-Time Libraries (RTLib) for
MicroLabBox.

Where to go from here Information in this section

Features of the MicroLabBox Flexible I/O Framework................................ 81

The DS1202 FPGA IO Type 1 (Flexible I/O) framework lets you model
real-time application with the FPGA Programming Blockset together with
RTI blocksets/RTLib for MicroLabBox.

Workflow when Using MicroLabBox Flexible I/O Framework.................... 82

The compatibility of the MicroLabBox frameworks lets you save time
when you model and test the FPGA application.

Features of the MicroLabBox Flexible I/O Framework

Introduction The DS1202 FPGA IO Type 1 (Flexible I/O) framework lets you handcode
real-time applications for MicroLabBox together with the RTI1202 blockset,
the RTI Electric Motor (EMC) blockset, and the Real-Time Library (RTLib) for
MicroLabBox.

An I/O channel of MicroLabBox is either used by the standard I/O features

of MicroLabBox or by a custom FPGA application. The standard I/O features
of MicroLabBox let you access the I/O interface with RTI blocksets/RTLib for
MicroLabBox. These features are automatically implemented into the FPGA if the
real‑time application that you load to the hardware does not contain a custom
FPGA application. Custom FPGA applications that are built with the DS1202
FPGA I/O Type 1 framework do not provide the standard I/O features for
remaining I/O channels. Therefore, you cannot access the remaining I/O channels
with RTI blocksets/RTLib for MicroLabBox.

Features of the DS1202 FPGA The framework provides the following features:
I/O Type 1 (Flexible I/O) § During the build process of the custom FPGA application, the standard I/O
framework features for remaining I/O channels are added. The standard I/O features let
you use the remaining I/O channels with RTI blocksets/RTLib for MicroLabBox.
§ The framework provides the same I/O functions as the DS1202 FPGA I/O Type
1 framework.
§ The framework is compatible with the DS1202 FPGA I/O Type 1 framework.
You can switch between the DS1202 FPGA I/O Type 1 (Flexible I/O) and the
DS1202 FPGA I/O Type 1 frameworks. The compatibility lets you save time

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when you model and test the the FPGA application. Refer to Workflow when
Using MicroLabBox Flexible I/O Framework on page 82.
§ I/O channels that are used by the DS1202 FPGA I/O Type 1 (Flexible I/O)
framework are marked within the RTI1202 and the EMC blocksets with an
asterisk.

You must not access the same channel with the DS1202 FPGA I/O Type 1
(Flexible I/O) framework and the RTI1202 or EMC blocksets.

Note

The DS1202 Serial Interface blocks (rti1202serlib) do not mark I/O

channels that are used by the custom FPGA application with an asterisk.
§ If you use DS1202 Serial Interface blocks, make sure that the custom
FPGA application does not use the same communication channels.

Related topics Basics

Overview of the RTI Electric Motor Control Blockset (RTI Electric Motor Control
Blockset Reference )

References

Overview of RTI1202 (MicroLabBox RTI Reference )

Workflow when Using MicroLabBox Flexible I/O Framework

Introduction Building FPGA applications with the DS1202 FPGA I/O Type 1 framework is
substantially faster than building FPGA applications with the DS1202 FPGA
I/O Type 1 (Flexible I/O) framework. The implementation of the standard I/O
features, which let you use the remaining I/O channels with RTI blocksets/RTLib
for MicroLabBox, takes additional FPGA resources and more build time.

The compatibility of the frameworks lets you use the DS1202 FPGA I/O Type 1
framework for handcoding and testing and the DS1202 FPGA I/O Type 1

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(Flexible I/O) framework for building the final FPGA application including the
standard I/O features for the remaining I/O channels.

Recommended workflow 1. Model, test, and build the FPGA application with the DS1202 FPGA I/O
Type 1 framework (DS1302_XC7K325T) until you have the final version.
2. Copy the cm file, the hc_fpga_framework_ini_DS1302.m file, and
custom code to the DS1202 FPGA I/O Type 1 (Flexible I/O) framework
(DS1302_XC7K325T_FLEXIBLEIO).
3. Build the final FPGA application.
4. Implement the processor interface with RTI blocksets/RTLib for MicroLabBox
to access the remaining I/O channels.
5. Build the processor application.
The build process makes sure that no I/O channel is accessed multiple times,
for example, by the FPGA application and the processor application.
6. Download the application to MicroLabBox.

Related topics Basics

Detailed Instructions on the Handcode Workflow..................................................................... 29

Features of the MicroLabBox Flexible I/O Framework................................................................. 81

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DS6602: Accessing the DDR4 RAM

Introduction The DS6602 (KU15P) FPGA Base Board framework lets you access the DDR4
RAM of the FPGA base board.

Where to go from here Information in this section

Accessing the DDR4 RAM of the DS6602................................................ 84

The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be
used by the FPGA application.

Initializing the DDR4 RAM of the DS6602................................................ 85

Executing the FPGA application with defined DDR4 RAM data values.

Accessing the DDR4 RAM of the DS6602

Introduction The DS6602 FPGA Base Board provides a 4 GB DDR4 RAM that can be used by
the FPGA application.

The RAM interface always handles 512 bits at once. Therefore, the FPGA
application can read/write 16 x 32 bits data or 8 x 64 bits data within one
memory access.

You can select different I/O functions to access the DDR4 RAM:
§ DDR4 32 Mode 1 and DDR4 64 Mode 1 to read/write 32/64-bit values.
These I/O types use the memory access mode 1.
§ DDR4 32 Mode 2 and DDR4 64 Mode 2 to read/write 32/64-bit values.
These I/O types use the memory access mode 2.

Tip

The DDR4 RAM processes the data values as raw data.

Memory access modes The FPGA Programming Handcode Framework provides two memory access
modes:
§ Mode 1
Mode 1 addresses one memory area of 512 bits, each with read/write access.
§ Mode 2
Mode 2 addresses two memory areas of 256 bits, each with read/write access.

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The following example shows the memory areas addressed by the different
access modes.
Mode 1 Mode 2

2 1024 4 1024

768 3 768

1 512 2 512

256 1 256

Address 0 Bit 0 Address 0 Bit 0

Memory Memory

Note

The memory areas are addressed differently by the different access modes.

Optimizing read/write access To decrease the read/write time, use consecutive addresses for read/write
accesses. A random address access approximately triples the read/write time:

Read access Linear addressing 7.37 GB/s

Random addressing 2.58 GB/s
Write access Linear addressing 6.77 GB/s
Random addressing 2.29 GB/s

Related topics References

I/O Functions of the DS6602 FPGA Base Board Framework (FPGA Programming
Handcode Framework - FPGA Interface Reference )

Initializing the DDR4 RAM of the DS6602

Introduction You can provide a file with initial values for the RAM memory to start the FPGA
application with defined DDR4 RAM data values. The processing hardware writes
the initial values from a SCALEXIO SSD to the FPGA base board during the
initialization phase of the SCALEXIO system.

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Generating an initialization The initialization file is a binary file. You can use the following MATLAB script to
file generate an initialization file with MATLAB.
% generate sample 32 bit values (4GB – 1 Word) 1..2^30-1 (2^30*4 Byte = 4 GB)
% generate sample 64 bit values (4GB – 1 Word) 1..2^29-1 (2^29*8 Byte = 4 GB)
ddr4_4gb = 1:2^30-1;
% open, write, close file
fid = fopen('ddr4_4gb.bin', 'w');
fwrite(fid, ddr4_4gb, 'uint32');
% or as different data type
% fwrite(fid, ddr4_4gb, 'single');
% fwrite(fid, ddr4_4gb, 'double');
% 64 bit -> use only half as many elements
…
fclose(fid)

Note

You can use any data type to initialize the DDR4 RAM.

Providing the initialization You download the initialization file to a SCALEXIO SSD to provide the initial
file to the SCALEXIO system values. For instructions, refer to How to Initialize the DDR4 RAM of the DS6602
(ConfigurationDesk I/O Function Implementation Guide ).

Related topics References

DDR4 32 Mode 1 (FPGA Programming Handcode Framework - FPGA Interface

Reference )
DDR4 32 Mode 2 (FPGA Programming Handcode Framework - FPGA Interface
Reference )
DDR4 64 Mode 1 (FPGA Programming Handcode Framework - FPGA Interface
Reference )
DDR4 64 Mode 2 (FPGA Programming Handcode Framework - FPGA Interface
Reference )

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 DS6601, DS6602: Coding a Customized MGT Protocol

DS6601, DS6602: Coding a Customized MGT Protocol

Introduction The DS6601 (KU035) FPGA Base Board and the DS6602 (KU15P) FPGA Base
Board frameworks let you customize MGT protocols.

Customizing MGT Protocols

Supported platforms MGT communication is supported by SCALEXIO systems with a DS6601 or

DS6602 FPGA Base Board with an installed MGT module.

Block diagram of the The DS6601 and DS6602 FPGA base boards provide a connector to insert an
interface optical adapter for MGT (MGT module). The following illustration shows the
basic components to support the MGT communication bus.

FPGA base board

Reference
GTH transceiver clock
(master)
GTH transceiver
FPGA (slave 1)
MGT module
GTH transceiver
(slave 2)
GTH transceiver
(slave 3)

Components description The following table shows the description of the components.

Component Description
FPGA The FPGA processes the build FPGA application.
GTH The GTH transceivers are configurable transceivers that are integrated with the logic resources of
transceiver the FPGA. The GTH transceivers support line rates from 500 Mbit/s … 16.375 Gbit/s. The master
transceiver receives the differential reference clock signal and provide it to the slave transceivers.
Master or slave has no influence on the MGT communication.
The GTH transceivers can be configured by the FPGA application to support different protocols, line
rates, etc.
For details on the GTH transceiver, refer to
https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf.
Reference This clock provides the configured reference frequency for the GTH transceivers.
clock
MGT module The MGT module is an optical adapter that can be connected to the FPGA base board. The MGT
module provides four channels for communication.

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Component Description
The order number of the SCALEXIO MGT modules are as follows:
§ DS6601_MGT1 for the DS6601 FPGA Base Board.
§ DS6602_MGT1 for the DS6602 FPGA Base Board.

Using a customized protocol You can use the IP Catalog of Vivado to customize a predefined protocol.
The IP Catalog provides a list of IP cores that can be customized. For more
information, refer to https://docs.xilinx.com/r/en-US/ug896-vivado-ip.

The IP Catalog lets you generate a net list that you can integrate in the
handcode. You can also include optional features like FIFOs for the inports and
outports, or a reset logic for the GTH transceiver.

Required settings The following parameters depend on the FPGA base board and must be set to a
specific value in the VHDL file:
§ The low power mode of the equalizer must be enabled.
gt_rxlpmen => (others => '1')
§ The differential swing voltage must be set to board-specific value:
§ DS6601: 460 mVpp (peak-to-peak voltage)
gt_txdiffctrl => "0100"
§ DS6602: 498 mVpp
gt_txdiffctrl => "01010"

Related topics References

MGT In (FPGA Programming Handcode Framework - FPGA Interface Reference )

MGT Out (FPGA Programming Handcode Framework - FPGA Interface
Reference )

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 DS6601, DS6602: Configuring the Timeout of a Watchdog I/O Function

DS6601, DS6602: Configuring the Timeout of a Watchdog I/O

Function
Introduction The DS6601 (KU035) FPGA Base Board and the DS6602 (KU15P) FPGA Base
Board frameworks provide a watchdog I/O function to check if the processor
application is alive.

Where to go from here Information in this section

How to Configure the Condition when the Watchdog Expires................. 89

To specify a fixed or adaptive timeout for the watchdog timer.

Information in other sections

I/O Functions of the DS6601 FPGA Base Board Framework

(FPGA Programming Handcode Framework - FPGA Interface
Reference )
The DS6601 (KU035) FPGA Base Board framework of the DS6601 FPGA
Base Board provides the standard I/O functionality of the board.

I/O Functions of the DS6602 FPGA Base Board Framework

(FPGA Programming Handcode Framework - FPGA Interface
Reference )
The DS6602 (KU15P) FPGA Base Board framework of the DS6602 FPGA
Base Board provides the standard I/O functionality of the board.

How to Configure the Condition when the Watchdog Expires

Objective To specify a fixed or adaptive timeout for the watchdog timer.

Basics on the watchdog timer The watchdog I/O function provides a timer that must be reset by a keep-alive
signal of the processor application before a configured timeout expires.

Providing the keep-alive signal The keep-alive signal is a trigger signal. To

provide the trigger signal, you can connect the model port to a constant in the
processor model. Each read process triggers the FPGA application. The read value
itself has no influence on the triggering.

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Configuring the timeout The watchdog I/O function provides no settings to

configure the timeout. You configure the timeout in ConfigurationDesk.
There are two timeout modes to configure the expiration of the watchdog timer:
§ You can use a fixed timeout, i.e., you specify a time interval in seconds that
does not change.
The fixed timeout is useful if a periodic task triggers the keep-alive signal.
§ You can use an adaptive timeout, i.e., you specify a factor by how much
longer than the last task execution time to wait for the keep-alive signal. In
this mode, the watchdog measures the time interval between the last two
keep-alive signals and multiplies it by the specified factor to constantly adjust
the timeout value.
The adaptive timeout is useful if an asynchronous task triggers the keep-alive
signal.
If the specified time interval expires without a keep-alive signal being transmitted
to the FPGA application, the watchdog timer expires and outputs a timeout.

Preconditions The following preconditions must be fulfilled:

§ You built an FPGA application with watchdog functionalities. Refer to
Watchdog (FPGA Programming Handcode Framework - FPGA Interface
Reference ).
§ In ConfigurationDesk, the FPGA application is added to the signal chain as an
FPGA custom function block. Refer to How to Import FPGA Custom Function
Block Types Provided by an FPGAC File (ConfigurationDesk I/O Function
Implementation Guide ).

Method To configure the condition when the watchdog expires

1 In ConfigurationDesk, select the Watchdog function of the FPGA custom
function block.

2 In the Properties Browser, select the timeout mode for the watchdog.
3 If you selected the fixed timeout mode, enter a fixed timeout in seconds.
4 If you selected an adaptive timeout, enter an integer factor by how much
longer than the last task execution time the watchdog timer waits for the
keep-alive signal.
5 To activate the watchdog feature, map the Trigger function inport to a
model port that provides the keep-alive signal.

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 DS6601, DS6602: Configuring the Timeout of a Watchdog I/O Function

Result You configured the timeout for the watchdog timer. If the specified time interval
expires without a keep-alive signal being transmitted to the FPGA application,
the watchdog timer expires and outputs a timeout to trigger the implemented
FPGA functionality.

If a timeout occurs, you must restart the real-time application to reset the
watchdog.

Tip

In ConfigurationDesk, you deactivate the watchdog functionality by not

mapping the Trigger port of the watchdog function to a model port.
If deactivated, the Status port of the Watchdog block always outputs 1 in
the FPGA application.

Related topics Basics

Configuring the Basic Functionality (FPGA) (ConfigurationDesk I/O Function

Implementation Guide )

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 Troubleshooting

Troubleshooting

Introduction When working with the FPGA Programming Software there are some problems
which can arise.

Problems and Their Solutions

Building an FPGA application If you use a DS6602 FPGA Base Board, the build process issues a critical warning
that the design failed to meet the timing requirements:

Implementation (1 critical warning)

§ Route Design (1 critical warning)
§ [Timing 38-282] The design failed to meet the timing requirements. Please
see the timing summary report for details on the timing violations.
§ Intra-Clock Paths
Clock: clk_out4_clk_ctrl_kup
Type: Pulse Width Violation
Required:3.333
Actual: 4.000
Slack: -0.667
At Pin: FeedbackBaseBoardTemplate_inst/…/REFCLK
…/io_bus_master_dlyctrl_gen.delayctrl_REPLICATED_0/REFCLK
…/io_bus_master_dlyctrl_gen.delayctrl_REPLICATED_0_1/REFCLK
…/io_bus_master_dlyctrl_gen.delayctrl_REPLICATED_0_2/REFCLK
…/io_bus_master_dlyctrl_gen.delayctrl_REPLICATED_0_3/REFCLK
…/io_bus_master_dlyctrl_gen.delayctrl_REPLICATED_0_4/REFCLK
…/io_bus_master_dlyctrl_gen.delayctrl_REPLICATED_0_5/REFCLK

Solution Ignore this warning because the warning is issued in error.

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 Index

S
Index
components 10
A FPGA Programming Handcoding Framework
SCALEXIO FPGA base board
hardware support 19
adapting processor model interface 45 feature overview 22
AMD Design Suite 17 script interface
G configuring FPGA code 32
generating a processor model interface 44 generating FPGA model INI file 39
B
generating FPGA bitstream 37 generating FPGAC file 39
best practise 26 script interface function
generating FPGA custom function 39
building FPGA application 37 HCFPGAFrameworkInit 32
generating FPGA model INI file 39
building processor application 48 HCFPGAModelIniGenerate 39
generating FPGAC file 39
burnapplication folder 50 SDF file 62
simulating a processor model 47
H
C specifying FPGA functionality 33
handcode FPGA framework INI file 30 specifying FPGA I/O interface 30
cm.v 35
handcoding processor interface 54 Specifying the FPGA framework 30
cm.vhd 34
hardware support starting the simulation 48
Common Program Data folder 6
FPGA Programming Handcoding supported AMD design tools 17
components of the FPGA Programming
Framework 19 supported MATLAB versions 17
Blockset 10
hc_fpga_framework_ini_<Framework_Name>.m supported operating systems 17
configuring FPGA code
30
via script interface 32
HC_Vivado2014.xpr 34
configuring FPGA code with I/O 32 T
HC_Vivado2014_verilog.xpr 35
creating a burn application 49 TRC file 62
HcUsed 31
customizing architecture section 34 triggering interrupt-driven tasks 46
customizing Vivado project file 34 troubleshooting 93
I
building FPGA application 93
D I/O modules
for MicroAutoBox II 21
Documents folder 6 U
for MicroAutoBox III 21
downloading FPGA application 61 Unsupported features 27
for SCALEXIO DS2655 23
downloading processor application 61 using FPGA model INI file for the processor
implementing the processor interface 54
DS1514 model interface 40
interrupt handling 46
feature overview 20
DS1552 Multi-I/O Module
L W
feature overview 21
DS1552B1 Multi-I/O Module Local Program Data folder 6 workflow
feature overview 21 handcode FPGA 25
DS1554 Engine Control I/O Module M
feature overview 21
MAP file 62
DS2655 FPGA Base Board
MicroAutoBox II
feature overview 22
feature overview 20
DS2655M1 Multi-I/O Module
MicroAutoBox III
feature overview 23
feature overview 20
DS2655M2 Digital I/O Module
MicroLabBox
feature overview 23
feature overview 19
DS6601 FPGA Base Board
MicroLabBox II
feature overview 22
feature overview 20
DS6602 FPGA Base Board
feature overview 22
DS6651 Multi-I/O Module P
feature overview 23 preparing the handcode environment 30
processor communication
E MicroAutoBox II 14
MicroAutoBox III 14
example
MicroLabBox 13
configuring FGPA code with I/O 33
MicroLabBox II 13
I/O interface specification 31
SCALEXIO 14
exchanging data with the processor model 13
processor interface 10
experimenting with FPGA application 61
programming FPGA 49
programming into flash 49
F programming into RAM 50
FPGA architecture 8
FPGA data synchronization 27
FPGA Programming Blockset

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 Index

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