Verilog

Verilog
• Verilog HDL
– General-purpose
– Easy to learn, easy to use
– Similar in syntax to C
– Allows different levels of abstraction and mixing them
– Supported by most popular logic synthesis tools
– Post-logic-synthesis simulation libraries by all fabrication
vendors
Design Flow
 Trends in HDLs

• Design at behavioral level

• Formal verification techniques
• Very high speed and time critical circuits
– e.g. microprocessors
– Mixed gate-level and RTL designs
• Hardware-Software Co-design
– System-level languages: SystemC, SpecC, …
Basics of Digital Design Using HDLs
Stimulus block

Generating Checking
inputs Circuit Under Design outputs
to CUD (CUD) of CUD
4
8

Test bench
Design Methodologies
 Levels of abstraction
• Verilog supported levels of abstraction
– Behavioral (algorithmic) level
• Describe the algorithm used
• Very similar to C programming
– Dataflow level
• Describe how data flows between registers and is processed
– Gate level
• Interconnect logic gates
– Switch level
• Interconnect transistors (MOS transistors)
• Register-Transfer Level (RTL)
– Generally known as a combination of behavioral+dataflow that is
synthesizable by EDA tools
 Modules
module <module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule

• Example:
module TFF(q,clock, reset);
...
<functionality of T_flipflop>
...
endmodule
 Verilog Basic Building Block
• Module

module not_gate(in, out); // module name+ports

// comments: declaring port type
input in;
output out;

// Defining circuit functionality

assign out = ~in;

endmodule
 Instances
module ripple_carry_counter(q, clk, reset);

output [3:0] q;
input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);

endmodule
Module
 Example (cont’d)
module stimulus;
reg clk; reg reset; wire[3:0] q;

// instantiate the design block

ripple_carry_counter r1(q, clk, reset);

// Control the clk signal that drives the design block.

initial clk = 1'b0;
always #5 clk = ~clk;

// Control the reset signal that drives the design block

initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $stop;
end

initial // Monitor the outputs

$monitor($time, " Output q = %d", q);
endmodule
Ports
Ports Example
Port Example
Port Connections
Ports
Registers and nets

Value Definition
Logic zero or
0
false
Logic one or
1
true
Unknown
x
logical value
High
z impedance of
tristate gate
 Registers and nets
• NETS –
The nets variables represent the physical connection
between structural entities.
• These variables do not store values (except trireg);
have the value of their drivers which changes
continuously by the driving circuit.
• Some net data types are wire, tri, wor, trior, wand,
triand, tri0, tri1, supply0, supply1 and trireg.
• wire is the most frequently used type.
• A net data type must be used when a signal is: driven
by the output of some device.
• declared as an input or in-out port.
• on the left-hand side of a continuous assignment.
 Registers and nets

• wire a; // Declare net a for the above circuit

• wire b,c; // Declare two wires b,c for the
above circuit
• wire d = 1'b0; // Net d is fixed to logic value 0
at declaration.
 Registers and nets
• Registers –
The register variables are used in procedural blocks which
store values from one assignment to the next.
• An assignment statement in a procedure acts as a trigger
that changes the value of the data storage element.
• Some register data types are: reg, integer, time and real.
• reg is the most frequently used type.
• Reg is used for describing logic, integer for loop variables
and calculations, real in system modules,
and time and realtime for storing simulation times in test
benches.
 Registers and nets
• Register
 Arrays
• Arrays are allowed in Verilog for reg, integer, time, real,
realtime and vector register datatypes.
• Multi-dimensional arrays can also be declared with
any number of dimensions.
• Arrays of nets can also be used to connect ports of
generated instances.
• Each element of the array can be used in the same
fashion as a scalar or vector net.
• Arrays are accessed by <array_name>[<subscript>].
• For multi-dimensional arrays, indexes need to be
provided for each dimension.
Arrays
Arrays
 Identifiers and Keywords
• Keywords are special identifiers reserved to
define the language constructs.
• Keywords are in lowercase.
Identifiers and Keywords
 Parameters
• Verilog allows constants to be defined in a
module by the keyword parameter.
• Parameters cannot be used as variables.
• Parameter values for each module instance
can be overridden individually at compile
time.
• This allows the module instances to be
customized.
 Parameters
• Example
Parameters
Verilog Operators
Operators
Verilog Operators
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
Writing Expressions
 Behavioral Modelling
• Initial Block
 Behavioral Modelling
• Initial Block
• All statements inside an initial statement
constitute an initial block.
• An initial block starts at time 0, executes exactly
once during a simulation, and then does not
execute again.
• If there are multiple initial blocks, each block
starts to execute concurrently at time 0.
• Each block finishes execution independently of
other blocks.
• Multiple behavioral statements must be grouped,
typically using the keywords begin and end.
 Behavioral Modelling
Always statement
• The always statement starts at time 0 and
executes the statements in the always block
continuously in a looping fashion.
• This statement is used to model a block of
activity that is repeated continuously in a
digital circuit.
 Behavioral Modelling
Always statement
 Behavioral Modelling
• Blocking Assignments
Blocking assignment statements are executed in the order they are specified in a
sequential block.
 Behavioral Modelling
Non Blocking statement

• Nonblocking assignments allow scheduling of

assignments without blocking execution of the
statements that follow in a sequential block.
• A <= operator is used to specify nonblocking
assignments.
 Behavioral Modelling
• Non Blocking statement
 Behavioral Modelling
• Non Blocking statement
 Behavioral Modelling
• Control Statement (If -else)
 Behavioral Modelling
• Control Statement (If -else)
 Behavioral Modelling
• Control Statement (case)
 Behavioral Modelling
• Control Statement (case)
 Loops
While Loop
• If the loop is entered when the while-
expression is not true, the loop is not
executed at all.
Loops
 Loops
• For Loop
Loops
 Loops
Repeat Loop
• The keyword repeat is used for this loop. The
repeat construct executes the loop a fixed
number of times.
 Loops
Repeat Loop
 Loops
• Repeat Loop
 Loops
Forever loop
• The keyword forever is used to express this loop.
• The loop does not contain any expression and
executes forever until the $finish task is
encountered.
• The loop is equivalent to a while loop with an
expression that always evaluates to true, e.g.,
while(1).
• A forever loop can be exited by use of the disable
statement.
 Loops
• Forever loop