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TPS53819A
SLUSB56B – NOVEMBER 2012 – REVISED APRIL 2019

TPS53819A 3-V to 28-V Input, 40-A, Eco-Mode™, D-CAP2™ Synchronous

Buck Controller With PMBus™
1 Features 2 Applications
•
1 Conversion Input Voltage 3 V to 28 V • Point-of-load power In:
• VDD input voltage 4.5 V to 28 V – Storage computers
• Output voltage 0.6 V to 5.5 V – Server computers
• Supports all ceramic output capacitors – Multi-function printers
• Reference voltage: 600 mV ±0.5% tolerance – Embedded computing
• ±9% Voltage adjustment with PMBus™
• Built-in 5-V LDO 3 Description
• D-CAP2™ mode with 100-ns load-step response The TPS53819A device is a small-sized, single buck
controller with adaptive on-time D-CAP2 mode control
• Auto-skip Eco-mode™ for light-load efficiency and PMBus. The device is suitable for low output
• Adaptive on-time control architecture with eight voltage and high current, system power rail, or similar
selectable frequencies using PMBus point-of-load (POL) power supply in digital consumer
• Supports voltage margining using PMBus products. Small package with minimal pin-count
saves space on the PCB, while the programmability
• Programmable soft-start time using PMBus and fault report via PMBus simplify the power supply
• Programmable power-on delay using PMBus design. The skip-mode at light-load condition
• Programmable VDD UVLO level using PMBus combined with strong gate drivers and low-side FET
on-resistance (RDS(on)) current sensing can support
• Fault report using PMBus low-loss and high efficiency operation, over a broad
• Pre-charged start-up capability load range. The conversion input voltage, which is
• Built-In output discharge the high-side FET drain voltage, ranges from 3 V to
• Power-good output with programmable delay 28 V. The supply voltage (VDD) is from 4.5 V to 28 V.
The output voltage ranges from 0.6 V to 5.5 V. The
• Internal overvoltage, undervoltage, and device is available in a 16-pin, QFN package and is
overcurrent limit protections specified from –40°C to +85°C.
• Thermal shutdown (non-latch)
• 3 mm × 3 mm, 16-pin, QFN package Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Create a custom design using the TPS53819A
TPS53819A QFN (16) 3.00 mm × 3.00 mm
with the WEBENCH® Power Designer
(1) For all available packages, see the orderable addendum at
the end of the datasheet.

Simplified Application
VREG
V3P3 EN VIN
VIN CSD87350 SW
VOUT

16 15 14 13 VIN SW

ADDR PGOOD EN VBST

1 SCL SW 12 TG SW

2 SDA DRVH 11

TPS53819A DRVL 10 TGR BG

3 ALERT
VREG 9 PGND
4 TRIP
GND

VDD
VO

FB

5 6 7 8

VDD

UDG-12118

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 19
2 Applications ........................................................... 1 7.5 Programming........................................................... 21
3 Description ............................................................. 1 7.6 Register Maps ........................................................ 24
4 Revision History..................................................... 2 8 Application and Implementation ........................ 34
8.1 Application Information............................................ 34
5 Pin Configuration and Functions ......................... 3
8.2 Typical Application ................................................. 34
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 9 Power Supply Recommendations...................... 40
6.2 ESD Ratings ............................................................ 4 10 Layout................................................................... 41
6.3 Recommended Operating Conditions....................... 4 10.1 Layout Guidelines ................................................. 41
6.4 Thermal Information .................................................. 5 10.2 Layout Example .................................................... 42
6.5 Electrical Characteristics........................................... 5 11 Device and Documentation Support ................. 44
6.6 Timing Requirements ................................................ 8 11.1 Device Support...................................................... 44
6.7 Switching Characteristics .......................................... 9 11.2 Receiving Notification of Documentation Updates 44
6.8 Typical Characteristics ............................................ 10 11.3 Community Resources.......................................... 44
7 Detailed Description ............................................ 16 11.4 Trademarks ........................................................... 44
7.1 Overview ................................................................. 16 11.5 Electrostatic Discharge Caution ............................ 44
7.2 Functional Block Diagram ....................................... 16 11.6 Glossary ................................................................ 44
7.3 Feature Description................................................. 17 12 Mechanical, Packaging, and Orderable
Information ........................................................... 45

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2015) to Revision B Page

• Added links for Webench; editorial updates - no changes to technical data ......................................................................... 1

Changes from Original (November 2012) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1

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5 Pin Configuration and Functions

RGT Package
16 Pin QFN
Top View

PGOOD
ADDR

VBST
EN
16 15 14 13

SCL 1 12 SW

SDA 2 11 DRVH
TPS53819A
ALERT 3 10 DRVL

TRIP 4 9 VREG

5 6 7 8
FB

GND
VO

VDD
Pin Functions
PIN
I/O (1) DESCRIPTION
NAME NO.
PMBus address configuration. Connect this pin to a resistor divider between VREG and GND to
ADDR 16 I
program different address settings. (See Table 2 for details.)
ALERT 3 O Open-drain alert output for the PMBus interface.
High-side MOSFET floating driver output that is referenced to SW node. The gate drive voltage is
DRVH 11 O
defined by the voltage across bootstrap capacitor between VBST and SW.
Synchronous MOSFET driver output that is referenced to GND. The gate drive voltage is defined by
DRVL 10 O
VREG voltage.
Enable pin that can turn on the DC/DC switching converter. EN pin works in conjunction with the CP
EN 14 I
bit in PMBus ON_OFF_CONFIG register.
Output voltage feedback input. Connect this pin to a resistor divider between output voltage and
FB 6 I
GND.
GND 7 G Ground pin.
Open drain power good status signal. Provides start-up delay time after FB voltage falls within
PGOOD 15 O
specified limits. After FB voltage goes out of specified limits, PGOOD goes low within 2 µs.
SCL 1 I Clock input for the PMBus interface.
SDA 2 I/O Data I/O for the PMBus interface.
SW 12 P Output switching terminal of power converter. Connect this pin to the output inductor.
OCL detection threshold setting pin. A 10-µA current with a TC of 4700ppm/°C is sourced out of the
TRIP 4 I/O TRIP pin and is used to set the OCL trip voltage as follows:
VOCL= VTRIP/8 and ( VTRIP ≤ 3 V, VOCL ≤ 375 mV)
Supply rail for high-side gate driver (boost terminal). Connect bootstrap capacitor from this pin to SW
VBST 13 P
node. Internally connected to VREG via bootstrap PMOS switch.
VDD 8 P Controller power supply input.
VO 5 I Output voltage.
VREG 9 P 5-V low-drop-out (LDO) output. Supplies the internal analog and driver circuitry.

(1) I=Input, O=Output, P=Power, G=Ground

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VBST –0.3 38
VBST (3) –0.3 6
EN –0.3 7.7
(2)
Input voltage VO, FB, SCL, SDA, ADDR –0.3 6 V
VDD –0.3 30
DC –3 32
SW
Pulse < 30% of the repetitive period –5 32
DC –3 38
DRVH
Pulse < 30% of the repetitive period –5 38
(2)
Output voltage DRVH (3), DRVL –0.3 6 V
ALERT, VREG, TRIP –0.3 6
PGOOD –0.3 7.7
Junction temperature, TJ 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VBST –0.1 35.5
VBST (1) –0.1 5.5
EN –0.1 6.5 V
Input voltage range VO, FB, SCL, SDA, ADDR –0.1 5.5
VDD 4.5 28
DC –3 30
SW V
Pulse < 30% of the repetitive period –4.5 30
DC –3 35.5
DRVH V
Pulse < 30% of the repetitive period –4.5 35.5
Output voltage range DRVH (1), DRVL –0.1 5.5 V
ALERT, VREG –0.1 5.5 V
PGOOD –0.1 6.5 V
Operating free-air temperature, TA –40 85 °C

(1) Voltage values are with respect to the SW terminal.

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6.4 Thermal Information

TPS53819A
THERMAL METRIC (1) RGT (QFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 51.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 85.4 °C/W
RθJB Junction-to-board thermal resistance 20.1 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 19.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.0 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range, VVREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TA = 25°C, no load, power
IVDD VDD bias current conversion enabled (no 920 μA
switching)
TA = 25°C, no load, power
IVDDSTBY VDD standby current 610 μA
conversion disabled
INTERNAL REFERENCE AND FEEDBACK REGULATION VOLTAGE
VFB Feedback regulation voltage FB w/r/t GND, CCM condition 600 mV
FB w/r/t GND, 0°C ≤ TJ ≤
VFBTOL Feedback voltage tolerance 597 600 603 mV
85°C
FB w/r/t GND, 0°C ≤ TA ≤
VDACTOL1 DAC voltage tolerance 1 85°C, all settings with –4.8 4.8 mV
VOUT_ADJUSTMENT only
FB w/r/t GND, 0°C ≤ TA ≤
VDACTOL2 DAC voltage tolerance 2 85°C, all settings with –4.8 4.8 mV
VOUT_MARGIN only
FB w/r/t GND, 0°C ≤ TA ≤
85°C, with
VDACTOL3 DAC voltage tolerance 3 VOUT_ADJUSTMENT = 0Dh –4.8 4.8 mV
and VOUT_MARGIN = 70h
for +5%
FB w/r/t GND, 0°C ≤ TA ≤
85°C, with
VDACTOL4 DAC voltage tolerance 4 VOUT_ADJUSTMENT = 13h –4.8 4.8 mV
and VOUT_MARGIN = 07h
for -5%
Loop comparator input offset
VIOS_LPCMP VREF to VFB, TA = 25°C –2.5 2.5 mV
voltage
IFB FB pin input current VFB = 600 mV –1 1 μA
OUTPUT VOLTAGE
VVO = 0.5 V, power
IVODIS VO discharge current 10 12 mA
conversion disabled
DRIVER
Source, IDRVH = 50 mA 1.6
RDRVH DRVH resistance
Sink, IDRVH = 50 mA 0.6
Ω
Source, IDRVL = 50 mA 0.9
RDRVL DRVL resistance
Sink, IDRVL = 50 mA 0.5

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Electrical Characteristics (continued)

over operating free-air temperature range, VVREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL BOOT STRAP SWITCH
VVREG-VBST, TA = 25°C, IF =
VF Forward voltage 0.1 0.2 V
10 mA
TA = 25°C, VVBST = 33 V, VSW
IVBST VBST leakage current 0.01 1.5 μA
= 28 V
ENABLE LOGIC THRESHOLD
VL EN low-level voltage 0.5 V
VH EN high-level voltage 1.8 V
VHYST EN hysteresis voltage 0.22 V
ILEAK EN input leakage current -1 0 1 μA
POWER GOOD COMPARATOR
PGOOD in from higher 105% 108% 111%
PGOOD in from lower 89% 92% 95%
VPGTH Powergood threshold
PGOOD out to higher 113% 116% 119%
PGOOD out to lower 81% 84% 87%
IPG PGOOD sink current VPGOOD = 0.5 V 6.9 mA
IPGLK PGOOD leakage current VPGOOD = 5.0 V -1 0 1 μA
CURRENT DETECTION
TA = 25°C, VTRIP = 0.4 V,
ITRIP TRIP source current 9 10 11 μA
RDS(on) sensing
TRIP source current
TCITRIP RDS(on) sensing 4700 ppm/°C
temperature coefficient (1)
VTRIP TRIP voltage range RDS(on) sensing 0.2 3 V
VTRIP = 3.0 V, RDS(on) sensing 360 375 390
VOCLP Positive current limit threshold VTRIP = 1.6 V, RDS(on) sensing 190 200 210 mV
VTRIP = 0.2 V, RDS(on) sensing 20 25 30
VTRIP = 3.0 V, RDS(on) sensing –390 –375 –360
Negative current limit
VOCLN VTRIP = 1.6 V, RDS(on) sensing –212 –200 –188 mV
threshold
VTRIP = 0.2 V, RDS(on) sensing –30 –25 –20
VZC Zero cross detection offset 0 mV
PROTECTIONS
VREG UVLO threshold Wake-up 3.32
VVREGUVLO V
voltage Shutdown 3.11
VOVP OVP threshold voltage OVP detect voltage 117% 120% 123%
tOVPDLY OVP propagation delay time With 100-mV overdrive 430 ns
VUVP UVP threshold voltage UVP detect voltage 65% 68% 71%
THERMAL SHUTDOWN
Shutdown temperature 140
TSDN Thermal shutdown threshold °C
Hysteresis 40
LDO VOLTAGE
VREG LDO output voltage VIN = 12 V, ILOAD = 10 mA 4.5 5 5.5 V
LDO low droop drop-out VIN = 4.5 V, ILOAD = 30 mA,
VDOVREG 365 mV
voltage TA = 25°C
(1)
ILDO(max) LDO overcurrent limit VIN = 12 V, TA = 25°C 152 mA

(1) Specified by design. Not production tested.

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Electrical Characteristics (continued)

over operating free-air temperature range, VVREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD UVLO VOLTAGE
VDDINUVLO<2:0> = 0xx 10.2
VDDINUVLO<2:0> = 101 4.1 4.25 4.4
VDDUVLO VDD UVLO voltage V
VDDINUVLO<2:0> = 110 6.0
VDDINUVLO<2:0> = 111 8.1
VDDHY-UVLO VDD UVLO hysteresis voltage 0°C ≤ TJ ≤ 85°C 0.2 V
PMBus SCL and SDA INPUT BUFFER LOGIC THRESHOLDS
SCL and SDA low-level input
VIL-PMBUS 0°C ≤ TJ ≤ 85°C 0.8 V
voltage (1)
SCL and SDA high-level input
VIH-PMBUS 0°C ≤ TJ ≤ 85°C 2.1 V
voltage (1)
SCL and SDA hysteresis
VHY-PMBUS 0°C ≤ TJ ≤ 85°C 240 mV
voltage (1)
PMBus SDA and ALERT OUTPUT PULLDOWN
VDDPMBus = 5.5 V,
SDA and ALERT low-level
VOL1-PMBUS RPULLUP = 1.1 kΩ, 0°C ≤ TJ ≤ 0.4 V
output voltage (1)
85°C
VDDPMBus = 3.6 V,
SDA and ALERT low-level
VOL2-PMBUS RPULLUP = 0.7 kΩ, 0°C ≤ TJ ≤ 0.4 V
output voltage (1)
85°C

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6.6 Timing Requirements

MIN NOM MAX UNIT
POWER-ON DELAY
Delay from enable to switching
356 μs
POD<2:0> = 000
Delay from enable to switching
612 μs
POD<2:0> = 001
Delay from enable to switching
1.124 ms
POD<2:0> = 010
Delay from enable to switching
2.148 ms
POD<2:0> = 011
tPODLY Power-on delay time
Delay from enable to switching
4.196 ms
POD<2:0> = 100
Delay from enable to switching
8.292 ms
POD<2:0> = 101
Delay from enable to switching
16.48 ms
POD<2:0> = 110
Delay from enable to switching
32.86 ms
POD<2:0> = 111
PGOOD DELAY
Delay for PGOOD going in
165 256 320 μs
PGD<2:0> = 000
Delay for PGOOD going in
409 512 614 μs
PGD<2:0> = 001
Delay for PGOOD going in
0.819 1.024 1.228 ms
PGD<2:0> = 010
Delay for PGOOD going in
1.638 2.048 2.458 ms
PGD<2:0> = 011
tPGDLY PGOOD delay time
Delay for PGOOD going in
3.276 4.096 4.915 ms
PGD<2:0> = 100
Delay for PGOOD going in
6.553 8.192 9.83 ms
PGD<2:0> = 101
Delay for PGOOD going in
13.104 16.38 19.656 ms
PGD<2:0> = 110
Delay for PGOOD going in
105 131 157 ms
PGD<2:0> = 111
Delay for PGOOD coming out 2 μs
SOFT START TIME
SST<1:0> = 00 1.0
SST<1:0> = 01 2.0
tSS Soft-start time ms
SST<1:0> = 10 4.0
SST<1:0> = 11 8.0
FREQUENCY CONTROL
tOFF(min) Minimum off-time DRVH falling to rising 320 ns
(1)
tON(min) Minimum on-time DRVH rising to falling 60 ns
PROTECTIONS
tUVPDLY UVP filterdelay time 1 ms
DRIVER
DRVH-off to DRVL-on 10
tDEAD Dead time ns
DRVL-off to DRVH-on 20

(1) Specified by design. Not production tested.

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6.7 Switching Characteristics

over operating free-air temperature range VIN = 12 V, VVO = 3.3 V(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY CONTROL
FS <2:0> = 000 275
FS <2:0> = 001 325
FS <2:0> = 010 425
FS <2:0> = 011 525
fSW VO pin switching frequency kHz
FS <2:0> = 100 625
FS <2:0> = 101 750
FS <2:0> = 110 850
FS <2:0> = 111 1000

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6.8 Typical Characteristics

1400 800

1200 700

Shutdown Current (µA)

600
Supply Current (µA)

1000
500
800
400
600
300
400
200
No Load No Load
200 VEN = 5 V 100 VEN = 0 V
VVDD = 12 V VVDD = 12 V
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C) G001 Temperature (°C) G002

Figure 1. VDD Supply Current vs Temperature Figure 2. VDD Shutdown Current vs Temperature
140 16

120 14
OVP/UVP Threshold (%)

12
100

TRIP Current (µA)

10
80
8
60
6
40
4
20 OVP 2
UVP VVDD = 12 V
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C) G003 Temperature (°C) G004

Figure 3. OVP/UVP Thresholds vs Temperature Figure 4. TRIP Pin Current vs Temperature

VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, DCM VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, FCCM

EN (5 V/div) EN (5 V/div)

VOUT (0.5 V/div) VOUT (0.5 V/div)

SW (10 V/div) SW (10 V/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (0.4 ms/div) Time (0.4 ms/div)

Figure 5. No-Load Start-Up Waveforms with DCM Figure 6. No-Load Start-Up Waveforms with FCCM

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Typical Characteristics (continued)

VIN = 12 V, V OUT = 1.2 V, I OUT = 20 A, 425 kHz VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, DCM

EN (5 V/div) EN (5 V/div)

VOUT (0.5 V/div)

VOUT (0.5 V/div) 0.5 V pre-biased

SW (10 V/div) SW (10 V/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (0.4 ms/div) Time (0.4 ms/div)

Figure 7. Full-Load Start-Up Waveforms Figure 8. Pre-Bias Start-Up Waveforms with DCM

VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, FCCM VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, DCM
EN (5 V/div)
EN (5 V/div)

VOUT (0.5 V/div)

0.5 V pre-biased VOUT (0.5 V/div)

SW (10 V/div) SW (10 V/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (0.4 ms/div) Time (4 ms/div)

Figure 9. Pre-Bias Start-Up Waveforms with FCCM Figure 10. No-Load Shutdown Waveforms with DCM

VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, FCCM VIN = 12 V, V OUT = 1.2 V, I OUT = 20 A, 425 kHz,
EN (5 V/div) EN (5 V/div)

VOUT (0.5 V/div) VOUT (0.5 V/div)

SW (10 V/div) SW (10 V/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (4 ms/div) Time (40 µs/div)

Figure 11. No-Load Shutdown Waveforms with FCCM Figure 12. Full-Load Shutdown Waveforms

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Typical Characteristics (continued)

VIN = 12 V, V OUT = 1.2 V VIN = 12 V, V OUT = 1.2 V

IOUT = 0 A IOUT = 20 A, 425 kHz
425 kHz, DCM

VIN (5 V/div) VIN (5 V/div)

VOUT (0.5 V/div) VOUT (0.5 V/div)

VREG (5 V/div) VREG (5 V/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (2 ms/div) Time (2 ms/div)

Figure 13. No-Load UVLO Start-Up Waveforms Figure 14. Full-Load UVLO Start-Up Waveforms

VIN = 12 V, V OUT = 1.2 V VIN = 12 V, V OUT = 1.2 V

IOUT = 0 A, 425 kHz, FCCM IOUT = 0 A, 425 kHz, DCM

VOUT (50 mV/div) VOUT (50 mV/div)

SW (10 V/div)

SW (10 V/div)

IL (5 A/div)
IL (5 A/div)

Time (2 µs/div) Time (1 µs/div)

Figure 15. 1.2-V Output Ripple with FCCM Figure 16. 1.2-V Output Ripple with DCM

VIN = 12 V, V OUT = 1.2 V, 425 kHz, DCM VIN = 12 V, V OUT = 1.2 V, 425 kHz , DCM

VOUT (50 mV/div)

VOUT (50 mV/div)

SW (10 V/div)

SW (10 V/div)

IL (5 A/div)

IL (5 A/div)

Time (0.1 ms/div) Time (0.1 ms/div)

Figure 17. CCM to DCM Transitions Figure 18. DCM to CCM Transitions

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Typical Characteristics (continued)

VIN = 12 V, V OUT = 1.2 V, 425 kHz, FCCM VIN = 12 V, V OUT = 1.2 V, 425 kHz, DCM
IOUT from 0 A to 10 A, 2.5 A/ µs IOUT from 0 A to 10 A, 2.5 A/ µs
VOUT (50 mV/div) VOUT (50 mV/div)

IOUT (5 A/div) IOUT (5 A/div)

Time (0.1 ms/div) Time (0.1 ms/div)

Figure 19. FCCM Load Transients Figure 20. DCM Load Transients

VIN = 12 V, V OUT = 1.2 V, 425 kHz VIN = 12 V, V OUT = 1.2 V, 425 kHz
VOUT (1 V/div) VOUT (1 V/div)
IOUT = 20 A then short output, Hiccup IOUT = 20 A then short output, Latch -off

SW (10 V/div) SW (10 V/div)

IL (10 A/div) IL (10 A/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (10 ms/div) Time (10 ms/div)

Figure 21. Output Short Circuit Protection with Hiccup Figure 22. Output Short Circuit Protection with Latch-off

VIN = 12 V, V OUT = 1.2 V, I OUT = 0 A, 425 kHz, DCM VIN = 12 V, V OUT = 1.2 V, I OUT = 20 A, 425 kHz
VOA from 0 % to +9 % SCL (5 V/div) VOA from 0 % to +9 % SCL (5 V/div)

VOUT (100 mV/div) VOUT (100 mV/div)

IL (5 A/div)

IL (5 A/div)

PGOOD (5 V/div) PGOOD (5 V/div)

Time (40 ms/div) Time (40 ms/div)

Figure 23. No-Load VOUT Adjustment Waveforms Figure 24. Full-Load VOUT Adjustment Waveforms

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Typical Characteristics (continued)

1000 1000
Frequency (kHz)

Frequency (kHz)
100 100

fSET = 425 kHz fSET = 625 kHz

VIN = 12 V VIN = 12 V
10 10
VOUT = 1.2 V VOUT = 1.2 V

FCCM FCCM
DCM DCM
1 1
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Output Current (A) G005 Output Current (A) G001

Figure 25. Switching Frequency vs. Output Current Figure 26. Switching Frequency vs. Output Current
1000 1000
Frequency (kHz)

Frequency (kHz)
100 100

fSET = 750 kHz fSET = 1 MHz

VIN = 12 V VIN = 12 V
10 10
VOUT = 1.2 V VOUT = 1.2 V

FCCM FCCM
DCM DCM
1 1
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Output Current (A) G001 Output Current (A) G001

Figure 27. Switching Frequency vs. Output Current Figure 28. Switching Frequency vs. Output Current
1.220 1.220
VOUT = 1.2 V VIN = 12 V
1.215 fSW = 425 kHz 1.215 VOUT = 1.2 V
fSW = 425 kHz
1.210 1.210
Output Voltage (V)

Output Voltage (V)

1.205 1.205

1.200 1.200

1.195 1.195

1.190 1.190
DCM, IOUT = 0 A
1.185 FCCM, IOUT = 0 A 1.185 FCCM
DCM, IOUT = 15 A DCM
1.180 1.180
5 6 7 8 9 10 11 12 13 14 0 2 4 6 8 10 12 14 16 18 20
Input Voltage (V) G000 Output Current (A) G000

Figure 29. Output Voltage vs. Input Voltage Figure 30. Output Voltage vs. Output Current

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Typical Characteristics (continued)

100 100
VIN = 12 V
90 90
VOUT = 1.2 V
80 80
70 70
Efficiency (%)

Efficiency (%)
60 60
50 50
40 40
30 30
fSW = 625 kHz, FCCM
20 DCM VOUT = 0.6 V 20 fSW = 425 kHz, FCCM
VIN = 12 V VOUT = 1.2 V fSW = 625 kHz, DCM
10 VOUT = 1.8 V 10
fSW = 425 kHz fSW = 425 kHz, DCM
0 0
0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10 100
Output Current (A) G000 Output Current (A) G001

Figure 31. Efficiency vs. Output Current Figure 32. Efficiency vs. Output Current

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7 Detailed Description

7.1 Overview
The TPS53819A is a high-efficiency, single-channel, synchronous buck regulator controller that uses the PMBus
protocol. It is suitable for low output voltage, point-of-load applications in computing and similar digital consumer
applications. The device features proprietary D-CAP2 mode control combined with adaptive on-time architecture.
This combination is ideal for building modern low duty-ratio and ultra-fast load step response DC-DC converters.
The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 3 V to 28 V. The D-
CAP2 mode uses emulated current information to control the loop modulation. One advantage of this control
scheme is that it does not require an external phase compensation network, which makes it easy to use. It also
allows for a low external component count. The switching frequency is selectable from eight preset values
through the PMBus interface. Adaptive on-time control tracks the preset switching frequency over a wide range
of input and output voltages while increasing the switching frequency as needed during load step transient.

7.2 Functional Block Diagram

VREF +8/16% + PGOOD

VREF – 32% + UV

Delay
+
+ OV
VREF –8/16%
VREF +20%
VBST
Control Logic

EN Enable/SS Control
PWM DRVH
+

FB
+
+ SW
VREF VOUT
VOUT XCON
TM
D-CAP2 Ramp Reference
VO
Generator Generator

Adjustment /
SCL
Margining
tON
PMBus One-
SDA
Interface Shot
ALERT
DCM / LDO
VDD
FCCM Regulator
ADDR Address Detector
VREG
10 ?A
x(-1/8) +
OCP DRVL
TRIP

GND
+
x(1/8) ZC

TPS53819 A
UDG-12119

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7.3 Feature Description

7.3.1 Enable and Soft-Start
When the EN pin voltage rises above the enable threshold voltage and/or ON_OFF bit is set via PMBus
according to the setting in OPERATION command, the controller enters a start-up sequence. After a
programmed power-on-delay duration from 0.35 ms to 32.86 ms, the internal DAC starts ramping up the
reference voltage from 0 V to a target voltage (typically 0.6 V) with the programmed soft-start time from 1 ms to 8
ms. The device maintains a smooth and constant output voltage ramp-up during start-up regardless of load
current.

7.3.2 Adaptive On-Time Control

The TPS53819A does not have a dedicated oscillator. The device operates with a pseudo-constant frequency by
feed-forwarding the input and output voltages into the on-time one-shot timer. The adaptive on-time control
adjusts the on-time to be inversely proportional to the input voltage and proportional to the output voltage (tON ∝
VOUT/VIN). This makes the switching frequency fairly constant in steady state conditions over a wide input voltage
range. The switching frequency is selectable from 275 kHz to 1 MHz via PMBus (FREQUENCY_CONFIG).

7.3.3 Zero Crossing Detection

The TPS53819A uses a low offset comparator to detect SW node zero crossing event in order to optimize turn-
off timing of low-side MOSFET.

7.3.4 Output Discharge Control

When the EN pin voltage falls below the enable threshold voltage and/or ON_OFF bit is reset via PMBus
according to the setting in OPERATION command, the TPS53819A discharges output capacitor using internal
MOSFET connected between the VOUT pin and the GND pin while the high-side and low-side MOSFETs are
maintained in the OFF state. The typical discharge resistance is 40 Ω.

7.3.5 Low-Side Driver

The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFETs. The drive capability is
represented by the internal resistance, which is 0.9 Ω for VREG to DRVL and 0.5 Ω for DRVL to GND. A dead-
time period to prevent shoot through is internally generated between high-side MOSFET OFF to low-side
MOSFET ON, and low-side MOSFET OFF to high-side MOSFET ON. The 5-V, VREG supply voltage delivers
the bias voltage. A bypass capacitor connected between the VREG and GND pins supplies the instantaneous
drive current. Equation 1 shows the average low-side gate drive current.
IGL = CGL ´ VVDRV ´ fSW (1)

7.3.6 High-Side Driver

The high-side driver drives high current, low RDS(on) , N-channel MOSFETs. When configured as a floating driver,
the VREG pin supply delivers the bias voltage. Equation 2 shows the average high-side gate current.
IGH = CGH ´ VVDRV ´ fSW (2)
The flying capacitor between the VBST and SW pins supplies the instantaneous drive current. The internal
resistance, which is 1.6 Ω for VBST to DRVH and 0.6 Ω for DRVH to SW represents the drive capability.
Equation 3 calculates the driver power dissipation required for the TPS53819A
PDRV = (IGL + IGH )´ VVDRV (3)

7.3.7 Power Good

The TPS53819A indicates the switcher output is within the target range when the power-good output is high. The
power-good function activates after the soft-start operation has finished. If the output voltage comes within ±8%
of the target value, internal comparators detect power-good state and the power-good signal becomes high after
a programmed delay time between 0.25 ms and 131 ms. If the output voltage goes outside of ±16% of the target
value, the power-good signal becomes low after a 2-μs internal delay. The power-good output is an open drain
output and must be pulled up externally.

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Feature Description (continued)

7.3.8 Current Sense and Overcurrent Protection
TPS53819A has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period when inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53819A supports
temperature compensated MOSFET on-resistance (RDS(on)) sensing. The TRIP pin should be connected to GND
through the trip voltage setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 μA typically at
room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 4. Note that the
VTRIP is limited up to approximately 3 V internally.
VTRIP (mV ) = RTRIP (kW )´ ITRIP (mA ) (4)
The inductor current is monitored by the voltage between GND pin and SW pin so that SW pin should be
properly connected to the drain terminal of the low-side MOSFET. The TRIP current has a 4700-ppm/°C
temperature slope to compensate the temperature dependency of the on-resistance. The device uses the GND
pin as the positive current sensing node. As the comparison occurs during the OFF state, VTRIP sets the valley
level of the inductor current. Thus, the average load current at the overcurrent threshold, IOCP, is calculated as
shown in Equation 5.

IOCP =
VTRIP
+
IIND(ripple)
=
VTRIP
+
1
´
(VIN - VOUT )´ VOUT
(8 ´ RDS(on) ) 2 (8 ´ RDS(on) ) 2 ´ L ´ fSW VIN
(5)
In an overcurrent condition, the load current exceeds the inductor current delivered to the output capacitor, thus
the output voltage tends to fall. Eventually, it crosses the undervoltage protection threshold and the device shuts
down. If hiccup mode is selected, then after a hiccup delay time (8.96 ms + 7× programmed soft-start time), the
controller restarts. If the overcurrent condition remains, the procedure is repeated and the device enters hiccup
mode. During the CCM, the negative current limit (NCL) protects the external FET from carrying too much
current. The OCLN detect threshold is set at the same absolute value as positive current limit (OCLP) but with
negative polarity. Note that the threshold still represents the valley value of the inductor current. When an OCLP
or OCLN event occurs, the corresponding fault signals (IOUT_OC and IOUT) of the STATUS_WORD register is
latched to indicate the faults and can be read via PMBus.

7.3.9 Overvoltage and Undervoltage Protection

TPS53819A monitors a resistor divided feedback voltage to detect overvoltage and undervoltage conditions.
When the feedback voltage becomes lower than 68% of the target voltage, the undervoltage protection (UVP)
comparator output goes high and an internal UVP delay time counter begins counting. After 1 ms, the device
turns OFF both high-side and low-side MOSFETs drivers. If the hiccup mode is selected, then the controller
restarts after a hiccup delay time (8.96 ms + 7 × programmed soft-start time). This function is enabled after the
soft-start operation is completed. When the feedback voltage becomes higher than 120% of the target voltage,
the overvoltage protection (OVP) comparator output goes high and the circuit latches OFF the high-side
MOSFET driver and latches ON the low-side MOSFET driver. If the sensed inductor current reaches the negative
current limit, then the low-side MOSFET driver is turned OFF, and high-side MOSFET driver is turned ON with
an appropriate on-time to limit the inductor current while the output voltage discharges.

7.3.10 Out-of-Bound Protection

TPS53819A has an out-of-bound (OOB) overvoltage protection that tries to protect the output load at a much
lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault,
so the device is not latched off after an OOB event. OOB protection is intended as an early no-fault overvoltage
protection mechanism, in addition to the official overvoltage protection as described in the Overvoltage and
Undervoltage Protection section.

7.3.11 UVLO Protection

The TPS53819A has VDD undervoltage lockout protection (UVLO). When the VDD voltage is lower than the
programmed UVLO threshold voltage, the switch mode power supply shuts OFF. This is a non-latch protection,
but if VDD UVLO occurs when the switcher is enabled by either EN pin or ON_OFF bit via PMBus, the
corresponding fault signals (VIN_UV and INPUT) of the STATUS_WORD register latch off to indicate the fault
condition, and can be read via PMBus.

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Feature Description (continued)

7.3.12 Thermal Shutdown
The TPS53819A has an over-temperature protection feature. If the temperature exceeds the threshold value
(typically 140°C), the device is shut OFF. This is a non-latch protection, but when the temperature exceeds the
threshold value, the corresponding fault signal (TEMP) of the STATUS_WORD register latches off to indicate the
fault condition, and can be read via PMBus.

7.4 Device Functional Modes

7.4.1 Light-Load Condition in Auto-Skip Operation (Eco-mode)
If the discontinuous conduction mode (DCM) is selected via PMBus (MODE_SOFT_START_CONFIG),
TPS53819A automatically reduces the switching frequency at light-load conditions to maintain high efficiency.
Specifically, as the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its ripple valley current touches zero level, which is the boundary between
continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The synchronous MOSFET is
turned OFF when this zero inductor current is detected. As the load current further decreases, the converter runs
into DCM.

NOTE
The zero current must be detected for at least 16 switching cycles to switch from CCM to
DCM.

The on-time remains almost the same as continuous conduction mode so that it takes longer time to discharge
the output capacitor with smaller load current to the reference voltage level. The transition point to the light-load
operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) is calculated in
Equation 6.

IOUT(LL ) =
1
´
(VIN - VOUT )´ VOUT
2 ´ L ´ fSW VIN

where
• fSW is the PWM switching frequency (6)
Switching frequency versus output current in the light-load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current when below the IOUT(LL) given in Equation 6. For example, it
is 65 kHz at IO(LL)/5 if the frequency setting is 325 kHz.

7.4.2 Forced Continuous Conduction Mode

When the forced continuous conduction mode (FCCM) is selected via PMBus (MODE_SOFT_START_CONFIG),
the controller maintains continuous conduction mode even in light-load condition. In FCCM mode, switching
frequency maintains a constant level over the entire load range which is suitable for applications that need tight
control of the switching frequency at a cost of lower efficiency. During the soft-start time, the controller maintains
discontinuous conduction mode, and then switches to continuous conduction mode if FCCM is selected after the
soft-start operation is completed.

7.4.3 D-CAP2™ Mode

From small-signal loop analysis, a buck converter using D-CAP2™ mode control architecture can be simplified
as shown in Figure 33.

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Device Functional Modes (continued)

VO C C1 RC1 SW

C C2 R C2
VIN

R FBH
G DRVH
FB
+
+ Lx
Control VOUT
Logic
R FBL
and
+ + Driver DRVL ESR R LOAD
0.6 V VOFS

TPS53819A COUT

UDG-12120

Figure 33. Simplified Modulator Using D-CAP2™ Control Architecture

The D-CAP2 control architecture in TPS53819A includes an internal ripple generation network enabling the use
of very low-ESR output capacitors such as multi-layer ceramic capacitors (MLCC). No external current sensing
networks or compensators are required with D-CAP2 control architecture in order to simplify the power supply
design. The role of the internal ripple generation network is to emulate the ripple component of the inductor
current information and then combine it with the voltage feedback signal. VOFS is the internal offset to
compensate the offset caused by the internal ripple, and the typical VOFS value is 4 mV. The 0-dB frequency of
the D-CAP2 architecture can be approximated as shown in Equation 7.
RC1 ´ CC1 ´ 0.6 ´ (0.67 + D )
f0 =
2p ´ G ´ L X ´ COUT ´ VOUT

where
• G is gain of the amplifier which amplifies the ripple current information generated by the network
• D is the duty ratio (7)
The typical G value is 0.25. The RC1CC1 time constant value varies according to the selected switching frequency
as shown in Table 1.

Table 1. Switching Frequency Selection

SWITCHING FREQUENCY (kHz) RC1CC1 TIME CONSTANT (µs)
275
75
325
425
62
525
625
48
750
850
36
1000

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In order to secure enough phase margin, consider that f0 should be lower than 1/3 of the switching frequency, but
is also higher than 5 times the fC2 as shown in Equation 8.
f
5 ´ fC2 £ f0 £ SW
3
where
• fC2 is determined by the internal network of RC2 and CC2 (1.4 kHz typ) (8)
This example describes a DC-DC converter with an input voltage range of 12-V and an output voltage of 1.2-V. If
the switching frequency is 525 kHz and the inductor is given as 0.44uH, then COUT should be larger than 197 μF,
and also be smaller than 4.9 mF based on the design requirements. The characteristics of the capacitors should
be also taken into considerations. For MLCC, use X5R or better dielectric and take into account derating of the
capacitance by both DC bias and AC bias. When derating by DC bias and AC bias are 80% and 50%,
respectively, the effective derating is 40% because 0.8 x 0.5 = 0.4. The capacitance of specialty polymer
capacitors may change depending on the operating frequency. Consult capacitor manufacturers for specific
characteristics.

7.5 Programming
7.5.1 PMBus General Descriptions
The TPS53819A has seven internal custom user-accessible 8-bit registers. The PMBus interface has been
designed for program flexibility, supporting a direct format for write operation. Read operations are supported for
both combined format and stop separated format. While there is no auto increment or decrement capability in the
TPS53819A PMBus logic, a tight software loop can be designed to randomly access the next register, regardless
of which register was accessed first. The START and STOP commands frame the data packet and the REPEAT
START condition is allowed when necessary.
The device can operate in either standard mode (100 kb/s) or fast mode (400 kb/s).

7.5.2 PMBus Slave Address Selection

The seven-bit slave address is 001A3A2A1A0x, where A3A2A1A0 is set by the ADDR pin on the device. Bit 0 is the
data direction bit, i.e., 001A3A2A1A00 is used for write operation and 001A3A2A1A01 is used for read operation.

7.5.3 PMBus Address Selection

The TPS53819A allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed
as 001. The address selection process is defined by the resistor divider ratio from VREG pin to ADDR pin, and
the address detection circuit starts to work only after VDD input supply has risen above its UVLO threshold. The
table below lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical
temperature coefficient of ±100ppm/°C are recommended. Higher performance resistors can be used if tighter
noise margin is required for more reliable address detection, as shown in Table 2.

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Table 2. PMBus Address Selection Settings

DIVIDER
RESISTOR RATIO HIGH-SIDE LOW-SIDE
PMBus
DIVIDER RANGE RESISTANCE RESISTANCE
ADDRESS
RATIO (kΩ) (kΩ)
LOW HIGH
0011111 > 0.557 — 1 300
0011110 0.509 0.4958 0.5247 160 165
0011101 0.461 0.4482 0.4772 180 154
0011100 0.416 0.4073 0.4294 200 143
0011011 0.375 0.3662 0.3886 200 120
0011010 0.334 0.3249 0.3476 220 110
0011001 0.297 0.2905 0.3067 249 105
0011000 0.263 0.2560 0.2725 249 88.7
0010111 0.229 0.2215 0.2385 240 71.5
0010110 0.195 0.1870 0.2044 249 60.4
0010101 0.160 0.1524 0.1703 249 47.5
0010100 0.126 0.1179 0.1363 249 36.0
0010011 0.096 0.0900 0.1024 255 27.0
0010010 0.068 0.0622 0.0752 255 18.7
0010001 0.041 0.0340 0.0480 270 11.5
0010000 < 0.013 — 300 1

7.5.4 Supported Formats

The supported formats are described in this section.

7.5.4.1 Direct Format: Write

The simplest format for a PMBus write is direct format. After the start condition [S], the slave chip address is
sent, followed by an eighth bit indicating a write. The TPS53819A then acknowledges that it is being addressed,
and the master responds with an 8-bit register address byte. The slave acknowledges and the master sends the
appropriate 8-bit data byte. Again the slave acknowledges and the master terminates the transfer with the stop
condition [P].

7.5.4.2 Combined Format: Read

After the start condition [S], the slave chip address is sent, followed by an eighth bit indicating a write. The
TPS53819A then acknowledges that it is being addressed, and the master responds with an 8-bit register
address byte. The slave acknowledges and the master sends the repeated start condition [Sr]. Again the slave
chip address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge
followed by previously addressed 8 bit data byte. The master then sends a non-acknowledge (NACK) and finally
terminates the transfer with the stop condition [P].

7.5.4.3 Stop-Separated Reads

Stop-separated read features are also available. This format allows a master to initialize the register address
pointer for a read and return to that slave at a later time to read the data. In this format the slave chip address
followed by a write bit are sent after a start [S] condition. The TPS53819A then acknowledges it is being
addressed, and the master responds with the 8-bit register address byte. The master then sends a stop or restart
condition and may then address another slave. After performing other tasks, the master can send a start or
restart condition to the device with a read command. The device acknowledges this request and returns the data
from the register location that had been set up previously.

7.5.5 Supported PMBus Commands

The TPS53819A supports the PMBus commands shown in Table 1 only. Not all features of each PMBus
command are supported. The CLEAR_FAULTS, STORE_DEFAULT_ALL and RESTORE_DEFAULT_ALL
commands have no data bytes. The non-volatile memory (NVM) cells inside the TPS53819A can permanently
store some registers.
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Table 3. Supported PMBus Commands

COMMAND NOTES
OPERATION Turn on or turn off switching converter only
ON_OFF_CONFIG ON/OFF configuration
CLEAR_FAULTS Clear all latched status flags
WRITE_PROTECT Control writing to the PMBus device
STORE_DEFAULT_ALL Store contents of user-accessible registers to non-volatile memory cells
RESTORE_DEFAULT_ALL Copy contents of non-volatile memory cells to user-accessible registers
STATUS_WORD PMBus read-only status and flag bits
CUSTOM_REG MFR_SPECIFIC_00 (Custom Register 0): Custom register
DELAY_CONTROL MFR_SPECIFIC_01 (Custom Register 1): Power on and power good delay times
MODE_SOFT_START_CONFIG MFR_SPECIFIC_02 (Custom Register 2): Mode and soft-start time
FREQUENCY_CONFIG MFR_SPECIFIC_03 (Custom Register 3): Switching frequency control
VOUT_ADJUSTMENT MFR_SPECIFIC_04 (Custom Register 4): Output voltage adjustment control
VOUT_MARGIN MFR_SPECIFIC_05 (Custom Register 5): Output voltage margin levels
UVLO_THRESHOLD MFR_SPECIFIC_06 (Custom Register 6): Turn-on input voltage UVLO threshold

7.5.6 Unsupported PMBus Commands

Do not send any unsupported commands to the TPS53819A. Even though the device receives an unsupported
commands, it can acknowledge the unsupported commands and any related data bytes by properly sending the
ACK bits. However, the device ignores the unsupported commands and any related data bytes, which means
they do not affect the device operation in any way. Although the TPS53819A may acknowledge but ignore
unsupported commands and data bytes, it can however, set the CML bit in the STATUS_BYTE register and then
pull down the ALERT pin to notify the host. For this reason, unsupported commands and data bytes should not
be sent to TPS53819A.

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7.6 Register Maps

7.6.1 OPERATION [01h] (R/W Byte)
The TPS53819A supports only the functions of the OPERATION command shown in Table 4.

Table 4. OPERATION Command Supported Functions

COMMAND DEFINITION DESCRIPTION NVM
0: turn off switching converter
OPERATION<7> ON_OFF —
1: turn on switching converter
OPERATION<6> — not supported and don’t care —
00xx: turn off output voltage margin function
0101: turn on output voltage margin low and ignore fault
OPERATION<5:2> OPMARGIN<3:0> 0110: turn on output voltage margin low and act on fault —
1001: turn on output voltage margin high and ignore fault
1010: turn on output voltage margin high and act on fault
OPERATION<1> — not supported and don’t care —
OPERATION<0> — not supported and don’t care —

7.6.2 ON_OFF_CONFIG [02h] (R/W Byte)

The TPS53819A supports only the functions of the ON_OFF_CONFIG command shown in Table 5.

Table 5. ON_OFF_CONFIG Command Supported Functions

COMMAND DEFINITION DESCRIPTION NVM
ON_OFF_CONFIG<7> — not supported and don’t care —
ON_OFF_CONFIG<6> — not supported and don’t care —
ON_OFF_CONFIG<5> — not supported and don’t care —
ON_OFF_CONFIG<4> PU not supported and always set to 1 —
0: ignore ON_OFF bit (OPERATION<7>) (1)
ON_OFF_CONFIG<3> CMD Yes
1: act on ON_OFF bit (OPERATION<7>)
0: ignore EN pin
ON_OFF_CONFIG<2> CP Yes
1: act on EN pin (1)
ON_OFF_CONFIG<1> PL not supported and always set to 1 —
ON_OFF_CONFIG<0> SP not supported and always set to 1 —

(1) TI default.

Conditions required to enable the switcher:

• If CMD is cleared and CP is set, then the switcher can be enabled only by the EN pin.
• If CMD is set and CP is cleared, then the switcher can be enabled only by the ON_OFF bit (OPERATION<7>)
via PMBus.
• If both CMD and CP are set, then the switcher can be enabled only when both the ON_OFF bit
(OPERATION<7>) and the EN pin are commanding to enable the device.
• If both CMD and CP are cleared, then the switcher is automatically enabled after the ADDR detection
sequence completes, regardless of EN pin and ON_OFF bit polarities.

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7.6.3 WRITE_PROTECT [10h] (R/W Byte)

The WRITE PROTECT command is used to control writing to the PMBus device. The intent of this command is
to provide protection against accidental changes. This command has one data byte as described in Table 6.

Table 6. WRITE_PROTECT Command Supported Functions

COMMAND DEFINITION DESCRIPTION NVM
Disable all writes, except the
10000000: —
WRITE_PROTECT command.
Disable all writes, except the
01000000: WRITE_PROTECT and OPERATION —
commands.
WRITE_PROTECT<7:0> WP<7:0>
Disable all writes, except the
00100000: WRITE_PROTECT, OPERATION, and —
ON_OFF_CONFIG commands.
00000000: Enable writes to all commands. —
Others: Fault data —

7.6.4 CLEAR_FAULTS [03h] (Send Byte)

The CLEAR_FAULTS command is used to clear any fault bits in the STATUS_WORD and STATUS_BYTE
registers that have been set. This command clears all bits in all status registers. Simultaneously, the TPS53819A
releases its ALERT signal output if the device is asserting the ALERT signal. If the fault condition is still present
when the bit is cleared, the fault bits shall immediately be set again, and the ALERT signal should also be re-
asserted.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have
been shut down for a fault condition can be restarted with one of the following conditions.
• The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to
turn off and then to turn back on.
• VDD power is cycled for TPS53819A
The CLEAR_FAULT command is used to clear the fault bits in the STATUS_WORD and STATUS_BYTE
commands, and to release the ALERT pin. It is recommended not to send CLEAR_FAULT command when there
is no fault to cause the ALERT pin to pull down.

7.6.5 STORE_DEFAULT_ALL [11h] (Send Byte)

The STORE_DEFAULT_ALL command instructs TPS53819A to copy the entire contents of the operating
memory to the corresponding locations in the NVM. The updated contents in the non-volitile memory (NVM)s
become the new default values. The STORE_DEFAULT_ALL command can be used while the device is
operating. However, the device may be unresponsive during the copy operation with unpredictable results. (see
PMBus Power System Management Protocol Specificaiton, Part II - Command Language, Revision, 1.2, 6 Sept.
2010. www.powerSIG.org). It is recommended not to exceed 1000 write/erase cycles for non-volatile memory
(NVM).

7.6.6 RESTORE_DEFAULT_ALL [12h] (Send Byte)

The RESTORE_DEFAULT_ALL command instructs TPS53819A to copy the entire contents of the NVMs to the
corresponding locations in the operating memory. The values in the operating memory are overwritten by the
value retrieved from the NVM. It is permitted to use the RESTORE_DEFAULT_ALL command while the device is
operating. However, the device may be unresponsive during the copy operation with unpredictable results.

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7.6.7 STATUS_WORD [79h] (Read Word)

The TPS53819A does not support all functions of the STATUS_WORD command. A list of supported functions
appears in Table 7. A status bit reflects the current state of the converter. Status bit becomes high when the
specified condition has occurred and goes low when the specified condition has disappeared. A flag bit is a
latched bit that becomes high when the specified condition has occurred and does not go back low when the
specified condition has disappeared. STATUS_BYTE command is a subset of the STATUS_WORD command,
or more specifically the lower byte of the STATUS_WORD.

Table 7. STATUS_WORD Command Supported Functions

COMMAND DEFINITION DESCRIPTION
LOW BYTE: STATUS_BYTE [78h]
Low STATUS_WORD<7> BUSY not supported and always set to 0
0: raw status indicating device is providing power to output voltage
Low STATUS_WORD<6> OFF
1: raw status indicating device is not providing power to output voltage
0: latched flag indicating no output voltage overvoltage fault has occurred
Low STATUS_WORD<5> VOUT_OV
1: latched flag indicating an output voltage overvoltage fault has occurred
0: latched flag indicating no output current overcurrent fault has occurred
Low STATUS_WORD<4> IOUT_OC
1: latched flag indicating an output current overcurrent fault has occurred
0: latched flag indicating input voltage is above the UVLO turn-on threshold
Low STATUS_WORD<3> VIN_UV
1: latched flag indicating input voltage is below the UVLO turn-on threshold
0: latched flag indicating no OT fault has occurred
Low STATUS_WORD<2> TEMP
1: latched flag indicating an OT fault has occurred
0: latched flag indicating no communication, memory or logic fault has occurred
Low STATUS_WORD<1> CML
1: latched flag indicating a communication, memory or logic fault has occurred
Low STATUS_WORD<0> OTHER not supported and always set to 0
HIGH BYTE
0: latched flag indicating no output voltage fault or warning has occurred
High STATUS_WORD<7> VOUT
1: latched flag indicating a output voltage fault or warning has occurred
0: latched flag indicating no output current fault or warning has occurred
High STATUS_WORD<6> IOUT
1: latched flag indicating an output current fault or warning has occurred
0: latched flag indicating no input voltage fault or warning has occurred
High STATUS_WORD<5> INPUT
1: latched flag indicating a input voltage fault or warning has occurred
High STATUS_WORD<4> MFR not supported and always set to 0
0: raw status indicating PGOOD pin is at logic high
High STATUS_WORD<3> PGOOD
1: raw status indicating PGOOD pin is at logic low
High STATUS_WORD<2> FANS not supported and always set to 0
High STATUS_WORD<1> OTHER not supported and always set to 0
High STATUS_WORD<0> UNKNOWN not supported and always set to 0

The latched flags of faults can be removed or corrected only until one of the following conditions occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to
turn off and then to turn back on
• VDD power is cycled for TPS53819A
If the fault condition remains present when the bit is cleared, the fault bits are immediately set again, and the
ALERT signal is re-asserted.
TPS53819A supports the ALERT pin to notify the host of fault conditions. Therefore, the best practice for
monitoring the fault conditions from the host is to treat the ALERT pin as an interrupt source for triggering the
corresponding interrupt service routine. It is recommended not to keep polling the STATUS_WORD or
STATUS_BYTE registers from the host to reduce the firmware overhead of the host.

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7.6.8 CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)

Custom register 0 provides the flexibility for users to store any desired non-volatile information. For example,
users can program this register to track versions of implementation or other soft identification information. The
details of each setting are listed in Table 8.

Table 8. CUSTOM_REG (MFR_SPECIFIC_00) Settings

COMMAND DEFINITION DESCRIPTION NVM
CUSTOM_REG<7> — not supported and don’t care —
CUSTOM_REG<6> — not supported and don’t care —
00000: (1) can be used to store any desired non-volatile
CUSTOM_REG<5:0> CUSTOMWORD <5:0> Yes
information.

(1) TI default

7.6.9 DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)

Custom register 1 provides software control over key timing parameters of the controller: Power-on delay (POD)
time and power-good delay (PGD) time. The details of each setting are listed in Table 9.

Table 9. DELAY_CONTROL (MFR_SPECIFIC_01) Settings

COMMAND DEFINITION DESCRIPTION NVM
DELAY_CONTROL<7> — not supported and don’t care —
DELAY_CONTROL<6> — not supported and don’t care —
000: 256 µs
001: 512 µs
010: 1.024 ms (1)
011: 2.048 ms
DELAY_CONTROL<5:3> PGD<2:0> Yes
100: 4.096 ms
101: 8.192 ms
110: 16.384 ms
111: 131.072 ms
000: 356 µs
001: 612 µs
010: 1.124 ms (1)
011: 2.148 ms
DELAY_CONTROL<2:0> POD<2:0> Yes
100: 4.196 ms
101: 8.292 ms
110: 16.484 ms
111: 32.868 ms

(1) TI default

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7.6.10 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)

Custom register 2 provides software control over mode selection and soft-start time (tSS). The details of each
setting are listed in Table 10.

Table 10. MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) Settings

COMMAND DEFINITION DESCRIPTION NVM
MODE_SOFT_START_CONFIG<7> — not supported and don’t care —
MODE_SOFT_START_CONFIG<6> — not supported and don’t care —
MODE_SOFT_START_CONFIG<5> — not supported and don’t care —
MODE_SOFT_START_CONFIG<4> — not supported and don’t care —
00: 1 ms (1)
01: 2 ms
MODE_SOFT_START_CONFIG<3:2> SST<1:0> Yes
10: 4 ms
11: 8 ms
0: hiccup after UV (1)
MODE_SOFT_START_CONFIG<1> HICLOFF Hiccup interval is (8.96 ms + soft-start time × 7) Yes
1: latch-off after UV
0: DCM (1)
MODE_SOFT_START_CONFIG<0> CM Yes
1: FCCM

(1) TI Default

Figure 34 shows the soft-start timing diagram of TPS53819A with the programmable power-on delay time (tPOD),
soft-start time (tSST), and PGOOD delay time (tPGD). During the soft-start time, the controller remains in
discontinuous conduction mode (DCM), and then switches to forced continuous conduction mode (FCCM) at the
end of soft-start if CM bit (MODE_SOFT_START_CONFIG<0>) is set.

EN Pin and/or
ON_OFF bit tPOD tSST tPGD

VOUT

PGOOD DCM or FCCM

DCM (based on CM bit)
Time UDG-12070

Figure 34. Programmable Soft-Start Timing

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7.6.11 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)

Custom register 3 provides software control over frequency setting (FS). The details of FS setting are listed in
Table 11.

Table 11. FREQUENCY_CONFIG (MFR_SPECIFIC_03) Settings

COMMAND DEFINITION DESCRIPTION NVM
FREQUENCY_CONFIG<7> — not supported and don’t care —
FREQUENCY_CONFIG<6> — not supported and don’t care —
FREQUENCY_CONFIG<5> — not supported and don’t care —
FREQUENCY_CONFIG<4> — not supported and don’t care —
FREQUENCY_CONFIG<3> — not supported and don’t care —
000: 275 kHz
001: 325 kHz
(1)
010: 425 kHz
011: 525 kHz
FREQUENCY_CONFIG<2:0> FS<2:0> Yes
100: 625 kHz
101: 750 kHz
110: 850 kHz
111: 1 MHz

(1) TI default.

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7.6.12 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)

Custom register 4 provides ouput voltage adjustment (VOA) in ±0.75% steps, with a total range of ±9%. When
fine adjustment is used together with the margin setting, the change in the output voltage is determined by the
multiplication of the two settings.

Table 12. VOUT_ADJUSTMENT (MFR_SPECIFIC_04) Settings

COMMAND DEFINITION DESCRIPTION NVM
VOUT_ADJUSTMENT<7> — not supported and don’t care —
VOUT_ADJUSTMENT<6> — not supported and don’t care —
VOUT_ADJUSTMENT<5> — not supported and don’t care —
111xx: +9.00%
11011: +8.25%
11010: +7.50%
11001: +6.75%
11000: +6.00%
10111: +5.25%
10110: +4.50%
10101: +3.75%
10100: +3.00%
10011: +2.25%
10010: +1.50%
10001: +0.75%
10000: +0% (1)
VOUT_ADJUSTMENT<4:0> VOA<4:0> Yes
01111: –0%
01110: –0.75%
01101: –1.50%
01100: –2.25%
01011: –3.00%
01010: –3.75%
01001: –4.50%
01000: –5.25%
00111: –6.00%
00110: –6.75%
00101: –7.50%
00100: –8.25%
000xx: –9.00%

(1) TI default.

7.6.13 Output Voltage Fine Adjustment Soft Slew Rate

To prevent sudden buildup of voltage across inductor, output voltage fine adjustment setting cannot change
output voltage instantaneously. The internal reference voltage must slew slowly to its final target, and SST<1:0>
is used to provide further programmability. The details of output voltage fine adjustment slew rate are shown in
Table 13.

Table 13. Output Voltage Fine Adjustment Soft Slew Rate Settings
COMMAND DEFINITION DESCRIPTION NVM
00: 1 step per 4 µs (1)
MODE_SOFT_START_CONF 01: 1 step per 8 µs
SST<1:0> Yes
IG<3:2> 10: 1 step per 16 µs
11: 1 step per 32 µs

(1) TI default.

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7.6.14 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)

Custom register 5 provides output voltage margin high (VOMH) and output voltage margin low (VOML) settings.
This register works in conjunction with PMBus OPERATION command to raise or lower the output voltage by a
specified amount. This register settings described in Table 14 are also used together with the fine adjustment
setting described in Table 12. For example, setting fine adjustment to +9% and margin to +12% changes the
output by +22.08%, whereas setting fine adjustment to –9% and margin to –9% change the output by –17.19%

Table 14. VOUT_MARGIN (MFR_SPECIFIC_05) Settings

COMMAND DEFINITION DESCRIPTION NVM
11xx: +12.0%
1011: +10.9%
1010: +9.9%
1001: +8.8%
1000: +7.7%
0111: +6.7%
VOUT_MARGIN<7:4> VOMH<3:0> 0110: +5.7% Yes
0101: +4.7% (1)
0100: +3.7%
0011: +2.8%
0010: +1.8%
0001: +0.9%
0000: +0%
0000: –0%
0001: –1.1%
0010: –2.1%
0011: –3.2%
0100: –4.2%
0101: –5.2% (1)
VOUT_MARGIN<3:0> VOML<3:0> 0110: –6.2% Yes
0111: –7.1%
1000: –8.1%
1001: –9.0%
1010: –9.9%
1011: –10.7%
11xx: –11.6%

(1) TI default.

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7.6.15 Output Voltage Margin Adjustment Soft-Slew Rate

Similar to the output voltage fine adjustment, margin adjustment also cannot change output voltage
instantaneously. The soft-slew rate of margin adjustment is also programmed by SST<1:0>. The details are listed
in Table 15.

Table 15. Output Voltage Margin Adjustment Soft-Slew Rate Settings

COMMAND DEFINITION DESCRIPTION NVM
00: 1 step per 4 µs (1)
01: 1 step per 8 µs
MODE_SOFT_START_CONFIG<3:2> SST<1:0> Yes
10: 1 step per 16 µs
11: 1 step per 32 µs

(1) TI default.

Figure 35 shows the timing diagram of the output voltage adjustment via PMBus. After receiving the write
command of VOUT_ADJUSTMENT (MFR_SPECIFIC_04), the output voltage starts to be adjusted after tP delay
time (about 50 μs). The time duration tDAC for each DAC step change can be controlled by SST bits
(MODE_SOFT_START_CONFIG<3:2:> from 4 μs to 32 μs.
PMBus
Write Write
VOA<4:0>=10101b VOA<4:0>=01010b

tP tP

VOUT
tDAC

UDG-12071

Figure 35. Output Voltage Adjustment via PMBus

The margining function is enabled by setting the OPERATION command, and the margining level is determined
by the VOUT_MARGIN (MFR_SPECIFIC_05) command. Figure 36 and Figure 37 illustrate the timing diagrams
of the output voltage margining via PMBus. Figure 36 shows setting the margining level first, and then enabling
margining by writing OPERATION command. After the OPERATION margin high command enables the margin
high setting (VOMH<3:0>), the output voltage starts to be adjusted after tP delay time (about 50 μs). The time
duration tDAC for each DAC step change can be controlled by SST bits (MODE_SOFT_START_CONFIG<3:2>)
from 4 μs to 32 μs.
PMBus
Write Write
VOMH<3:0>=0100b OPMARGIN<3:0>=1010b

tP

VOUT
tDAC

UDG-12072

Figure 36. Setting the Margining Level First

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Write Write
OPMARGIN<3:0>=1010b VOMH<3:0>=0001b

tP
tP

VOUT
tDAC

UDG-12073

Figure 37. Enabling Margining First

As shown in Figure 37, the margining function is enabled first by a write command of OPERATION. The output
voltage starts to be adjusted toward the default margin high level after tP delay. Since the margining function has
been enabled, the output voltage can be adjusted again by sending a different margin high level with a write
command of VOUT_MARGIN. The time duration tDAC for each DAC step change can be also controlled by SST
bits (MODE_SOFT_START_CONFIG<3:2>) from 4 μs to 32 μs.

7.6.16 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]

Custom register 6 provides some limited programmability of input supply UVLO threshold, as described in
Table 16. The default turn-on UVLO threshold is 4.25 V.

Table 16. UVLO_THRESHOLD (MFR_SPECIFIC_06) Settings

COMMAND DEFINITION DESCRIPTION NVM
UVLO_THRESHOLD<7> — not supported and don’t care —
UVLO_THRESHOLD<6> — not supported and don’t care —
UVLO_THRESHOLD<5> — not supported and don’t care —
UVLO_THRESHOLD<4> — not supported and don’t care —
UVLO_THRESHOLD<3> — not supported and don’t care —
0xx: 10.2 V
100: not supported and should not be used
UVLO_THRESHOLD<2:0> VDDINUVLO<2:0> 101: 4.25 V (1) Yes
110: 6.0 V
111: 8.1 V

(1) TI default.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS53819A device is a small-sized, single buck controller with adaptive on-time D-CAP2 mode control and
PMBus.

8.2 Typical Application

The following application shows a TPS53819A 12-V to 1.2-V point-of-load synchronous buck regulator.

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TPS53819A

Figure 38. Typical Application Schematic, TPS53819A

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8.2.1 Design Requirements

Table 17. Design Example Specifications

PARAMETER MIN TYP MAX UNIT
VVIN Input voltage range 8 12 14 V
VVIN(ripple) Input voltage ripple 240 mVPP
VOUT Output voltage 1.2 V
VRIPPLE Output voltage ripple 12 mVPP
IOUT Output load current 0 20 A
IOCL Output overcurrent 25 A
fSW Switching frequency 425 kHz

8.2.2 Detailed Design Procedure

Selecting external components is a simple process using D-CAP2™ Mode

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS53819A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Switching Frequency

The switching frequency must first be decided on and is set using the PMBus. When deciding on a frequency a
tradeoff between component size and efficiency must be made. A lower frequency reduces the switching losses
in the MOSFETs improving efficiency but a larger inductance and/or output capacitance is required for low output
voltage ripple. This example uses the TI default PMBus setting, 425 kHz.

8.2.2.3 Inductor (L1)

Determined the inducatance to yield a ripple current (IIND(ripple)) of approximately ¼ to ½ of maximum output
current. Larger ripple current increases output ripple voltage, improves the signal-to-noise ratio and helps stable
operation. Maximum current ripple occurs with the maximum input voltage. Equation 9 calculates the
recommended inductance. After choosing the inductance, use Equation 10 to calculate the ripple.

L=
1
´
(V IN(max ) - VOUT )´ VOUT
=
3
´
(V
IN(max ) - VOUT )´ V OUT

IIND(ripple ) ´ fSW VIN(max ) IOUT(max ) ´ fSW VIN(max)

(9)

IIND(ripple) =
1
´
(
VIN(max) - VOUT ´ VOUT )
L ´ fSW VIN(max)
(10)
The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough margin above the
peak inductor current before saturation. The peak inductor current can be estimated in Equation 11.
IIND(peak ) = IOCL + IIND(ripple )
(11)

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Using Equation 9 the recommended inductance for the example is 0.329 μH. An inductor supplied by Pulse
Electronics (PA0513.441NLT) is selected with an inductance of 0.440 μH at 0 A and 0.363 μH at its 30 A rated
current. The saturation current is 35 A and the DCR is 0.32 mΩ. Using Equation 10 with the selected inductance
and maximum input voltage, the current ripple is estimated to be 6.23 A. Equation 11 calculates the peak current
to be 31.3 A, well below the saturation current of the inductor. The output current threshold when the supply
operates in DCM or CCM can also be estimated as half the estimated current ripple. With the maximum 14 V
input in this design the output current threshold is 3.12 A. With lower input voltages, ripple decreases and so
does the threshold.

8.2.2.4 Output Capacitors (C10, C11, C12, C13, C14)

Determine the output capacitance to meet the load transient, ripple requirements, and to meet small-signal
stability as shown in Equation 12.
RC1 ´ CC1 ´ 0.6 ´ (0.67 + D )
f
5 ´ fC2 £ £ SW
2p ´ G ´ L ´ COUT ´ VOUT 3

where
• G =0.25
• RC1 × CC1 time constant can be referred to Table 1
• D is the duty cycle (12)
Based on Equation 12, the value of COUT to ensure small signal stability can be calculated using Equation 13 and
Equation 14. These equations assume MLCC are used and the ESR effects are negligible. If a high ESR output
capacitor is used, the effects may reduce the minimum and maximum capacitance. In the design example using
Table 1 for 425-kHz switching frequency, the time constant is 62 μs. The recommended minimum capacitance
for a design with an 8-V minimum input voltage is 260 μF. The recommended maximum capacitance for design
with a 14-V maximum input voltage is 4842 μF.
æ V ö
RC1 ´ CC1 ´ 0.6 ´ ç 0.67 + OUT ÷
ç VIN(max) ÷
COUT £ è ø
2p ´ G ´ L ´ 5 ´ fC2 ´ VOUT (13)
æ V ö
RC1 ´ CC1 ´ 0.6 ´ ç 0.67 + OUT ÷
ç VIN(min) ÷
COUT ³ è ø
f
2p ´ G ´ L ´ SW ´ VOUT
3 (14)
Select a larger output capacitance to decrease the output voltage change that occurs during a load transient and
the output voltage ripple.
The minimum output capacitance to meet an output voltage ripple requirement can be calculated with
Equation 15. In the example the minimum output capacitance for 12 mVPP ripple is 162 μF. If non ceramic
capacitors are used Equation 16 calculates the maximum equivalent series resistance (ESR) of the output
capacitor to meet the ripple requirement. Equation 17 calculates the required RMS current rating for the output
capacitor. In this example with 12-V nominal input voltage it is 1.77 A. Finally the output capacitor must be rated
for the output voltage.
IIND(ripple)
COUT ³
8 ´ VRIPPLE ´ fSW (15)
æ IIND(ripple) ö
VRIPPLE - çç ÷÷
ESR £ è 8 ´ COUT ´ fSW ø
IIND(ripple)
(16)
IIND(ripple)
ICOUT(RMS) =
12 (17)

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This example uses five 1210, 100-μF, 6.3-V, X5R ceramic capacitors with 2 mΩ of ESR. From the data sheet the
estimated DC derating of 95% and AC derating of 70% for a total of 66.5% at room temperature. The total output
capacitance is approximately 332.5 μF.

8.2.2.5 Input Capacitors (C1, C2, C3, C4, C5)

Choose an input capacitance that reduces the input voltage ripple. Equation 18 calculates the minimum input
capacitance. In the example design to limit the input ripple to 240 mV, assuming all ceramic and ignoring ESR
ripple, the minimum input capacitance is 27.8 μF. The input capacitor must also be rated for the input RMS
current calculated in Equation 19. For this design example this current is 8.95 A with the minimum 8-V input
voltage. Also, the input capacitors must be rated for the maximum input voltage.
DIL
CIN ³
8 ´ VINRIPPLE ´ fSW (18)

ICIN(RMS) = I OUT ´
VOUT
´
(
VIN(min) - VOUT )
VIN(min) VIN(min)
(19)
This example uses four 1206, 22 μF, 16 V, X5R ceramic capacitors with 3 mΩ of ESR. An additional 0.1-μF
capacitor is placed close to the drain of the high-side MOSFET and the source of the low-side MOSFET.

8.2.2.6 MOSFET (Q1, Q2)

The TPS53819A uses two external N-channel MOSFETs. The VDS rating should be greater than the maximum
input voltage and include some tolerance for ringing on the switching node. It must also be rated for the DC
current. The high-side MOSFET conducts the input current and the low-side MOSFET conducts the output
current. The gate drive voltage is set by the VREG voltage of 5 V typical. The gate capacitance should be
reduced to minimize the current required to turn on the MOSFETs and switching losses. However it is
recommended the low-side MOSFET have a higher gate capacitance to avoid unintentional shoot-through
caused by the high dv/dt on the switching node during the high-side turn-on. A reduction in current also reduces
power dissipation in TPS53819A. Choose a low RDS(on) to reduce conduction losses especially for the low-side
MOSFET because it conducts the output current.
This design uses the CSD87350Q5D, 30-V, 40-A, NexFET power block with integrated low-side and high-side
MOSFETs. This is optimized for applications with a 5 V gate drive. The typical gate to source capacitance of the
high-side and low-side MOSFETs is 1341 pF and 2900 pF respectively. Using Equation 1 and Equation 2 the
average drive currents are 2.7 mA and 5.9 mA. With Equation 3 the power dissipated in the driver is estimated to
42.4 mW. The RDS(on) of the high-side and low-side MOSFETs with a 5 V gate drive voltage is 5 mΩ and 2.2 mΩ
respectively.
A small, 4.7-Ω resistance from R6, is added in series between DRVH and the gate of the high-side MOSFET.
This slows down the turn-on time of the high-side MOSFET dv/dt and reduces rising edge ringing on the
switching node to help prevent shoot-through. This value should be kept small and if it is too large it may lead to
too large of a delay time in the turn-on time of the high-side switch.

8.2.2.7 VREG Bypass Capacitor (C18)

A ceramic capacitor with a recommended value between 0.47-μF and 2.2-μF is required on the VREG pin for
proper operation. The example uses a 1-μF capacitor. Choose one rated for the VREG 5.5-V maximum voltage
in order to supply the instantaneous drive current of the low-side MOSFET.

8.2.2.8 VDD Bypass Capacitor (C19)

A 1-μF capacitor should be placed at the VDD pin rated for the maximum input voltage. If power stage switching
noise is causing faults, a small resistor (R12) can be added between VDD and all the input capacitors (C1-C5).
This creates an R-C filter and reduces any switching noise in the device input.

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8.2.2.9 VBST Capacitor (C7)

The bootstrap capacitor is required to generate the high-side gate drive bias voltage and provide the
instantaneous drive current for DRVH. A 0.1-μF ceramic capacitor is recommended to limit the ripple voltage.
R5 (0-Ω) resistance, is added in series with the bootstrap capacitor. This resistor can be used to slow down the
turn-on time of the high-side MOSFET dv/dt and reduces rising edge ringing on the SW node to help prevent
shoot-through. Keep the value small because a higher value may increase the the turn-on delay time of the high-
side switch.

8.2.2.10 Snubber (C8 and R9)

Fast-switching edges and parasitic inductance and capacitance cause voltage ringing on the SW node . If the
ringing results in excessive voltage on the SW node or erratic operation an R-C snubber can be used to reduce
ringing on the SW node and ensure proper operation in all operating conditions.

8.2.2.11 Feedback Resistance, RFBH and RFBL (R17 and R18)

The values of the voltage-divider resistors, RFBH and RFBL determine the output voltage as shown in Figure 38.
RFBH is connected between the FB pin and the output, and RFBL is connected between the FB pin and GND. The
recommended RFBH value is between 10 kΩ and 20 kΩ. Determine RFBL using Equation 20.
RFBH
RFBL =
é 1 æ æ 1 öö ù
ê VOUT - ´ ç IIND(ripple) ´ ç ESR + ÷ ÷÷ ú
ê 2 è ç 8 ´ COUT ´ fSW ø ø ú
è
ê ú -1
ê 0.6 - çæ 1 ´ æ I L ö ö ú
ê ç ç IND(ripple) ´ ÷ - VOFS ÷÷ ú
è2 è 4 ´ RC1 ´ CC1 ø ø û
ë
where
• VOFS is the internal offset voltage (4 mV)
• ESR is the from the output capacitors (20)
In this example R17 has a value of 10-kΩ. R18 is calculated to be 9.91 kΩ. The nearest standard value of 10 kΩ
is used for R18.

8.2.2.12 Overcurrent Limit (OCL) Setting Resistance (R10)

Combining Equation 7 and Equation 8, Equation 21 calculates RTRIP.
æ æ (V - VOUT ) ö VOUT ö
8 ´ ç IOCL - ç IN ÷ ´ ÷ ´ RDS(on)
ç ç (2 ´ L X ) ÷ (fSW ´ VIN ) ÷
è è ø ø
RTRIP =
ITRIP (21)
In this example for a 25-A current limit, RTRIP is calculated as 38.5 kΩ and is rounded up to the nearest standard
value of 39.2 kΩ.

8.2.2.13 PMBus Device Address (R3 and R4)

The PMBus address is selected using a resistive divider as shown in Table 2. In this example the address is set
to 0010000 with a 300-kΩ resistor (R3) and a 1.00-kΩ (R4).

8.2.2.14 PGOOD Pullup Resistor (R2)

A pullup resistor is required because the PGOOD pin is an open-drain output. Use a value between 10 kΩ to 100
kΩ. The recommended max 100 kΩ resistor is used.

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8.2.2.15 SCL and SDA Pulldown Resistors (R14 and R15)

If there is no PMBus (I2C) needed in the system, pull these two pins down to ground. If a PMBus interface is
always present, then these resistors are not needed. This example design uses 100-kΩ of resistance to pull
these pins down to ground, allowing it to operate with or without a PMBus interface.

8.2.2.16 PMBus Pullup Resistors

Due to the limited drive strength of pulldown MOSFETs on SDA and ALERT pins, the external PMBus pullup
resistors must be kept within certain ranges. For example, if the external PMBus supply is 3.3 V, then use a
pullup resistance of 1-kΩ. If the external PMBus supply is 5 V, then use a pullup resistance of 1.5 kΩ.

8.2.3 Application Curves

100
90 VIN AC
80
70 SW
Efficiency (%)

60
50
40
30
VOUT AC
20 DCM VIN (V) FCCM
10 8
12
14
0
0.001 0.01 0.1 1 10 100
Output Current (A)
fSW = 425 kHz VIN = 12 V IOUT = 25 A

Figure 39. Efficiency Figure 40. Output Ripple

9 Power Supply Recommendations

The TPS53819A device operates using an input voltage supply range between 3 V and 28 V (4.5-V to 28-V
biased). This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is
also critical for noise performance, as is PCB layout and grounding scheme.

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10 Layout

10.1 Layout Guidelines

Note these design considerations before starting a layout work using TPS53819A
• Inductor, VIN capacitors, VOUT capacitors and MOSFETs are the power components and should be placed on
one side of the PCB (solder side). Other small signal components can be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
• Place all sensitive analog traces and components such as FB, VO, TRIP, PGOOD, and EN away from high-
voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layers as ground
planes and shield feedback trace from power traces and components.
• Keep PMBus interfacing signals away from the sensitive analog traces.
• The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress
switching noise.
– The path from the VIN capacitors through the high and low-side MOSFETs and back to the capacitors
through ground, is the most important loop area to minimize. Connect the negative node of the VIN
capacitors and the source of the low-side MOSFET at ground as close as possible.
– The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors,
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of VOUT capacitors at ground as close as possible.
– The third important loop is that of the gate driving system for the low-side MOSFET. To turn on the low-
side MOSFET, high current flows from the VDRV capacitor through the gate driver and the low-side
MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET,
high current flows from gate of the low-side MOSFET through the gate driver and PGND of the device,
and back to source of the low-side MOSFET through ground. Connect the negative node of the VREG
capacitor, source of the low-side MOSFET and PGND of the device at ground as close as possible.
• A separate AGND from the high-current loop PGND should be used for the return of the sensitive analog
circuitry. The two grounds should connect at a single point as close to the GND pin as possible.
• Minimize the current loop from the VDD and VREG pins through their respective capacitors to the GND pin.
• Because the TPS53819A controls the output voltage referring to voltage across VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. In a same
manner both bottom side resistor and GND of the device should be connected to the negative node of VOUT
capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component
side and avoid vias between these resistors and the device.
• Connect the overcurrent setting resistor from the TRIP pin to ground and make the connections as close as
possible to the device. Avoid coupling a high-voltage switching node to the trace from the TRIP pin to RTRIP
and from RTRIP to ground .
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and vias of at least 0.5
mm (20 mils) diameter along this trace.
• The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
• Follow any layout considerations for the MOSFET provided by the MOSFET manufacturer.

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10.2 Layout Example

VIN VOUT

HF capacitor

LOUT
CIN COUT

SW

GND

Figure 41. Top Layer

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Layout Example (continued)

Bottom layer
PMBus

VIN
VOUT

U
1

CIN
COUT

GND

Figure 42. Bottom Layer

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS53819A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
PMBus is a trademark of SMIF, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback 45

Product Folder Links: TPS53819A
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS53819ARGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 3819A

TPS53819ARGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 3819A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Apr-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53819ARGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS53819ARGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Apr-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53819ARGTR VQFN RGT 16 3000 367.0 367.0 35.0
TPS53819ARGTT VQFN RGT 16 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RGT0016C SCALE 3.600
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1.0 C
0.8

SEATING PLANE

0.05 0.08
0.00

1.68 0.07 (0.2) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5 4
9

4X SYMM
1.5

1
12
0.30
16X
0.18
16 13 0.1 C A B
PIN 1 ID SYMM
(OPTIONAL) 0.05

0.5
16X
0.3

4222419/C 04/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGT0016C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.68)
SYMM
16 13

16X (0.6)

1
12

16X (0.24)
SYMM

(2.8)
(0.58)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA

5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222419/C 04/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGT0016C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.55)
16 13

16X (0.6)

1
12

16X (0.24)

17 SYMM

(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4222419/C 04/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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