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module counter

The document describes a Verilog module for a counter that increments or decrements based on the mode input and resets to zero when the reset input is active. It includes a test bench for simulating the counter's behavior with clock generation and input driving. The test bench also monitors and displays the values of the reset, clock, count, and mode signals during simulation.

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kkandasamy0303
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3 views2 pages

module counter

The document describes a Verilog module for a counter that increments or decrements based on the mode input and resets to zero when the reset input is active. It includes a test bench for simulating the counter's behavior with clock generation and input driving. The test bench also monitors and displays the values of the reset, clock, count, and mode signals during simulation.

Uploaded by

kkandasamy0303
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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module counter (mode,clk,reset,count);

input mode,clk,reset;
output reg [7:0] count;

//internal wires
wire [7:0] count_mux_out, rst_mux_out;

//combinational logic
assign count_mux_out = mode ? count + 1'b1: count - 1'b1;
assign rst_mux_out = reset ? 8'b0 : count_mux_out;

//sequential logic
always @( posedge clk)
begin
count <= rst_mux_out;
end
endmodule

TEST BENCH

module counter_test();

// wire/reg declaration
reg clk, reset, mode;
wire [7:0] count;

// Module instantiation
counter dut_counter (.clk(clk), .mode(mode), .reset(reset), .count(count));

//Generate vcd file


initial begin
$dumpfile("dump.vcd");
$dumpvars(0);
end

// Clock generation
always #5 clk=~clk;

// Driving inputs
initial
begin
clk=0;
reset=1; // active-high reset
#20; // waits 20ns
reset=0;
end

initial
begin
mode=1;
#180
mode=0;
#165
$finish;
end

// Displays values of wires being monitored


initial $monitor("Time = %d rst = %b clk = %b count = %b mode = %b", $time, reset, clk, count, mode);

end module

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