Module 1

8085 microprocessor:
 8085 is an 8-bit microprocessor.
 The “5” in the model number came from the fact that the 8085 requires only a +5 volt
power supply.
 It has a 16-bit address bus which are A0-A15.
 Data bus is a group of 8-bit D0-D7.
 The first 8 lines of address bus and the first 8 lines of the data bus are multiplexed as
AD0-AD7
 It supports external interrupt request.

8085 architecture:

8085 consists of the following functional units −

Accumulator

It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. The
data to be processed by ALU is stored in accumulator and also the result of the operation
carried out by the ALU. It is connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.

Program counter

It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being
executed.

Stack pointer

It is also a 16-bit register works like stack, which is always incremented/decremented by 2

during push & pop operations.

Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register

It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.

These are the set of 5 flip-flops −

 Sign (S)

 Zero (Z)

 Auxiliary Carry (AC)

 Parity (P)

 Carry (C)

Its bit position is shown in the following table –

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits −

 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’

 DMA Signals: HOLD, HLDA

 RESET Signals: RESET IN, RESET OUT

Interrupt control

As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is
completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).

Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the address
buffer and address-data buffer to communicate with the CPU. The memory and I/O chips are
connected to these buses; the CPU can exchange the desired data with the memory and I/O
chips.

Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the
location to where it should be stored and it is unidirectional. It is used to transfer the data &
Address I/O devices.
Pin diagram of 8085:

The pins of a 8085 microprocessor can be classified into seven groups −

Address bus

A15-A8, it carries the most significant 8-bits of memory/IO address.

Data bus

AD7-AD0, it carries the least significant 8-bit address and data bus.

Control and status signals

These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals.

Three control signals are RD, WR & ALE.

 RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.

 WR − This signal indicates that the data on the data bus is to be written into a
selected memory or IO location.

 ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.

Three status signals are IO/M, S0 & S1.

  IO/M - This signal is used to differentiate between IO and Memory operations, i.e.
when it is high indicates IO operation and when it is low then it indicates memory
operation.
 S1 & S0 - These signals are used to identify the type of current operation.

Power supply

There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.

Clock signals

There are 3 clock signals, i.e. X1, X2, CLK OUT.

 X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.

 CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.

Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

 INTA − It is an interrupt acknowledgment signal.

 RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.

 RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.

 READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.

 HOLD − This signal indicates that another master is requesting the use of the address
and data buses.

 HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after
the HOLD signal is removed.

Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.

 SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
  SID (Serial input data line) − The data on this line is loaded into accumulator
whenever a RIM instruction is executed.

Interfacing I/O devices

 Using I/O devices data can be transferred between the microprocessor and the
outside world.
 This can be done in 2 ways, transferring 8-bits using entire data bus called parallel I/O
and transferring 1 bit at a time using the SID and SOD pins called serial I/O.
 There are 2 ways to interface 8085 with I/O devices in parallel mode:
1. Memory mapped I/O
2. I/O mapped I/O

Instruction sets:
Control instructions

It includes the instructions related to interrupts and the instruction used to halt program
execution.
Data transfer instructions

Includes the instructions that moves data between registers or between memory locations
and registers.

Arithmetic instructions
Includes the instructions which performs the operations such as addition, subtraction,
increment or decrement operations.

Logical instructions

The instructions which perform logical operations such as AND, OR, NOT, XOR and
complement etc.
Branching instructions

The instructions that are used to transfer program control from one memory location to
another memory location are called branching instructions.

Module 2
Features of 8086
 It has an instruction queue, which is capable of prefetching six instruction bytes from
the memory.
 It was the first 16-bit processor having 16-bit ALU, registers, internal and external
data buses.
 It is available in 3 versions based on the frequency of operation
1. 8086 -> 5MHz
2. 8086-2 -> 8MHz
3. 8086-1 -> 10MHz
 It uses two stages i.e fetch stage and execute stage.
 Fetch stage can prefetch 6 bytes of instructions and stores them in the queue and
execution stage executes these instructions.
Architecture of 8086 microprocessor:

The 8086 microprocessor has two main execution units: the execution unit (EU) and the bus
interface unit (BIU).

The BIU is responsible for fetching instructions from memory and decoding them, while the
EU executes the instructions. The BIU also manages data transfer between the
microprocessor and memory or I/O devices.

The 8086 microprocessor has a rich set of registers, including general-purpose registers,
segment registers, and special registers.

 The general-purpose registers can be used to store data and perform arithmetic and
logical operations
 The segment registers are used to address memory segments.
 The special registers include the flags register, which stores status information about
the result of the previous operation.
 And the instruction pointer (IP), which points to the next instruction to be executed.

Bus interface unit (BIU)

The BIU has a direct link with the memory. This memory can be directly accessed either by
segment registers, instruction pointer or instruction queue.

1. Instruction queue:
 The instruction queue contains the set of instruction which is to be executed.
  Whenever one instruction completes its execution, the control unit need not to
wait for the next instruction to be fetched from the memory because this job is
already done by the instruction queue.

2. Segment registers:
 It contains the addresses of instructions and data which are used by the
processor to access memory locations.
 There are 4 segment registers:
CS: code segment register
DS: data segment register
SS: stack segment register
ES: extra segment register

3. Instruction pointer:
 The instruction pointer in 8086 microprocessor acts as a program counter.
 It indicates the address of the next instruction to be executed

Execution unit (EU)

The EU receives the opcode of an instruction from the queue, decodes it and then executes
it. While the EU decodes and executes the instructions, the BIU fetches the instructions from
the memory and stores them in the instruction queue.

1. General purpose registers:

 There are four 16-bit bit general purpose registers: AX, BX, CX and DX.
 Each of these 16-bit registers can be further divided into 8-bit registers as shown
below:
16-bit registers 8-bit high 8-bit low
order order
AX – accumulator AH AL
register
BX – base register BH BL
CX – counter CH CL
register
DX – data register DH DL

2. Control unit:
 All the instructions are executed inside the control unit. It is the main component
which is responsible for the processing.

3. Arithmetic and logic unit (ALU):

  All the mathematical and logical operations such as addition, subtraction, division,
AND, OR, NOT etc. are carried out in ALU.

4. Flag register:
 The flag register is of 16-bit length which consists of 9 flags and rest of the 7 flags
are don’t care flags.
 The 9 flags are divided into two groups, namely, conditional flags and control flags.
 Conditional flags represent the result of the last arithmetic or logical instruction
executed and the control flags controls the operations of the execution unit.
Conditional flags Control flags

 Carry flag  Trap flag

 Auxiliary flag  Interrupt flag
 Parity flag  Direction flag
 Zero flag
 Sign flag
 Overflow flag

8086 pin diagram:

1. AD0-AD15 (Address/Data bus):

 These are low order address bus. They are multiplexed with data.
 When AD lines are used to transmit memory address the symbol A is used instead
of AD, for example A0-A15.
  When data are transmitted over AD lines the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

2. A16-A19:

 High order address bus. These are multiplexed with status signals, S2,S1,S0.
S2 S1 S0
0 0 0 Interrupt acknowledge
0 0 1 Read IO port
0 1 0 Write IO port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state

3. RD:
 This is used for read operation. It is active when low (0).

4. READY:
 This is the acknowledgement from the memory or slow device that they have
completed the data transfer.
 The signal is active high (1).

5. INTR:
 This is triggered input. If any interrupt request is found pending, the processor
enters the interrupt acknowledge cycle.

6. NMI:
 NMI is non-maskable internally by software. A transition made from low (0) to high
(1) initiates the interrupt at the end of the current instruction.

7. MN/MX (minimum/maximum):
 This pin signal indicates what mode the processor will operate in.

8. RQ/GT1, RQ/GT0 (Request/Grant):

 These pins are used by local bus masters used to force the microprocessor to
release the local bus at the end of the microprocessor’s current bus cycle.

9. LOCK:
  It’s an active low pin. It indicates that other system bus masters have not been
allowed to gain control of the system bus while LOCK’ is active low(0).
 The LOCK signal will be active until the completion of the next instruction.

10. TEST:
 This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will
continue, else the processor remains in an idle state.

11. CLK (Clock Input):

 The clock input provides the basic timing for processing operation and bus control
activity.

12. RESET:
 This pin requires the microprocessor to terminate its present activity immediately.
The signal must be active high (1) for at least four clock cycles.

13. QS1/QS0 (Queue Status):

 These signals indicate the status of the internal 8086 instruction queue according
to the table shown below:
QS1 QS0 STATUS

0 0 No operation

0 1 First byte of OP
code from queue
1 0 Empty the queue

1 1 Subsequent byte
from queue

Addressing modes
The way for which an operand is specified for an instruction in the accumulator in a general-
purpose register or in memory location is called addressing modes.

Different types of addressing modes,

1. Register addressing:

 In register addressing, the operand is placed in one of the 16-bit or 8-bit general
purpose registers.
 Eg: MOV AX, CX
ADD AL, BL
 ADD CX, DX

2. Immediate addressing:

 In immediate addressing, the operand is specified in the instruction itself.

 Eg: MOV AL, 35H
MOV BX, 0301H
MOV [0401], 3598H
ADD AX, 4836H

3. Direct addressing:

 In direct addressing mode, the operand offset is given in the instruction as an 8-bit or
16-bit displacement element.
 Eg: ADD AL, [0301]

4. Indirect addressing:

 The operand offset is placed in any one of the register BX, BP, SI, DI as specified in the
instruction.
 Eg: MOV AX, [BX]

5. Based addressing:

 The operand offset is the sum of an 8-bit or 16-bit displacement and the content of
the base register BX or BP.
 BX is used as base register for stack segment and the BP is used as base register for
stack segment.
 Effective address (offset) = [BX+8-bit or 16-bit displacement]
 Eg: MOV AL, [BX+05];
MOV AL, [BX+1346H]

6. Indexed addressing:

 The offset of an operand is the sum of the content of an index register SI or DI and an
8-bit or 16-bit displacement.
 Offset (effective address) = [SI or DI + sum of 8-bit or 16-bit displacement]
 Eg: MOV AX, [SI+05]
MOV AX, [SI+1538H]

7. Based indexed addressing:

 The offset of an operand is the sum of the content of a base register BX or BP and an
index register SI or DI.
 Effective address(offset) = [BX or BP] + [SI or DI]
 Eg: ADD AX, [BX+SI]
MOV CX, [BX+SI]
8. Based indexed with displacement addressing:

 Effective address(offset) = [BX or BP] + [SI or DI] + [8-bit or 16-bit displacement]

 Eg: MOV AX, [BX+SI+05] -> 8-bit
MOV AX, [BX+SI+1235H] -> 16-bit

Assembly language program development tools

1. Editor

An editor is a program which allows you to create a file containing the assembly language
statements for your program.

When you have typed in all your program, you can save the file on hard disk with the
extension (.asm). This file is called source file.

2. Assembler

An assembler is a program used to translate the assembly language to corresponding binary

codes.

When you run the assembler, it reads the source file from the disk you have saved it after
editing.

The assembler generates 2 files on the hard disk. The first file is called the object file (.obj)
and the second file is called list file (.lst).

3. Linker

A linker is a program used to join several object files into one large object file.

The linker produces a link file which contains the binary codes for all combined files. It also
produces a link map file which contains the address information about the linked files (.exe).

4. Locator

A locator is a program used to assign the specific address of where the segments of object
code are to be loaded into memory.

5. Debugger

A debugger is a program which allows you to load your object code program into system
memory, execute the program and troubleshoot or debug it.

6. Emulator

An emulator is a mixture of hardware and software. It is used to test and debug hardware
and software of an external system.
Assembler directives
Directives Meaning
ASSUME Used to inform the assembler the name of the segment
DB Used to declare a byte variable
DD Used to declare a variable of type double word
DW Used to declare a word type variable
DQ Used to declare a variable of 4 words in length
DT Used to reserve 10 bytes of storage in memory
EQU Used to give a name to some value or symbol
ORG Changes the starting offset address of the data
PROC Used to identify the start of a procedure
END Indicates the end of a program
ENDP Indicates the end of a procedure
ENDS Indicates the end of a segment

Module 3
String manipulation instructions of 8086
 String in assembly language is just a sequentially stored bytes or words.
 8086 instruction set includes instructions for string movement, comparison, scan,
load and store.
 String instructions end with S (string) or SB (string byte) or SW (string word).
 Offset or effective address of the source operand is stored in the SI register and that
of the destination operand is stored in the DI register.

MOVS/MOVSB/MOVSW: (from SI to DI)

 It causes moving of byte or word from one string to another.

 In this instruction, the source string is in data segment referred by DS:SI and
destination string is in extra segment referred by ES:DI

LODS/LODSB/LODSW: (from SI to accumulator)

 It causes transfer of byte or word from one string to another.

 In this instruction, the string is in data segment referred by DS:SI transferred to
accumulator.

STOS/STOSB/STOSW: (from DI to accumulator)

 It causes transfer of byte or word from one string to another.

  In this instruction, the string is in extra segment referred by ES:DI transferred to
accumulator.

CMP Des, Src:

 It stands for ‘compare destination with source’.

 It compares the string bytes or words.

SCAS:

 It scans a string
 It compares the string with byte in AL or with word in AX.

REP:

 This is an instruction prefix.

 It causes the repetition of the instruction until CX becomes zero.

Procedure
A procedure is a group of instructions that usually performs one task.

It is a reusable section of a program which is stored in memory once but can be used as
often as necessary.

Syntax:

name PROC

procedure body //here goes the code of the procedure

RET

name ENDP

name is the procedure name, the same name should be used in the top and the bottom, this
is used to check correct closing of the procedures.

RET instruction is used to return to operating system. The same instruction is used to return
from procedure.

PROC and ENDP are compiler directives, they are not assembled into any real machine code.
They are used to start and end a procedure.

The procedure is called from another function using the CALL instruction. The CALL
instruction should have the name of the called procedure as an argument.

CALL proc_name
The CALL instruction is used to transfer execution to a procedure.

The called procedure returns the control to the calling procedure by using the RET
instruction.

ORG 100h

MOV AL, 1

MOV BL, 2

CALL m2

CALL m2

CALL m2

CALL m2

RET

m2 PROC

MUL BL

RET

m2 ENP

END

In the above example the value of AL register is updated every time the procedure is called,
BL register stays unchanged.

The procedure is called four times which calculates 2 in power of 4 so the final answer is 16
in AL register.

The stack
Stack is an area of memory for keeping temporary data.

Stack is used by CALL instruction to keep return address for procedure, RET instruction gets
this value from the stack and returns to that offset.

There are two instructions that work with the stack:

 PUSH – stores 16 bit value in the stack

 POP – gets 16 bit value from the stack

It is very important to do equal number of PUSHs and POPs, otherwise the stack maybe
corrupted and it will be impossible to return to operating system.
Macro
A MACRO is a group of small instructions that usually performs one task. It is a reusable
section of a software program.

A MACRO can be defined by using the directives MACRO and ENDM.

name MACRO [ARGUMENT 1, ARGUMENT 2…ARGUMENT N]

macro body //macro code goes here

ENDM

Module 4
8253/54 microprocessor
 8253 and 8254 are devices designed to solve timing and control problems in a
microprocessor.
 They have 3 independent counter which are of 16-bit size.
 Both of the devices operate in +5V regulated power supply and has 24 pin signals.
 The 8254 is an advanced version of 8253.
There are three counters, a data bus buffer, read/write control logic, and a control register.
Each counter has two input signals (CLOCK & GATE) and one output signal (OUT).

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.

 Reading the count values.

Read/Write control Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A1.

In the I/O mode, the RD and WR signals are connected to IOR and IOW and in the memory
mapped I/O mode, these are connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is
tied to a decoded address.

The control register and counters are selected according to the signals on lines A 0 & A1.

Control Register

This register is accessed when lines A0 & A1 are at 1.

It is used to write a command word, which specifies how the counter is to be used, its mode
type, and if it’s either a read or write operation.
Difference between 8253 and 8254

8255A - programmable peripheral interface

 The 8255A is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O. It can be used with almost any microprocessor.
 It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be configured
as per the requirement.

8255A ports

8255A has three ports i.e PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.

 Port B is similar to PORT A.

 Port C can be split into two parts i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.

Operating Modes

8255A has three different operating modes −

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit
ports.

 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. Each port uses three
lines from port C as handshake signals.

 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals
for data transfer. The remaining three signals from Port C can be used either as
simple I/O or as handshake for port B.
8255A architecture

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus.

Data is transmitted or received by the buffer as per the instructions by the CPU.

Control words and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal and external transfer of data.

It accepts the input from the CPU address and control buses.

CS – chip select

It stands for Chip Select.

A LOW on this input selects the chip and enables the communication between the 8255A
and the CPU.

It is connected to the decoded address and A0 & A1 are connected to the microprocessor
address lines.

8257 DMA controller

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate.
It allows the device to transfer the data directly to/from memory without any interference of
the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory.

The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

DMA operations

 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.

 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.

 Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through HLDA
signal.

 Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the CPU, memory, and I/O devices.

8257 architecture

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus.

Data is transmitted or received by the buffer as per the instructions by the CPU.

Control words and status information is also transferred using this bus.

Read/Write Logic

This block is responsible for controlling the internal and external transfer of data.

It accepts the input from the CPU address and control buses.

Control logic

The control logic determines which of the 4 channels the processor should access with the
help of the priority resolver.

Priority resolver is a program just like queue to set priorities for the occurring interrupts.

The control logic has the pins HLDA, HRQ which sends the hold request and receives the
hold acknowledgement from the CPU.

8257 pin diagram

DRQ0 − DRQ3:

 These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services.
 When the fixed priority mode is selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
DACKo − DACK3: These are the active-low DMA acknowledge lines, which updates the
requesting peripheral about the status of their request by the CPU.

Do − D7: These are bidirectional, data lines which are used to interface the system bus with
the internal data bus of DMA controller.

IOR:

 It is an active-low bidirectional tri-state line, which is used by the CPU to read

internal registers in the Slave mode.
 In the master mode, it is used to read data from the peripheral devices.

IOW is an active low bi-direction tri-state line, which is used to load the contents of the data
bus to the 8-bit mode register or 16-bit DMA address register or terminal count register.

CLK is a clock frequency signal which is required for the internal operation.

RESET signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3:

 These are the four least significant address lines.

 In the slave mode, they act as an input line which selects one of the registers to be
read or written.
 In the master mode, they act as four least significant memory address output lines.

CS is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257.

In the master mode, it disables the read/write operations to/from 8257.

A4 - A7: These are the higher nibble of the lower byte address generated by DMA in the
master mode.

READY makes DMA ready by inserting wait states.

HRQ signal is used to receive the hold request signal from the output device.

In the slave mode, it is connected with a DRQ input line.

In Master mode, it is connected with HOLD input of the CPU.

HLDA is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU.

MEMR is the read signal which is used to read the data from the addressed memory
locations during DMA read operation.

MEMW is the signal which is used to write the data to the addressed memory location
during DMA write operation.
ADST signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.

AEN signal is used to disable the address bus/data bus.

TC stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.

The MARK will be activated after each 128 cycles or integral multiples of it from the
beginning.

Vcc is the power signal which is required for the operation of the circuit.

8259 – programmable interrupt controller

The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor.

It was designed for 8085 and 8086 microprocessors to increase the interrupt handling
capability.

Data bus buffer

This block is used to communicate between 8259 and 8085/8086 by acting as buffer.

It transfers the opcode of the selected interrupts and address of ISR to the other connected
microprocessor.

R/W control logic

This block works when the value of pin CS is 0.

It is used to flow the data depending upon the inputs of RD and WR.
Control logic

It controls the functionality of each block. It has pin called INTR. This is connected to other
microprocessors for taking the interrupt request. The INT pin is used to give the output.

Interrupt request register

It stores all interrupt level that are requesting for interrupt service.

Interrupt service request

It stores interrupt level that are currently being execute.

Interrupt mask register

It stores interrupt level that will be masked, by storing the masking bits of interrupt level.

Priority resolver

It checks all three registers, and set the priority of the interrupts. Interrupt with the highest
priority is set in the ISR register.

Cascade buffer

To increase number of interrupt pin, we can cascade a greater number of pins, by using
cascade buffer.

When we are going to increase the interrupt capability, CSA lines are used to control
multiple interrupts.

8259 pin diagram

 Module 5
80286 microprocessor features
80286 is a 16-bit microprocessor which has the ability to execute 16-bit instructions at a
time.

It has non-multiplexed data and address bus, means that they have separate lines for
sending data and address.

The size of data bus is 16-bit and address bus is 24-bit.

It has two operating modes, real address mode and virtual address mode.

In real address mode, it can address up to 1Mb memory address and in virtual mode it can
address up to 16Mb.

The performance of 80286 is 5 times faster than 8086.

80286 architecture

The CPU of 80286 has 4 functional blocks:

 Address unit
 Bus unit
 Instruction unit
 Execution unit

Address unit:

 The physical address from where the data or instructions is to be fetched is

calculated by this unit.
 Once the physical address is calculated then it hands over the calculated addresses
to the bus unit.
 It consists of segment registers, offset address and a physical address.
Bus unit:

 This address specifies the memory location from where the data is to be fetched. The
fetching of the data is done by this unit.
 For faster execution, it prefetches instructions and stores them in the memory.

Instruction unit:

 The prefetched instructions are stored in a 6 byte instruction queue. This queue then
further sends the instructions to the instruction unit.
 This unit decodes the instructions prefetched by the bus unit. It fully decodes the
instructions and stores them in decoded instruction queue so that EU can access
them.

Execution unit:

 The instructions from decoded instruction queue are fed to the execution unit.
 The main component of EU is ALU that performs arithmetic and logical operations
according to the decoded instructions.
 It includes ALU, registers and the control unit.

80486 microprocessor architecture

80486 microprocessor is of 32-bit size. It is the advanced version of 80386.

One of its feature is a built in math coprocessor. It allows it to execute math instructions
about three times faster than 80386.

It operates on 25MHz, 33MHz, 50MHx, 60MHz, 66MHz and 100MHz.

It has three modes: real, protected and virtual mode.