Register Transfer Level

&
Design with ASM

Logic and Digital System Design - CS 303

1
 Overview
• Register transfer level (RTL) to model complex digital
systems
– a level of abstraction used in describing operations of
synchronous digital circuits
– a circuit's behavior is defined in terms of the transfer of data
between hardware registers, and the operations performed on
data.
• Goal: Algorithmic expression of a digital system
• Algorithmic State Machine (ASM) charts
– to model complex digital systems
– to map a complex design into hardware
2
 Register Transfer Level
• Designing a complex digital system using state tables
becomes difficult as the number of states increases
• Remedy
– partition the system into modular subsystems
– each module is designed separately
– modules are connected to each other
• A digital module is best defined by
1. A set of registers
2. Operations on the binary information stored in them

3
 Register Transfer Level
• Register operations
– move, copy, shift, count, clear, load, add, subtract
• A digital system is said to be represented at the register
transfer level (RTL) when it is specified by the following
three components
1. Set of registers
2. Operations performed on the data stored in the
registers
3. The control supervises the sequence of operations in
the system

4
 The Control
• Control logic
– Initiates the sequence of operations
– generates timing (control) signals that sequence the
operations in a prescribed manner
• The outputs of control logic are binary signals that initiate
the various operations in registers
– Certain conditions that depend on the previous operations
may determine the sequence of future operations
• Transfer statement
– R2  R1 (“replacement” operation)
• Conditional transfer statement
– if(T1 = 1) then R2  R1
– T1 is checked and a control signal set to a proper value
5
 Register Transfer Operations
• In register transfer operations, clock is not explicitly shown
– but, transfer is assumed to happen at the clock edge.
– previous example
• if (T1 = 1) then R2  R1
• T1 may become 1 before the clock edge, but actual transfer
happens exactly at the clock edge.
• Examples:
– if (T3 = 1) then (R2  R1, R1  R2)
– R1  R1 + R2
– R3  R3 + 1
– R4  shr R4
– R5  0 6
 Types of Register Operations
• Four categories
1. transfer operations
2. arithmetic operations
3. logic operations
4. shift operations

7
 Datapath and Control

Control signals

Control Control Status signals

inputs Datapath
Unit

• One obvious distinction

1. design of datapath (data processing path)
2. design of control circuit
8
 Hardware Algorithm & ASM Chart
• (Digital) hardware algorithm
– is a procedure for implementing a digital circuit with given
pieces of hardware equipments
– specifies the control sequence and datapath tasks
• Algorithmic state machine (ASM) chart is a special type
of flowchart used to define digital hardware algorithms.
– state machine is another term for a sequential circuit
• ASM chart describes
– the sequence of events,
– events that occur at state transitions.
9
 ASM Chart
• Three basic elements
1. State box
2. Decision box
3. Conditional box

10
 State Box
A 1011

START
name R0
state
assignment

• The output signals (e.g., START) in the box take the

specified values in the current state
– if not specified they are 0 in other states .
• The notation R  0 means that the register is cleared
to 0 when the system transits from A to the next state

11
 State Box
A 1011

START
name R0
state
assignment

START

Control RESET_R R

12
 Decision Box
0
J
1

• Decision box has two or more branches going out.

• Decision is made based on the value of one or more
input signals (e.g., signal J)
• Decision box must follow and be associated with a
state box.
• Thus, the decision is made in the same clock cycle as
the other actions of the state.

13
 Decision Box
0
J
1

Control signals

Control Control Status signals

inputs Datapath
Unit

START

J Control RESET_R R

14
 Conditional Box
Register operation
or output

• A conditional box must follow a decision box.

• A conditional box is attached to a state box
through one or more decision boxes.
• Therefore, the output signals in the conditional output
box are asserted in the same clock cycle as those in
the state box to which it is attached.
• The output signals can change during the current state as a
result of changes on the inputs.
• The conditional output signals are sometimes referred
as Mealy outputs since they depend on the input signals
as well.
15
 Conditional Box
Register operation S0
or output ENABLE

0
J
1
START
R0

START START

Control RESET_R R
ENABLE RESET_R
16
J
 Example: Traffic Control
Major road

Minor road
sensor

car/start_timer

major=G major=R timed’

car’ minor=R minor=G

timed
17
 Datapath & Control

MAJOR
MAJOR

car
Sensor Control

MINOR
start_ MINOR
timed timer

Counter
Datapath
18
 Example: ASM Chart
G MAJOR
MAJOR

car
Sensor Control MINOR
MAJOR
MINOR
start_
timed
timer
0
car
Counter
1 Datapath

start_timer

R
ASM Block
MINOR

1 0
timed
19
 Traffic Controller with a Timer
• There is an abundance of states.
G • states from s0 to s255 map to a
MAJOR simple counter
• we can just separate the traffic
0
car light controller from the timer.
s0 1

MINOR

s255

MINOR

20
 Linked ASM Charts
G
IDLE
MAJOR

0
car 0
start
1 s0 1

start_timer

R
s255

MINOR timeup

1 0
timed
21
 Linked ASM Charts
G
IDLE
MAJOR
CNT  0

0
car 0
start
1 1
COUNT
start_timer
CNT  CNT+1
R

MINOR
timeup

1
1 0
timed
22
 Linked ASM Charts
G IDLE

MAJOR CNT  0

0
0 start
car
COUNT 1
1
start_timer CNT  CNT+1

MINOR CNT=255

1 0 timeup
timed
23
 Traffic Control Example - Schematic

Note that present_state, start_timer and timed outputs

are normally not shown (they are internal). Here, they are used for
debugging 24
`timescale 1ns / 1ps Verilog Code – Counter 1/2
module Counter(input clk, reset, start, output reg timeup);
reg state;
reg [2:0] CNT;
parameter IDLE = 1'b0, COUNT = 1'b1, LIMIT = 3'd6;
//Sequential part
always @ (posedge clk or posedge reset)
if (reset) reset
state <= IDLE; CNT <= 0;
start timeup
else case(state)
IDLE:
CNT <= 0;
if(start) state <= COUNT; else state <= IDLE;
COUNT:
CNT <= CNT+1;
if(timeup) state <= IDLE; else state <= COUNT;
default:
CNT <= CNT;
state <= IDLE;
endcase
25
...
 Verilog Code – Counter 2/2
...

//Combinational output circuit

always@(*)
case (state)
COUNT:
if(CNT == LIMIT)
timeup = 1'b1;
else
timeup = 1'b0;
default:
timeup = 1'b0;
endcase

endmodule

26
 Verilog Code –Trafic Light 1/4
`timescale 1ns / 1ps
module TraficLight (clk, reset, car, timed, MAJOR, MINOR, start_timer, pres_state);

input clk, reset, car, timed; MAJOR

output MAJOR, MINOR, start_timer, pres_state;

reg next_state;
reset MINOR
reg pres_state;
car start_timer
reg MAJOR;
reg MINOR;
reg start_timer; timed pres_state
parameter
ST_G = 1'b0,
ST_R = 1'b1;

// FSM starts
//Sequential circuit state transitions
always@(posedge clk or posedge reset)
begin
if(reset)
pres_state <= ST_G;
else
pres_state <= next_state;
end
... 27
 Verilog Code –Trafic Light 2/4
...
//Combinational circuit for state transition
always@(*)
case (pres_state)
ST_G:
if(car)
next_state = ST_R;
else
next_state = pres_state;
ST_R:
if(timed)
next_state = ST_G;
else
next_state = pres_state;

default:
next_state = ST_G;

endcase
...

28
 Verilog Code –Trafic Light 3/4
...
//Combinational circuits outputs
always@(*)
case(pres_state)
ST_G:
if(car)
start_timer = 1; // Mealy output
else
start_timer = 0;// Mealy output
default:
start_timer = 0;
endcase

// FSM ends
...

29
 Verilog Code –Trafic Light 4/4
...
// DATAPATH STARTS: We have 2 register at datapath MAJOR and MINOR
//DATAPATH starts

always@(*)
begin
case(pres_state)
ST_R:
begin
MAJOR = 0; // Moore output
MINOR = 1; // Moore output
end
default:
begin
MAJOR = 1; // Moore output
MINOR = 0; // Moore output
end
endcase
end

//DATAPATH ends

endmodule
30
 Traffic Control Example - Simulation

• Note 1: 0 is state Green and 1 is state Red for

present_state.
• Note 2: Second time the “car” signal is asserted, the
system is not affected, because the system is designed in
this way (i.e., the car signal is effective only when the
present state is Green).
31
 Traffic Control Example - Verilog Code

• Please see the files “TrafficLight.v” and “Counter.v” for

verilog codes of the traffic control example.
• Note that these modules are seperate and they are used
– in a schematic file called “TrafficControl_sch.sch”,
– and, in a verilog file called “TrafficControl.v”.

32
 ASM Block
• A structure consisting of one state box and all the decision
and conditional boxes associated with it.

T1 001

AA+1

0 1
e

0 1
f R0

T2 010 T3 011 T4 100

33
 ASM Block
• One input path, any number of exit T1 001

paths AA+1

0 1
e
• Each ASM block describes the state 0 1
R0
f

of a system during one clock-pulse T2 010 T3 011 T4 100

interval
– The register operations within the
state and conditional boxes in the
example are executed with a common
clock pulse when the system in this
state (e.g. T1 in the example)
– The same clock pulse transfer the
system controller to one of the next
states (e.g. T2, T3, or T4) 34
 Timing Considerations 1/4
• The pulses of the common clock are applied to
– registers in the datapath
– all flip-flops in the control
• We can assume that inputs are also synchronized with
the clock
– Since they are the outputs of another circuit working with the
same common clock.
– Synchronous inputs

35
 Timing Considerations 2/4
• Major difference between a conventional flow chart
and ASM chart is in the time relations among the
various operations
• Example T1 001

AA+1
start

0 1
e

0 1
f R0

T2 010 T3 011 T4 100

36
 Timing Considerations 3/4
• If it were a conventional flowchart
1. A  A + 1 T1 001

2. start = 1 AA+1
start
3. if e = 1 then 0 1
e
R  0 0 1
f R0
next state is T4
T2 T3 011 T4 100
010
4. else
if f = 1 then
next state is T3
else
next state is T2

37
 Timing Considerations 4/4
• But, in ASM chart, interpretation is
different
T1
– all operations in a block occur in 001

AA+1
synchronism with the clock start
– “start” is asserted in T1 0 1
e
– input signals “e” and “f” are checked in T1 0 1
f R0
– The following operations are executed
simultaneously during the next positive T 2 010
T3 011 T4 100

edge of clock
• AA+1
• R  0 (if e = 1)
• control transfer to the next state

clock

next state
present state T1 38
T2 or T3 or T4
 Example: Binary Multiplier
• Sequential multiplier
• Algorithm: successive additions and shifting
multiplicand y3 y2 y1 y0

multiplier x3 x2 x1 x0
partial product x0 y3 x0 y2 x0 y1 x0 y0

x1 y3 x1 y2 x1 y1 x1 y0

x2 y3 x2 y2 x2 y1 x2 y0

+ x2 y3 x3 y2 x3 y1 x3 y0

z7 z6 z5 z4 z3 z2 z1 z0
product 39
 Schematic of Binary Multiplier
• Register Configuration if P= 0 then Z = 1

multiplicand
Register B Check for Z
zero
Q0 Control
logic
P
cout Parallel
adder n S
(start)
sum multiplier
0 C Register A Register Q

Product 40
 Hardware Algorithm for n-bit Multiplier
Input: X, Y, n = log2X
Output: Z = XY
Step 0. if (Start == 0) do nothing
else go to Step 1;
Step 1. Q  X; B  Y; A  0; C  0; P  n;
go to Step 2;
Step 2. P  P-1;
if(Q0 == 1)
A  A+B; C  Carry(A+B);
go to Step 3;
Step 3. CAQ  shr(CAQ); C  0;
if (P == 0) go to Step 0;
41
else go to Step 2;
 Example: ASM Chart
T0

A  A + B, C  Cout
0 S

T1 1
Q  X; A  0 T3
B  Y; C  0
Shift Right CAQ, C  0
Pn

T2 0 1
P=0
PP-1

A  shr A, An-1  C
0 1
Q0 Q  shr Q, Qn-1  A0
C0
42
 Example: ASM Chart
T0

A  A + B, C  Cout
0 S

1
QX; A  0 T3
B  Y; C  0 Shift Right CAQ, C  0
Pn

T2 0 1
P=0
PP-1

A  shr A, An-1  C
0 1
Q0 Q  shr Q, Qn-1  A0
C0
43
 Multiplier – Verilog Code 1/7
module TopModule(x, y, n, clk, start, reset, out, state, p);

input [3:0] x, y, n;
input clk, start, reset;

output [8:0] out;

output [1:0] state;
output [3:0] p; // counter

reg [8:0] out;

reg [1:0] state;

reg [3:0] b, a, q, p;
reg c;

parameter t0 = 0, t1 = 1, t2 = 2, t3 = 3;
parameter zero = 0;
...

44
 Multiplier – Verilog Code 2/7
...
module TopModule(x, y, n, clk, start, reset, out, state, p);
...
// combinational part for output
always @ *
begin
case (state)
t0:
out = {c, a, q};
t1:
out = {c, a, q};
t2:
out = {c, a, q};
t3:
out = {c, a, q};
default:
out = {c, a, q};
endcase
end
45
...
 Multiplier – Verilog Code 3/7
...
// Sequential part
always @(posedge clk or posedge reset)
reset
if (reset)
begin
state <= t0; from T3
a <= zero; T0
b <= zero;
c <= zero;
q <= zero; 0
S
p <= zero; // counter
end 1
else to T1
...

46
 Multiplier – Verilog Code 4/7
...
// Sequential part (cont.)
always @(posedge clk or posedge reset)
reset
if (reset)
...
else from T3
case (state) T0
t0:
if(start)
state <= t1; 0
S
else
state <= t0; 1
to T1
...

47
 Multiplier – Verilog Code 5/7
...
always @(posedge clk or posedge reset)
if (reset)
... from T0
to T0
else
case (state) 0
S
...
T1 1
t1:
Q  X; A  0
begin B  Y; C  0
b <= y; Pn
q <= x;
p <= n;
to T2
state <= t2;
end

...

48
 Multiplier – Verilog Code 6/7
...
always @(posedge clk or posedge reset) T2
if (reset) PP-1
...
0 Q0 1
else
case (state) To T3
...
A  A + B, C  Cout
t2:
begin To T3
p <= p - 1;
if(q[0] == 1'b0)
state <= t3;
else
begin
{c, a} <= a + b;
state <= t3;
end
end
...
49
 Multiplier – Verilog Code 7/7
...
from T2
always @(posedge clk or posedge reset)
if (reset) T3
... Shift Right CAQ, C  0

else
case (state) 0 1
P=0
...
t3: to T2 to T0
begin
{c, a, q} <= {1'b0, c, a, q[3:1]};
if(p == 0)
state <= t0;
else
state <= t2;
end
default:
if(start) state <= t1;
else state <= t0;
endcase
endmodule 50
 Multiplier – Verilog Code 1/6
module TopModule(x, y, n, clk, start, reset, out, state, p);

input [3:0] x, y, n;
input clk, start, reset;

output [8:0] out;

output [1:0] state;
output [3:0] p; // counter

reg [8:0] out;

reg [1:0] state;

reg [3:0] b, a, q, P;
reg c;

parameter t0 = 0, t2 = 2, t3 = 3; // we skip the state T1

parameter zero = 0;
...

51
 Multiplier – Verilog Code 2/6
...
module TopModule(x, y, n, clk, start, reset, out, state, p);
...
// combinational part for output
always @ *
begin
case (state)
t0:
out = {c, a, q};
t2:
out = {c, a, q};
t3:
out = {c, a, q};
default:
out = {c, a, q};
endcase
end
...

52
 Multiplier – Verilog Code 3/6
...
// Sequential part
always @(posedge clk or posedge reset)
reset
if (reset)
begin
state <= t0; from T3
a <= zero; T0
b <= zero;
c <= zero;
q <= zero; 0
S
p <= zero;
end 1
else to T1
...

53
 Multiplier – Verilog Code 4/6
...
// Sequential part (cont.)
always @(posedge clk or posedge reset)
reset
if (reset)
...
else from T3
case (state) T0
t0:
if(start)
b <= y; 0
S
q <= x;
P <= n; 1
state <= t2;
QX; A  0
else B  Y; C  0
state <= t0; Pn

... to T2

54
 Multiplier – Verilog Code 5/6
...
always @(posedge clk or posedge reset) T2
if (reset) CNT  CNT - 1
...
0 Q0 1
else
case (state) To T3
...
A  A + B, C  Cout
t2:
begin To T3
p <= p - 1;
if(q[0] == 1'b0)
state <= t3;
else
begin
{c, a} <= a + b;
state <= t3;
end
end
...
55
 Multiplier – Verilog Code 6/6
...
from T2
always @(posedge clk or posedge reset)
if (reset) T3
... Shift Right CAQ, C  0

else
case (state) 0 1
CNT=0
...
t3: to T2 to T0
begin
{c, a, q} <= {1'b0, c, a, q[3:1]};
if(p == 0)
state <= t0;
else
state <= t2;
end
default:
if(start) state <= t1;
else state <= t0;
endcase
endmodule 56
 Multiplier – Test Code 1/4
`timescale 1ns / 1ps
module topmoduleTest;

// Inputs
reg [3:0] x;
reg [3:0] y;
reg [3:0] n;
reg clk;
reg start;
reg reset;

// Outputs
wire [8:0] out;
wire [1:0] state;
wire [3:0] p;
...

57
 Multiplier – Test Code 2/4
`timescale 1ns / 1ps
module topmoduleTest;
...
// Instantiate the Unit Under Test (UUT)
TopModule uut (
.x(x),
.y(y),
.n(n),
.clk(clk),
.start(start),
.reset(reset),
.out(out),
.state(state),
.p(p)
);
...

58
 Multiplier – Test Code 3/4
`timescale 1ns / 1ps
module topmoduleTest;
...
initial begin
// Initialize Inputs
x = 0;
y = 0;
n = 0;
clk = 0;
start = 0;
reset = 0;
...

59
 Multiplier – Test Code 4/4
`timescale 1ns / 1ps
module topmoduleTest;
...
initial begin
...
// Wait 15 ns for global reset
#15
reset = 1;
#10
reset = 0;
#5
start = 1;
n = 4;
x = 10;
y = 13;
#10
start = 0;
#200;
end
always #10 clk = ~clk;
endmodule
60
Multiplier – Simulation 1/3

61
Multiplier – Simulation 2/3

62
Multiplier – Simulation 3/3

63