Bengaluru 560 103, Karnataka, India

Department of Electrical and Electronics Engineering

Course Code: 22EEL52

CMOS VLSIGN DESIGN LAB

Manual
Academic Year 2024-25
Odd Semester

BACHELOR OF ENGINEERING
in
ELECTRICAL AND ELECTRONICS ENGINEERING

VISVESVARAYA TECHNOLOGICAL UNIVERSITY

“Jnana Sangama”, Belgaum – 590018, Karnataka, India
 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

LABORATORY MANUAL

COURSE NAME : CMOS VLSI DESIGN LAB

COURSE CODE : 22EEL52

SEMESTER : 5th SEM

ACADEMIC YEAR : 2024 – 2025

PREPARED BY AUTHORIZED BY

Ms. SANGEETHA C N Ms. SURAT PYARI ATTI Dr. A. SAKTHIVEL

 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
Department Vision, Mission and PEOs
VISION

To evolve into a centre of excellence in Electrical and Electronics Engineering for bringing out contemporary
Engineers, Innovators, Researchers and Entrepreneurs for serving nation and society.

MISSION

● To provide suitable forums to enhance the teaching-learning, research and development activities.
● Framing and continuously updating the curriculum to bridge the gap between industry and
academia in the contemporary world and serve society.
● To inculcate awareness and responsibility towards the environment and ethical values.
.

PROGRAM EDUCATIONAL OBJECTIVES (PEO’s)

PEO1: To provide good learning environment to develop entrepreneurship capabilities in various areas of
Electrical and Electronics Engineering with enhanced efficiency, productivity, cost effectiveness and
technological empowerment of human resource.

PEO2: To inculcate research capabilities in the areas of Electrical and Electronics Engineering to identify,
comprehend and solve problems and adopt themselves to rapidly evolving technology.

PEO 3: To create high standards of moral and ethical values among the graduates to transform them as
responsible citizens of the nation.

PROGRAM SPECIFIC OUTCOMES (PSO’s)

PSO 1: Graduates will be able to solve real life problems of power system and power Electronics using
MiPower, PSPICE and MATLAB software tools and hardware.

PSO 2: Graduates will be able to Develop & support systems based on Renewable and sustainable Energy
sources.
 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

PROGRAM OUTCOMES (POs)

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals and an
engineering specialization to the solution of complex engineering problems in Electrical and Electronics
Engineering.

PO2: Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems in Electrical and Electronics Engineering reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.

PO3: Design / Development of solutions: Design solutions for complex engineering problems and design system
components or processes of Electrical and Electronics Engineering that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental considerations.

PO4: Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments in Electrical and Electronics Engineering, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.

PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering
and IT tools including prediction and modelling to complex engineering activities in Electrical and Electronics
Engineering with an understanding of the limitations.

PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice
in Electrical and Electronics Engineering.

PO7: Environment and sustainability: Understand the impact of the professional engineering solutions of
Electrical and Electronics Engineering in societal and environmental contexts, and demonstrate the knowledge of
and need for sustainable development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.

PO9: Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.

PO11: Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.

PO12: Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOME (PSOs)

PSO 1: Graduates will be able to solve real life problems of Power system and Power Electronics using MiPower,
PSPICE and MATLAB software tools and hardware.

PSO 2: Graduates will be able to develop and support systems based on renewable and sustainable Energy
 CMOS VLSI DESIGN LAB

Course Code: 22EEL52 Credits: 01

L: T: P: S : 0:0:1:0 CIE Marks: 50
Exam Hours: 03 SEE Marks: 50
Course Outcomes: At the end of the course, the students will be able to

CO1 Demonstrate the working of analog and digital CMOS circuits through simulation

CO2 Use the schematics of CMOS circuits to construct and verify their layouts

CO3 Apply Switch level description to digital CMOS circuits Modeling

CO4 Employ the Gate level description of digital CMOS circuits for simulation and synthesis

Mapping of Course Outcomes to Program Outcomes:

CO/ PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
PO
CO1 3 3 2 1 3 - - - 2 - - 3 3 2
CO2 3 - - - 3 - - - - - - 3 3 2
CO3 3 - - - 3 - - - - - - 3 3 2
CO4 3 3 3 1 3 - - - - - - 3 3 2

SYLLABUS
S.No. List of experiments COs
Cycle-1
1. Draw the schematic of CMOS Inverter for the given specifications, and verify
using Transient and DC Analyses. CO1, CO2
2. Draw the schematic of the following circuits for the given specifications, and
verify using Transient and DC Analyses: i) 2-input CMOS NAND gate, ii) CO1, CO2
2-input CMOS NOR gate.
3. Draw the schematic of transmission gate for the given specifications, and
CO1, CO2
verify using Transient and DC Analyses.
4. Draw the schematic of the following amplifiers for the given specifications,
and verify the same using Transient, DC and AC Analyses: i) Common CO1, CO2
Source amplifier, ii) Common Drain amplifier.
5. Draw the layout of the CMOS Inverter and perform physical verification
using DRC, ERC and LVS. Extract RC and back-annotate the same and CO1, CO2
verify the Design.
6. Draw the layout of the following circuits and perform physical verification
using DRC, ERC and LVS. Extract RC and back-annotate the same and
CO1, CO2
verify the Design: i) 2-input CMOS NAND gate ii) 2-input CMOS NOR
gate.
Cycle-2
7. For the following circuits, write the switch level Verilog Code, and verify
using Test Bench: i) CMOS inverter, ii) 2-input CMOS NAND and NOR CO1, CO3
gates.
8. For the following circuits, write the switch level Verilog Code and verify
using Test Bench: i) 2-input EXOR gate using CMOS logic, ii) 2-input CO1, CO3
EXOR gate using PTL.
9. Synthesize the following circuits using the gate level Verilog Code, with the
given Constraints: i) CMOS inverter, ii) 2-input CMOS NAND and NOR CO1, CO4
gates.
10. For the following circuits, write the Verilog Code, verify using Test Bench,
and then synthesize with the given Constraints: i) 4-bit Parallel adder ii) D CO1, CO4
Flip-flop.
11. For the following circuits, write the Verilog Code, verify using Test Bench,
and then synthesize with the given Constraints: i) T Flip-flop, ii) 4-bit CO1, CO4
Synchronous counter.
12. Write the Verilog Code for Sequence detector using Mealy and Moore, verify
using Test Bench, and then synthesize with the given Constraints. CO1, CO4
Assessment Pattern:
CIE-Continuous Internal Evaluation Lab (50 Marks):

Blooms levels CIE –LAB (50 Marks)

Assessment on Performance Internal lab examination
(30Marks) (20 Marks)
Remember - -
Understand 05 -
Apply 10 10
Analyze 10 05
Evaluate 05 05
Create - -

SEE – Semester End Examination Lab (50 Marks):

Bloom’s Taxonomy External Lab

Examination
(50 Marks)
Remember -
Understand 05
Apply 20
Analyze 15
Evaluate 10
Create -
 LABORATORY RULES

1. Follow proper dress code in laboratory.

2. Always be silent in the laboratory.

3. Unless and until needed, do not boot any system in the lab.

4. Don't move or shift the C.P.U. from its position.

5. The use of cell phones is prohibited in the lab.

6. Users are strictly prohibited from modifying or deleting any important files and install any software or settings in
the computer.

7. If any problem arises, please bring the same to the notice of lab in-charge.

8. Before leaving the lab, users must close all programs positively and keep the desktop blank.

*************************
 GUIDELINES FOR LABORATORY NOTEBOOK

The laboratory notebook is a record of all work pertaining to the experiment. This record should be
sufficiently complete so that you or anyone else of similar technical background can duplicate the
experiment and data by simply following your laboratory notebook. Record everything directly into
the notebook during the experiment. Do not trust your memory to fill in the details at a later time.
Organization in your notebook is important. Descriptive headings should be used to separate and
identify the various parts of the experiment. Record data in chronological order.

1. Heading: The experiment identification (number) should be at the top of each page.

2. Aim: A brief but complete statement of what you intend to find out or verify in the experiment
should be at the beginning of each experiment.

3. Diagram: A circuit diagram should be drawn and labelled so that the actual experiment circuitry
could be easily duplicated at any time in the future. Be especially careful to record all circuit changes
made during the experiment.

4. Equipment List: List those items of equipment which have a direct effect on the accuracy of the
data. It may be necessary later to locate specific items of equipment for rechecks if discrepancies
develop in the results.

5. Procedure: In general, lengthy explanations of procedures are unnecessary. Be brief. Short

commentaries alongside the corresponding data may be used. Keep in mind the fact that the
experiment must be reproducible from the information given in your notebook.

6. Data: Think carefully about what data is required and prepare suitable data tables. Record instrument
readings directly. Do not use calculated results in place of direct data; however, calculated results
may be recorded in the same table with the direct data. Data tables should be clearly identified and
each data column labelled and headed by the proper units of measure.

7. Calculations: Not always necessary but equations and sample calculations are often given to
illustrate the treatment of the experimental data in obtaining the results.

8. Graphs: Graphs are used to present large amounts of data in a concise visual form. Data to be
presented in graphical form should be plotted in the laboratory so that any questionable data points
can be checked while the experiment is still set up. The grid lines in the notebook can be used for
most graphs. If special graph paper is required, affix the graph permanently into the notebook. Give
all graphs a short descriptive title. Label and scale the axes. Use units of measure. Label each curve
if more than one on a graph.
Results: The results should be presented in a form which makes the interpretation easy. Tables are
generally used for small amounts of results.
 TABLE OF CONTENT
[List of Experiments]

S.No. List of experiments

Cycle - 1

1. Draw the schematic of CMOS Inverter for the given specifications, and verify using
Transient and DC Analyses.
Draw the schematic of the following circuits for the given specifications, and verify
2.
using Transient and DC Analyses: i) 2-input CMOS NAND gate, ii) 2-input CMOS
NOR gate.
3. Draw the schematic of transmission gate for the given specifications, and verify using Transient
and DC Analyses.
4. Draw the schematic of the following amplifiers for the given specifications, and verify the
same using Transient, DC and AC Analyses: i) Common Source amplifier, ii) Common Drain
amplifier.
5. Draw the layout of the CMOS Inverter and perform physical verification using DRC, ERC and
LVS. Extract RC and back-annotate the same and verify the Design.
6. Draw the layout of the following circuits and perform physical verification using DRC, ERC
and LVS. Extract RC and back-annotate the same and verify the Design: i) 2-input CMOS
NAND gate ii) 2-input CMOS NOR gate.
Cycle - 2

7. For the following circuits, write the switch level Verilog Code, and verify using Test Bench:
i) CMOS inverter, ii) 2-input CMOS NAND and NOR gates.
8. For the following circuits, write the switch level Verilog Code and verify using Test Bench: i)
2-input EXOR gate using CMOS logic, ii) 2-input EXOR gate using PTL.
9. Synthesize the following circuits using the gate level Verilog Code, with the given
Constraints: i) CMOS inverter, ii) 2-input CMOS NAND and NOR gates.

10. For the following circuits, write the Verilog Code, verify using Test Bench, and
then synthesize with the given Constraints: i) 4-bit Parallel adder ii) D Flip-flop.
For the following circuits, write the Verilog Code, verify using Test Bench, and
11.
then synthesize with the given Constraints: i) T Flip-flop, ii) 4-bit Synchronous
counter.

12. Write the Verilog Code for Sequence detector using Mealy and Moore, verify using
Test Bench, and then synthesize with the given Constraints.
CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT-1

Draw the schematic of i) CMOS Inverter for the given specifications and
verify using Transient and DC Analyses.

Aim: To simulate the schematic of the CMOS inverter, and then to perform the
physical verification for the layout of the same.
Theory: Complementary MOSFET (CMOS) technology is widely used today to form circuits in
numerous and varied applications. Today’s computers CPUs and cell phones make use of CMOS
due to several key advantages. CMOS offers low power dissipation, relatively high speed, high noise
margins in both states, and will operate over a wide range of source and input voltages. CMOS
circuit is composed of two MOSFETs. The top FET (MP) is a PMOS type device while the bottom
FET (MN) is an NMOS type. Both gates are connected to the input line. The output line connects to
the drains of both FETs. The CMOS circuit functions as an inverter by noting that when VIN is five
volts, VOUT is zero, and vice versa. Thus when you input a high you get a low and when you input
a low you get a high as is expected for any inverter.

Procedure: The three initial steps before simulation are: schematic entry, symbol entry and test
circuit entry. The procedures are as detailed below –

DESIGN ENTRY:

1. In the schematic editor window, for the addition of instances, press “i”. This will open the
“Add Instance” window. In that window, browse for the library gpdk180, select the cell pmos
and then select the view symbol. Click on close.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

2. The properties of the selected instance are displayed in the “Add Instance” window. There is
no need to modify any properties for this particular experiment. Click on Hide.

3. The pmos symbol will move along with the cursor. Place it in the top mid-position, left-click
and then press Esc.

4. Similarly place nmos device, and then press Esc.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

5. Now, press “w” for placing wire, click on the respective nodes and connect them through
wire. Place the input and output wires as well. Complete the substrate connections also.

6. After pressing Esc, press “p” for adding pins to the schematic diagram. In the “Add Pin”
window, enter the name of the pin (e.g.: in), and ensure its direction as input.

7. Click on Hide, and place the pin at the input. Later press Esc.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

8. Similarly, place the output pin with name “out” and direction output.

9. Complete the schematic by placing the instances “vdd” and “gnd”, which are in the analogLib
library. Finally, click on “check & save” icon and observe the errors in the virtuoso console. In
the schematic window, the errors will be highlighted with yellow boxes. Move those boxes,
correct the errors, and click on “check & save”. Correct all the errors that are reported.

10. After the schematic entry is finished, a symbol for the design has to be created. For this
purpose, click on Create and follow the procedure –

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Create → Cellview → From Cellview

The name comes by default, along with the other options. Click on OK.

11. Another window opens, which shows the input and output pin configurations. Click on OK.

12. A symbol editor window opens up with the default symbol.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

13. The default symbol can be deleted and the symbol as per our convention can be created. For this
purpose, click on the green colored edge of the symbol. Now the color of the selected partchanges
into magenta. Press Delete and click again on the edge. The default green box gets deleted, and a
new symbol can be created. Now press Esc to come out of the delete mode.

14. On the pulldown menu, Select Create → Shape → Line and click on the editor window.
Usethe mouse to create the shape of a triangle. Alternatively, you can select Create →
Shape →Polygon as well. Use “right click” for making the line slant.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

15. After the triangle is complete, select Create → Shape → Circle, and then bring the cursor in
front of the triangle, and click once. Release the finger and move the mouse. After the circle
is generated, click once again to place it.

16. Now, click on the output wire and drag it in front of the circle. Similarly, join the output pin
to the wire. Later, select Create → Selection box and click on Automatic. The tool will adjust
the selection box around the created symbol automatically. You can similarly select and drag
the port names to the respective places. Finally, “check & save” and observe the errors.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

17. After the schematic and symbol entries, both the editor windows can be closed. Now for creating
a test circuit, create a new cell view from the virtuoso console, and give the name as “inverter
_test”. When the editor window opens, press “i”, browse for your library and select the inverter
symbol which was created earlier. Place it in the middle of the screen.
To ensure that the symbol is loaded correctly, you can click on the symbol and then press “Shift
E”. The schematic editor will move one level down, and the inverter’s circuit entered earlier will
be displayed on the screen. To come back to the symbol, press “Ctrl E”; the symbol will be
displayed back. Press Esc to unselect the symbol.

18. Place wires at the input and output, and place an output pin as well. These wires are needed
during simulation, to plot the voltage waveforms

19. Press “i”, browse analogLib library and select “vpulse” and its symbol.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

20. In the property window, enter Voltage1 as 0 and Voltage2 as 1.8. Similarly enter Period as
20n and Pulse width as 10n, without the space in between. No need to enter the units; they
appear automatically. Place the “vpulse” at the input wire. Connect “gnd” at the other end.

21. Similarly, browse for the instance “vdc”, and enter its DC voltage as 1.8.
9

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

22. Place “vdc” at the front, and connect “vdd” and “gnd” accordingly. Finally “check & save”.
The test circuit is complete now, and ready to be simulated.

Note: The library gpdk180 contains the technology dependent components (180nm), and the library
analogLib contains the technology independent components.

Whenever a component needs to be selected, place the cursor on the component and click on it. The
selected component’s boundary turns into magenta color. Now the properties of the component can
be verified by pressing “q”, after which the property window opens.

To zoom a particular portion of the screen, right click, hold, and move the mouse. A yellow colored
boundary will be drawn on the screen. When the finger is released, the highlighted portion gets
zoomed. To come back to the original screen, press “f”. Alternatively, “Ctrl Z” and “Shift Z” can be
used, to zoom in and zoom out.

10

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

After the symbol is entered, Shift and E can be used together to move one level down, to view
theschematic diagram. Later, Ctrl and E can be used together to move one level up, to the symbol.

The hot key functions that are used during design entry are summarized as follows –

Hotkey Function

i Instance

w Wire

p Pin

m Stretch

q Property

r Rotate

u Undo

c Copy

f Fit to screen

Esc Exit

SIMULATION

1. In the test circuit’s editor window, click on Launch → ADE L. A new window will open.

2. Click on Analyses → Choose. A new window will open, in which select “tran”. Fill the stop time as
100n, and select liberal. Later, click on Apply.
11

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

3. Now select “dc” on the Choosing Analyses window, and click on Save DC Operating Point. Click on
the Component Parameter. A Select Component option will pop up.

4. Double click on Select Component. The ADE window gets minimized, and the schematic is shown.
Click on the component “vpulse”. In the new window that opens up, click on the top most parameter
dc and then click on OK.

12

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

5. Ensure that the component name and parameter name are updated. Now in the Sweep range, enter 0
and 1.8 in the Start and Stop options respectively. Later, click on Apply.

6. In the ADE window, ensure that the Analyses fields are updated for tran and dc.

7. Now to select the stimulus and response points, in the ADE window, click on Outputs → To be plotted
→ Select on Schematic. In the schematic window, click on input and output wires. These wires will
become dotted lines when selected. Later, press Esc.

8. In the ADE window, check that the Outputs fields are updated. Now click on Simulation → Netlist and
Run. The waveform window will open and the simulation results are displayed. Transient
13

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

response is displayed on the left side and DC response on the right. Click on the transient response
waveform and then click on the fourth icon at the top (Strip chart mode). The input and output
waveforms are displayed separately. You can “right click” on each waveform, and then edit the
properties of the display such as color and appearance. Similarly, the transfer characteristics can be
observed at the right hand side.

Result:

14

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT 2

Draw the schematic of i) 2-input CMOS NAND gate, ii) 2-input CMOS NOR gate for the given
specifications, and verify using Transient and DC Analyses

INPUT CMOS NAND GATE

Aim : To simulate the schematic diagrams of the NAND gate, and then to perform the physical
verification for the layouts of the same.

Theory: A CMOS NAND gate circuit uses four MOSFETs just like the NOR gate, except that its transistors
are differently arranged. The NAND gate uses two series-connected sinking transistorsand two parallel-
connected sourcing transistors.

Circuits Diagrams:

1. For the schematic entry, select pmos device from gpdk180 library, Place the wires
forconnection.

2. Place “vdd” and “gnd”. Later, place the input pins for A and B, and output pin for Vout.
Clickon “check & save” and correct the errors, if any.

1. Create the symbol for the schematic, using create cellview from cellview , the
defaultsymbol itself can be used.

15

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Close the editor windows, and create a new schematic in the virtuoso console, for the test circuit.
Inthe test circuit, retrieve the symbol from your library, and then place “vpulse” from the
analogLib library for the input signal, with the attributes entered as –

2. In the property window, enter Voltage1 as 0 and Voltage2 as 1.8. Similarly enter Period
as40n and Pulse width as 20n, without the space in between. No need to enter the units;
theyappear automatically. Place the “vpulse” at the input wire. Connect “gnd” at the other
end

3. Same step follow for other one where enter Voltage1 as 0 and Voltage2 as 1.8. Similarly
enterPeriod as 20n and Pulse width as 10n, then change vdc parameter as voltage 1.8 place
vdd and gnd at end

Press q for check the parameters of the components.

SIMULATION

In the test circuit’s editor window, click on Launch → ADE L. A new window will open.

Click on Analyses → Choose. A new window will open, in which select “tran”. Fill the stop time as 100n,
and select liberal. Later, click on Apply. Ensure analysis window updated. Now to select the stimulus and
response points, in the ADE window, click on Outputs → to be plotted → Select on Schematic. In the
schematic window, click on input and output wires. These wires will become dotted lines when selected.
Later, press Esc.
16

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Result:

17

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT3

Draw the schematic of Transmission Gate for the given specifications and verify using
Transient and DC Analyses.

Aim: To simulate the schematic of the Transmission Gate, and then to perform the physical
verification for the layout of the same.

Theory: A transmission gate is made up of two field-effect transistors. The two transistors, an n-
channel MOSFET and a p-channel MOSFET, are connected in parallel with this, however, only the
drain and source terminals of the two transistors are connected together. Their gate terminals are
connected to each other by a NOT gate (inverter), to form the control terminal. Transmission gates
are used in order to implement electronic switches and analog multiplexers.

Circuits Diagrams:

1. For the schematic entry, select pmos and nmos device from gpdk180 library, Place the wires
forconnection.

2. Later, place the input pins for A and B, and output pin for Vout. Click on “check & save”
andcorrect the errors, if any.

3. Create the symbol for the schematic, using create cellview from cellview , the default
symbol itselfcan be used.
18

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Close the editor windows, and create a new schematic in the virtuoso console, for the test circuit. Inthe
test circuit, retrieve the symbol from your library, and then place “vpulse” from the analogLib library
for the input signal, with the attributes entered appropriately.

Press q for check the parameters of the components.

SIMULATION:

In the test circuit’s editor window, click on Launch → ADE L. A new window will open.

Click on Analyses → Choose. A new window will open, in which select “tran”. Fill the stop time as
100n, and select liberal. Later, click on Apply. Ensure analysis window updated.

Now to select the stimulus and response points, in the ADE window, click on Outputs → to be
plotted → Select on Schematic. In the schematic window, click on input and output wires. These
wires will become dotted lines when selected. Later, press Esc.

19

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Result:

20

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT-4
Draw the schematic of Common source amplifier and Common drain amplifier for the given
specifications, and verify using Transient, DC and AC Analyses.

Circuit diagrams:

Procedure:

a) COMMON SOURCE AMPLIFIER:

For the schematic entry, select pmos device from gpdk180 library, and edit the properties as Length = 1
micron and Width = 50 microns. (type “u” for micron). Similarly, place the nmosdevice with Length = 1
micron and Width = 20 microns. Place the wires for connection.

2 Place “vdd” and “vss”. Later, place the input pins for Vbias and Vin, and output pin for Vout.
Click on “check & save” and correct the errors, if any.

21

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

3 Create the symbol for the schematic; the default symbol itself can be used.

4 Close the editor windows, and create a new schematic in the virtuoso console, for the test
circuit. In the test circuit, retrieve the symbol from your library, and then place “vsin” from
the analogLib library for the input signal, with the attributes entered as –

AC magnitude = 1mV, Amplitude = 5mV and Frequency = 1KHz. (Don’t enter the units).

The AC magnitude is used for ac analysis, and the Amplitude is used for transient analysis.
Place a wire in between vsin and vin.

5 Now, place “vdc” for the the biasing voltage, with DC voltage as -0.9V. Place two more
instances of “vdc”, to be utilized for the attributes of vdd and vss, and edit their values as 2.5V
and -2.5V respectively. Connect the respective vdd and vss symbols, along with gnd. Finally,
place a wire and pin for the output.

22
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE
CMOS VLSI DESIGN LABORATORY 22EEL52

6.After saving, launch ADE-L and enter the analyses requirements, as per the procedures
givenin the previous experiment. For transient analysis, as the input signal is of period 1ms,
enter the Stop Time as 10m. For dc analysis, Select Component “vsin”, select dc, and enter
the Sweep Range as Start -2.5 and Stop 2.5. (Units will appear automatically). As this
particular experiment is on amplifiers, ac analysis is also required for finding the bandwidth.
Hence, after tran and dc, click on ac, and enter the Sweep Range of Frequency as 100 Hz till
1GHz. Select the Sweep Type as Logarithmic and enter the Points per Decade as 20.

6 Finally, select the wires on the schematic for plotting the outputs, and click on the PLAY
iconin the ADE window, for netlist & run. The output will appear, and the waveforms can be
edited in different colors, for better viewing.

In the Transient Response, for measuring the amplitude, press “d”. Now two delta cursors are
made available on the screen, one with red pointer and the other with green pointer. Move one
cursor to the positive peak of the waveform and the other cursor to the negative peak. The
values (time & amplitude) corresponding to the cursor positions are displayed at the bottom,
red one first and green one next. The difference in y-values gives the peak-to-peak amplitude.

(The input amplitude in this case is 10 mVpp, as the amplitude given was 5mV). The dx | dy
is also displayed at the right side, and the dy value represents the amplitude.

23

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

For measuring the bandwidth, move the trace cursor in the AC Response to the point which
corresponds to 0.707 Vmax, and the display indicates the frequency, which is the
bandwidthcorresponding to the -3dB gain.

The DC Response can be observed for the quiescent operation of the amplifier.

7 The gain and phase response can be obtained separately, by following the procedure in the
ADE window as: Results → Direct plot → AC Gain & Phase. In the schematic window,
click on the output wire first and then on the input wire. Later, press Esc. The phase and gain
curves are displayed in a separate window. Click on the output and then on Strip chart mode,
and observe the output. The gain is displayed in dB, and hence, to check the bandwidth of
theamplifier, the trace cursor can be moved to the -3dB position on the gain curve.

24

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52
b) COMMON DRAIN AMPLIFIER:

1. The procedures remain similar to the previous experiment. Enter the schematic diagram with
the upper NMOS device dimensions as Length = 1 micron & Width = 50 microns, and the
lower NMOS device dimensions as Length = 1 micron & Width = 10 microns.

It is not mandatory that the “vdd” and “vss” symbols from the analogLib library have to be
used directly. They can be declared as pins, and their voltages can be directly specified in
thetest circuit. This alternative method is followed in this experiment, as shown in the circuit
diagram below. Complete the other connections as per the circuit diagram, and click on
“check & save” and correct the errors, if any.

2. During the symbol generation, the vdd pin can be placed as the top pin and the vss
pin can beplaced as the bottom pin.

25

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

3. The symbol that is generated can be used directly. Click on “check & save”.

4. The test circuit is similar to the common source amplifier except that “vdc” can be
directly connected to the vdd and vss pins, and their voltages can be edited respectively.
The biasingvoltage for the common drain amplifier is -1.8V.

5. Perform the simulation on the test circuit, and verify the gain and phase. As the circuit is
similar to the Emitter follower circuit of BJT, there will be no voltage gain as such.

26

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Result:

27

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT- 5
Draw the layout of CMOS Inverter and perform physical verification using DRC, ERC
and LVS and Extract RC.

LAYOUT:

1. For preparing the layout of the inverter, all the other windows can be closed, except for the
virtuoso console. In the console, open the schematic of the inverter and click on Launch →
Layout XL. In the Startup Option, click on OK.

2. In the New File option, the tool selects the view as layout by default. Click on OK.

3. The tool opens the LSW and the Layout suite.

28

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

4. Maximize the layout suite and click on Connectivity → Generate → All from Source. A
Generate Layout window will open, with default attributes. Click on OK.

5. Press “Shift F” to see all the layers within the default layout. Hold the “right click” and move the
mouse to zoom a selected portion, and observe the layout carefully. The color details are – Orange
border: n-well, Red border: p-diffusion’s boundary, Yellow border: n-diffusion’s boundary,
Green: diffusion, Rose: polysilicon, Yellow square: contact cut, Blue: metal1.

29

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

6. The layout can be moved either vertically or horizontally, not diagonally.(“s” is for stretch, in the
layout suite). The selected edge will turn into magenta color. Now release the finger and move
the mouse till the desired area, and click again. Later, press Esc.

7. After placing the devices, zoom the space in between the transistors. In the LSW, select Poly.
Now in the layout suite, press “p”, place the mouse at the middle of the gate’s lower contact of
pmos device, and click once. (“p” is for path, in the layout suite). Release the finger and move
the mouse downwards. The poly path will move along with the mouse. Move the mouse until the
gate area of the nmos device gets overlapped. Bring the cursor exactly to the middle of the path
and double click. The poly path between the gates gets realized. The area can be zoomed further,
and the devices can be moved, for the exact overlapping of the poly layers.

8. In the LSW, select Metal1. Using the same procedure, draw the paths for “vdd” at the top and
“gnd” at the bottom. Later, using the same metal path, connect the source of pmos device to “vdd”
and that of nmos device to “gnd”. Finally, connect both the drains for the output path.

30

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

9. Place the input pin in front of the poly and connect through a poly path.

10. Now, for connecting the input metal pin to the poly path, a via needs to be placed. Hence, in the
layout suite click Create → Via. In the Via Definition pull-down menu, select the via
M1_POLY1. Click on Hide, and place the via on the input pin. Press Esc.

31

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

11. Similarly, for the substrate connections, select the via M1_NWELL and place it touching the n-
well, and connect it to “vdd” through a metal path. Later, place the via M1_PSUB on the “vss”
path, for the substrate connection of nmos device; the Black background itself indicates the p-
substrate. (p-device resides on n-well and n-device resides directly on p-substrate).

Physical Verification: DRC Check

1. As the layout is now complete, its verification can be performed. In the layout suite, click
on Assura → Run DRC. Verify the output. If there are errors, the tool will highlight those
areasin White color. The errors will be displayed in the ELW, and the location of each error
can beknown, by selecting the error in ELW, and then clicking on the arrow mark available
in ELW.Correct those errors and rerun DRC.
2. The Run Assura DRC window will pop up. Now enable View Rule files, select the
technology like gpdk180, 90 or 45 and also provide the Run Name while running the DRC
as shown in the below figure
3. Click on Ok and new Progress File Window pop up so click on Watch log file so log file
32

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52
will appear.
4. If there are any DRC errors exist in the design View Layer Window (VLW) the Error Layer
Window (ELW) appears by double clicking on the errors in ELW the errors will be
highlighted in the layout window.Re-correct all the errors and re-run the DRC again.
5. If there are no DRC errors it will pop up with the window showing no DRC errors.

LVS Check
1. After the DRC check, click on Assura → Run LVS, Below window will pop up Select the
Technology File and specify the run name make all the necessary changes as shown in the figure
and hit on OK.and verify the output. Correct the errors.

33

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

If Layout and schematic matches one window will pop and notify schematic and layout match as shown
in the figure.

If the schematic and layout do not matches, a form informs that the LVS completed successfully and
asks if you want to see the results of this run. Click Yes in the form. LVS debug form appears, and you
are redirected to LVS debug environment. In the LVS debug form you can find the details of mismatches
and you need to correct all those mismatches and Re – run the LVS till you will be able to match the the
schematic and layout.

Running Quantus QRC:

1. After the LVS check, click on Assura →Run Quantus QRC for RC extraction.
2. Click on setup and set the output to Extracted View and select the Technology as shown in the below
image.
3. Click on Extraction from the top of the window and give the Ref Node as gnd! And also select the
Extraction Type to RC .

34

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

After the RCX is run, informs you that Quantus QRC run
1. completed successfully or not.the output is saved in your library as av_extracted. In the virtuoso
console, open the “inverter” file with view as av_extracted, and observe the output. The layout
can be enlarged and the parasitic components can be observed. Each components value can be
checked, by selecting the component and pressing “q”.

35

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

If the parasitic component values are beyond the limits, then the layout can be optimized in the layout
suite, for the reduction of the parasitic component values; later on, the layout canbe back-annotated with
the existing parasitic components, and simulation can be performed,for verifying the output.

Result:

36

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT- 6

Also draw the layout of

i) 2-input CMOS NAND gate, ii) 2-input CMOS NOR gate, and perform
physicalverification using DRC, ERC and LVS. And Extract RC.

LAYOUT: NAND GATE

1. For preparing the layout of the inverter, all the other windows can be closed, except for
the virtuoso console. In the console, open the schematic of the inverter and click on
Launch →Layout XL. In the Startup Option, click on OK.
2. In the New File option, the tool selects the view as layout by default. Click on OK.
3. The tool opens the LSW and the Layout suite.
4. Maximize the layout suite and click on Connectivity → Generate → All from Source. A
Generate Layout window will open, with default attributes. Click on OK.
5. The layout suite displays a cyan colored box in the first quadrant, which is the Photo-
Resist boundary. In addition, in the fourth quadrant, the default layouts of pmos and nmos
transistorsare displayed, along with four blue squares, which are the nodes - vdd, gnd,
input & output.
6. Start doing layout design,
7. As the layout is now complete, its verification can be performed. In the layout suite, click
on Assura → Run DRC. Verify the output. If there are errors, the tool will highlight those
areasin White color. The errors will be displayed in the ELW, and the location of each
error can beknown, by selecting the error in ELW, and then clicking on the arrow mark
available in ELW.Correct those errors and rerun DRC.

37

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

8. After the DRC check, click on Assura → Run LVS, and verify the output. Correct the errors.

9. After the DRC check, click on Assura → Run LVS, and verify the output. Correct the errors.

10. After the LVS check, click on Assura → Run RCX. Click OK on the form that appears.

11. After the RCX is run, the output is saved in your library as av_extracted. In the virtuoso
console, open the “inverter” file with view as av_extracted, and observe the output. The layout
can be enlarged and the parasitic components can be observed. Each components valuecan be
checked, by selecting the component and pressing “q”.

38

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

12. If the parasitic component values are beyond the limits, then the layout can be optimized in the
layout suite, for the reduction of the parasitic component values; later on, the layout canbe back-
annotated with the existing parasitic components, and simulation can be performed, for
verifying the output.

39

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

2- I/P NOR GATE

LAYOUT:

1. For preparing the layout of the inverter, all the other windows can be closed, except for
thevirtuoso console. In the console, open the schematic of the inverter and click on
Launch →Layout XL. In the Startup Option, click on OK.

2. In the New File option, the tool selects the view as layout by default. Click on OK.

3. The tool opens the LSW and the Layout suite.

4. Maximize the layout suite and click on Connectivity → Generate → All from Source. A
Generate Layout window will open, with default attributes. Click on OK.

5. The layout suite displays a cyan colored box in the first quadrant, which is the Photo-
Resist boundary. In addition, in the fourth quadrant, the default layouts of pmos and nmos
transistorsare displayed, along with four blue squares, which are the nodes - vdd, gnd,
input & output.

Start doing layout design,

6. As the layout is now complete, its verification can be performed. In the layout suite, click
on Assura → Run DRC. Verify the output. If there are errors, the tool will highlight those
areasin White color. The errors will be displayed in the ELW, and the location of each
error can beknown, by selecting the error in ELW, and then clicking on the arrow mark
available in ELW.Correct those errors and rerun DRC.

7. After the DRC check, click on Assura → Run LVS, and verify the output. Correct the errors.

40

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

8. After the DRC check, click on Assura → Run LVS, and verify the output. Correct the errors.

9. After the LVS check, click on Assura → Run RCX. Click OK on the form that appears.

10. After the RCX is run, the output is saved in your library as av_extracted. In the virtuoso
console, open the “inverter” file with view as av_extracted, and observe the output. The layout
can be enlarged and the parasitic components can be observed. Each components valuecan be
checked, by selecting the component and pressing “q”.

11. If the parasitic component values are beyond the limits, then the layout can be optimized
in the layout suite, for the reduction of the parasitic component values; later on, the
layout canbe back-annotated with the existing parasitic components, and simulation can
be performed,for verifying the output.

Result:
41

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT- 7

For the following circuits, write the switch level Verilog Code, and verify using Test Bench:

i) CMOS inverter, ii) 2-input CMOS NAND and NOR gates

Theory: transistor level modeling is referred to model in hardware structures using transistor
models with analog input and output signal values. At this level, a hardware component is
described at the transistor level, but transistors only exhibit digital behavior and their input, and
output signal values are only limited to digital values. At the switch level, transistors behave as
on-off switches- Verilog uses a 4 value logic value system, so Verilog switch input and output
signals can take any of the four 0, 1, Z, and X logic values.

In Verilog nmos and pmos switches are instantiated as shown in

below,nmos n1(out, data, control); // instantiate a nmos switch

pmos p1(out, data, control); // instantiate a pmos switch

Design Files: Main design module, Test bench module and Constraints file.

i) Main Design Module: Inverter.v

`timescale 1 ns / 1 ns
//Define our own
Invertermodule
inverter (out, in);
// Declarations of I/O, Power and Ground
output out;
input in;
supply1
pwr;
supply0
gnd;
// Instantiate pmos and nmos
switchespmos (out, pwr, in);
nmos (out,
gnd, in);
endmodule

II Test Bench Module: Inverter_test.v

`timescale 1 ns / 1 ns
// Testbench for Inverter Module
module inv_test;
wire out;
reg in;
// Instantiate inverter Module
Inverter i1 (out,in);
//Apply Stimulus 42

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52
Initial
Begin
In == 1’b0;#10;

In == 1’b1;#10;

In == 1’bx;#10;

In == 1’bz;#10;
End
endmodule

Procedure:
Initially, follow all the steps mentioned in the previous section. The rest of the steps are as follows –

1. After invoking the Simvision tool with the command ncsim modulename –gui, two
windows will be opened: one is the Simvision Console and the other is the Design
Browser window ofthe tool, as shown in the snap shot –

2 As the next step, you need to click on the module name on the left side of the Design
Browserwindow. As soon as you click, you will see all the port names displayed in the
right side of the Design Browser window.

43

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

3 Then select all the ports for which you want to see the waveforms.

4 Next, click the waveform icon on the right hand side corner of the Design Browser
window.Now the waveform window will open.

5 Click the play button on the waveform window to run the simulation. The waveforms
will begenerated as shown –

44

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

6 For synthesis, follow the steps that are mentioned previously. After synthesis, the
synthesiswindow will be shown as follows –

ii) NAND GATE:

Main Design Module: Nandg.v

`timescale 1 ns / 1 ns
//Define our own Nand
Gate module nandgate
(out, in1, in2);
// Declarations of I/O, Power and Ground Lines 45

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

output out;
input in1, in2;
supply1 pwr;
supply0 gnd;
wire contact;

// Instantiate pmos and nmos switches

pmos (out, pwr, in1);
pmos (out, pwr, in2);
nmos (out, contact, in1)
;nmos (contact, gnd, in2);

endmodule

ii) NOR GATE

Main Design Module: Norg.v

`timescale 1 ns / 1 ns
//Define our own Nor Gate
module norgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;
supply1 pwr;
supply0 gnd;

// Declaration of Wire
wire contact;
// Instantiate pmos and nmos switches

pmos (contact, pwr, in1);

pmos (out, contact, in2);
nmos (out, gnd, in1);
nmos (out, gnd, in2);

endmodule

Test Bench Module: Nor_test.v

`timescale 1 ns / 1 ns
// Testbench for Nor Gate Module
module nor_test;
wire out;
reg in1, in2;

Instantiate Nor Gate Module

norgate n1 (out, in1, in2);
// Apply Stimulus
initial

46

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52
begin

in1 = 1'b0; in2 = 1'b0; #10;

in1 = 1'b0; in2 = 1'b1; #10;
in1 = 1'b1; in2 = 1'b0; #10;
in1 = 1'b1; in2 = 1'b1; #10;

end

endmodule

Result:

47

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT- 8
2-input EXOR gate using CMOS logic, iv) 2-input EXOR gate using PTL

EXOR GATE
Schematic diagram (using CMOS logic)

Main Design Module: Exorg.v

`timescale 1 ns / 1 ns
module xorgate (out, a,b);
output out;
input a, b;
supply1 pwr;
supply0 gnd;

// Declaration of Wire
wire w1,w2,w3,w4;
pmos p1(w2, pwr, ~b);

pmos p2(out,w2,,a);
pmos p3(w2, pwr, ~b);
pmos p4(out,w2,,a);

nmos n1(out, w4, b);

nmos n2 (out, w3, ~b);
nmos n3 (w4, gnd,a);
nmos n4 (w3,gnd,~a);

endmodule

48

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

Test Bench Module: Exor_test.v

Timescale 1ns/1ns
//Testbench for Xor Module
Module xor test;
Wire out;
Reg a,b;
Xorgate x1 (out a b);
Initial
Begin
a = 1'b0; b = 1'b0; #10;
a = 1'b0; b = 1'b1; #10;
a = 1'b1; b = 1'b0; #10;
a = 1'b1; b = 1'b1; #10;
end
endmodule

Result:

49

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT- 9
Synthesize the following circuits using the gate level Verilog Code, with the given Constraints: i)
CMOS inverter, ii) 2-input CMOS NAND and NOR gates.

i) CMOS inverter, ii) 2-input CMOS NAND and NOR gates

Aim: To compile and to simulate the Verilog code for an inverter, and then to synthesize the
same forthe given constraints.

Theory: In Gate level model, the module is implemented in terms of logic gates and
interconnections between these gates. Designer should know the gate-level diagram of the design.
In general, gate-level modeling is used for implementing lowest level modules in a design like,
full- adder, multiplexers, etc. Verilog HDL has gate primitives for all basic gates. Gate primitives
are predefined in Verilog, which are ready to use. They are instantiated like modules. There are
two classes of gate primitives: Multiple input gate primitives and Single input gate primitives.
Multiple input gate primitives include and, nand, or, nor, xor, and xnor. These can have multiple
inputs and a single output. They are instantiated as follows:

// Two input AND

gate. and and_1

(out, in0, in1);

// Three input NAND gate.

nand nand_1 (out, in0, in1, in2);

Design Files: Main design module, Test bench module and Constraints file.

I Main Design Module: Inverter.v

`timescale 1 ns / 1 ns

//Define our own Inverter

module inverter (out, in);
// Declarations of I/O, Power and Ground Lines
output out;
input in;

not n1(out,in);
endmodule

II Constraints file for Synthesis: Constraints_Inverter.g

set_input_delay -max 1.0 [get_ports "in"]

set_output_delay -max 1.0 [get_ports "out"]

50

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52
Procedure:

Initially, follow all the steps mentioned in the previous section. The rest of the steps are as follows –

1. After invoking the Simvision tool with the command ncsim modulename –gui, two
windows will be opened: one is the Simvision Console and the other is the Design
Browser window ofthe tool, as shown in the snap shot –

2. As the next step, you need to click on the module name on the left side of the Design
Browserwindow. As soon as you click, you will see all the port names displayed in the
right side of the Design Browser window.

3 Then select all the ports for which you want to see the waveforms.

51

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

4 Next, click the waveform icon on the right hand side corner of the Design Browser
window.Now the waveform window will open.

5 Click the play button on the waveform window to run the simulation. The waveforms will
begenerated as shown –

6 For synthesis, follow the steps that are mentioned previously. After synthesis, the
synthesiswindow will be shown as follows –

52

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

ii) 2 input NAND and NOR gates

Design Files: The main design modules and the respective test bench modules are given as
follows,in the order of – NAND, NOR

Note: The words nand, nor, xor and xnor are the gate primitives in Verilog, and hence, care
must betaken not to use these keywords as module names or file names.

I Main Design Module: Nandg.v

`timescale 1 ns / 1 ns

//Define our own Nand Gate

module nandgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;

nand n1(out,in1,in2);
endmodule

Constraints file for Synthesis:

Constraints_nand.gset_input_delay -max 1.0

[get_ports "in1"] set_input_delay -max 1.0

[get_ports "in2"] set_output_delay -max 1.0

[get_ports "out"]

53

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

NOR GATE

Main Design Module: Norg.v

`timescale 1 ns / 1 ns

//Define our own Nor Gate

module norgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;

nor n1(out,in1,in2);

endmodule

II Constraints file for Synthesis:

Constraints_nor.gset_input_delay -max 1.0

[get_ports "in1"] set_input_delay -max 1.0

[get_ports "in2"] set_output_delay -max 1.0

[get_ports "out"]

Result:

54

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT-10
For the following circuits, write the Verilog Code, verify using Test Bench, and then synthesize with
the given Constraints:

i) 4-bit Parallel adder, ii) D Flip-flop, iii) T Flip-flop, iv)4-bit Synchronous counter

i) 4-BIT PARALLEL ADDERS:

Aim: To compile and to simulate the Verilog code for parallel adders, and then to synthesize these
designs for the given constraints.

Theory: A n bit parallel adder requires n full adders to perform the operation. So for the two-bit
number, two adders are needed while for four bit number, four adders are needed and so on. Parallel
adders normally incorporate carry lookahead logic to ensure that carry propagation between subsequent
stages of addition does not limit addition speed.

Design Files: The main design modules and the respective test bench modules are given as follow 4
bit parallel adder.

I Main Design Module: Parallel_adder.v

module padder ( x, y, c_in, sum, c_out);

input [3:0] x, y;
input c_in;
output [3:0] sum;
output c_out;
wire c1, c2, c3;

fulladd stage0 (x[0], y[0], c_in, sum[0], c1);

fulladd stage1 (x[1], y[1], c1, sum[1], c2);
fulladd stage2 (x[2], y[2], c2, sum[2], c3);
fulladd stage3 (x[3], y[3], c3, sum[3], c_out);
endmodule

module fulladd (a, b, cin, s, cout);

input a, b, cin;

55

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

output s, cout;

assign s = a^b^cin;
assign cout =(a & b)|(b & cin)|(a & cin);
endmodule

II Test Bench Module: Parallel_adder_test.v

module padder_test ;
reg [3:0] x, y;
reg c_in;
wire [3:0] sum;
wire c_out;

padder a1 (x, y, c_in, sum, c_out);

initial
begin
x = 4'b0000; y= 4'b0000; c_in = 1'b0;
#20 x = 4'b1111; y = 4'b1010;
#40 x = 4'b0011; y = 4'b0100;
#40 x = 4'b1001; y = 4'b1011;
#50 $finish;
end
endmodule

Following is the simulation result snapshot for the parallel adder –

III Constraints file for Synthesis: Constraints_pa.g

56

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

set_input_delay -max 1.0 [get_ports "x"]

set_input_delay -max 1.0 [get_ports "y"]
set_input_delay -max 1.0 [get_ports "c_in"]
set_output_delay -max 1.0 [get_ports "sum"]
set_output_delay -max 1.0 [get_ports "c_out"]
Following is the synthesis result snapshot for the parallel adder –

When double-clicked inside the blocks shown, the circuit diagram of the full adder gets displayed –

57

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

ii) D Flip-flop

Aim: To compile and to simulate the Verilog code for the common flip-flops, and then to synthesize
those designs for the given constraints.

Theory : The D flip-flop is widely used. It is also known as a "data" or "delay" flip-flop. The D flip-
flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of
the clock). That captured value becomes the Q output. At other times, the output Q does not change.
The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

In T flip flop, If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input
is strobed. If the T input is low, the flip-flop holds the previous value.

Design Files: The main design modules and the respective test bench modules are given as follows,
in the order of – D, T. The compiler directives are not used in these modules, as the primitives are not
used in the design modules, and the timing is specified in the test bench modules.

D FLIP-FLOP

I Main Design Module: D_ff.v

module dff(q, qbar, d, clk, rst);

output q, qbar;
input clk, d, rst;
reg tq;

always @(posedge clk or posedge rst)

begin
if (rst)
tq <= 1'b0;
else

tq <= d;
end
assign q = tq;
assign qbar = ~ tq;
endmodule

II Test Bench Module: D_ff_test.v

module dff_test;
reg clk, d, rst;
wire q, qbar;
dff d1(q, qbar, d, clk, rst);
initial
clk = 1'b0 58

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

always
#10 clk = ~ clk;

initial
begin
rst = 1'b1;
d = 1'b0;
#15 rst = 1'b0;
#25 d = 1'b1;
#20 d = 1'b0;
#20 d = 1'b1;
end
initial

#110 $finish;
endmodule

Following is the simulation result snapshot for the D flip-flop –

III Constraints file for Synthesis: Constraints_D_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]
59
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE
CMOS VLSI DESIGN LABORATORY 22EEL52

set_clock_transition -fall 0.1 [get_clocks "clk"]

set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "d"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]

Following is the synthesis result snapshot for the D flip-flop –

60

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

EXPERIMENT- 11

For the following circuits, write the Verilog Code, verify using Test Bench, and then synthesize with the
given Constraints: i) T Flip-flop, ii) 4-bit Synchronous counter.
I) T FLIP-FLOP:

Main Design Module: T_ff.v

module tff(q, qbar, t, clk, rst);

output q, qbar;
input clk, t, rst;
reg tq;
always @(posedge clk or posedge rst)
begin

if (rst)
else begin

tq <= 1'b0;

if (t)

tq <= ~ tq;

end

end

assign q = tq; assign qbar = ~ tq;

endmodule

II Test Bench Module: T_ff_test.v

module T_ff_test;
reg clk, t, rst;
wire q, qbar;
tff t1(q, qbar, t, clk, rst);
initial
clk = 1'b0;
always
#10 clk = ~ clk;
initial
begin
61

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

rst = 1'b1; t = 1'b0;

#15 rst = 1'b0;
#25 t = 1'b1;
#300 t = 1'b0;
#100 t = 1'b1;
#200 rst = 1'b1;
end
initial
#800 $finish;
endmodule

Following is the simulation result snapshot for the T flip-flop –

62

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

III Constraints file for Synthesis: Constraints_T_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "t"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]

Following is the synthesis result snapshot for the T flip-flop –

iii) 4-BIT COUNTERS

Aim: To compile and to simulate the Verilog code for the 4-bit synchronous counters, and then to
synthesize those designs for the given constraints.

Theory: Synchronous Counter, the external clock signal is connected to the clock input of EVERY
individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously
(in parallel) at the same time giving a fixed time relationship. In other words, changes in the output
occur in “synchronisation” with the clock signal. A 4 bit synchronous counter counts sequentially on
every clock pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ).

Design Files: The main design modules and the respective test bench modules are given as follows,
in the order of synchronous counter, and then asynchronous counter

SYNCHRONOUS COUNTER

I Main Design Module: Sync_counter.v

module s_counter (clk, reset, count);

input wire clk, reset;
output reg [3:0] count;
63

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

always @(posedge clk)

if (reset)
count <= 4'b0000;
else
count <= count + 4'b0001;
endmodule

II Test Bench Module: Sync_counter_test.v

module s_counter_test ;
reg clk, reset;
wire [3:0] count;
initial
clk = 1'b0;
always
#5 clk = ~ clk;
s_counter m1 (clk, reset, count);
initial
begin
reset = 1'b0 ;
#15 reset =1'b1;
#30 reset =1'b0;
#220 reset =1'b1;
#15 $finish;
end
endmodule

Following is the simulation result snapshot for the synchronous counter –

64

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE

CMOS VLSI DESIGN LABORATORY 22EEL52

III Constraints file for Synthesis: Constraints_sc.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "clk"]
Following is the synthesis result snapshot for the synchronous counter –

When double-clicked inside the circular block, the logics get displayed as shown –

65

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, NHCE