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Deeep Final Lab Report

This document is a practical record book for Jarugu Gnana Deep, a student at Amrita School of Engineering, for the 2nd semester M.Tech in VLSI Design during the academic year 2024-2025. It includes the vision and mission of the ECE department, program educational objectives, course objectives, and a list of experiments conducted in the ASIC Design and FPGA Laboratory. The document also outlines discipline guidelines, course outcomes, and recommended tools and references for the program.

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2 views8 pages

Deeep Final Lab Report

This document is a practical record book for Jarugu Gnana Deep, a student at Amrita School of Engineering, for the 2nd semester M.Tech in VLSI Design during the academic year 2024-2025. It includes the vision and mission of the ECE department, program educational objectives, course objectives, and a list of experiments conducted in the ASIC Design and FPGA Laboratory. The document also outlines discipline guidelines, course outcomes, and recommended tools and references for the program.

Uploaded by

dhana.chem2011
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 8

AMRITA SCHOOL OF ENGINEERING

BENGALURU

PRACTICAL RECORD BOOK


Academic Year: 2024 – 2025 (Even Semester)

Department:ECE

Name: Jarugu Gnana Deep

Reg. No.: BL.EN.P2VLD24030

Semester: II

Branch: VLSI Design


AMRITA SCHOOL OF ENGINEERING

BENGALURU

Department:

Certified that this is the bonafide record of work done by

Mr/Ms. Jarugu Gnana Deep

Register no. BL.EN.P2VLD24030

in the ASIC Design and FPGA Laboratory (21VL683) of this

Institution, as prescribed by the Amrita Vishwa Vidyapeetham for the

2nd Semester MTech. during the academic year 2024-2025 (Even

Semester).

Faculty Incharge Chairperson

Submitted for the 2nd Semester M.Tech Examination of the Amrita

Vishwa Vidyapeetham conducted on 02/05/2025.

Examiner 1 Examiner 2
Vision and Mission of the Department
Vision
To provide a value-based learning environment for producing engineers with a blend oftechnical
skills, moral values and leadership qualities in the field of Electronics, Communication and
Computing channelized towards technological advancement to cater to the needs of the industry
and the society.
Mission

 Achieving excellence in teaching and learning with an emphasis on fundamental


knowledge and hands-on exposure to match the state-of-the-art intechnology.
 Providing an environment for core competency development and enhancing quality
research in emerging areas.
 Facilitating professional growth to the students for higher education and careerin
industry and academia.
 Imbibing the essence of human values, ethics and professional skills to sustainsocio-
economic development.

Programme Educational Objectives (PEOs)


PEO1 To create manpower in VLSI domain so as to attain mastery in applying VLSI
concepts to engineering problems in electronics, communication and computing so as
to meet the need of the industry, teaching, higher education or research.

PEO2 Creation of state-of-the-art expertise in the microelectronics domain to deal with


design, development, analysis, testing and evaluation of the critical aspects of
integrated circuits and its core concepts.

PEO3 To exhibit professional competence and leadership qualities with harmonious blend of
ethics leading to an integrated personality development.

Programme Outcomes (POs)


An ability to independently carry out research /investigation and development work to solve
PO1
practical problems.
PO2 An ability to write and present a substantial technical report/document.
An ability to demonstrate a degree of mastery over the area as per the specialization of the
PO3
program.
An ability to use modern tools for engineering design problems, analyze the performance
PO4
and optimize the systems-level approaches.
An ability to engage in independent and life-long learning in the context of technological
PO5
change and industrial demands.
Discipline and Caution

Do’s Don’ts

1. Be regular to the lab. 1. Do not write anything on the work


bench.
2. Maintain silence.
2. Do not turn on the system unnecessarily
3. Read the theory behind the experiment before
coming to the lab. 3. Do not use online sources to do
coding
4. Handle the equipment carefully and gently.
4. Do not copy the codes.

5. For simulation-based- experiment, save all files 5. Don’t leave the lab without taking
in a single folder. permission from the faculty.

6. Shut down the systems properly before leaving


the work bench.

7. Arrange the chairs/stools and equipment


properly before leaving the lab.
Course Objectives:
 To provide a background in using SPICE based simulator for MOS based circuits.
 To introduce VLSI design flow practically.
 To impart understanding of design, oriented towards synthesis.
Course Outcomes
CO1: Ability to characterize and understand the fundamentals of MOSFET device and circuits.
CO2: Ability to analyze VLSI design flow using EDA tools.
CO3: Ability to demonstrate a synthesized system in hardware using any design level entry.
CO – PO Mapping

CO-PO PO 1 PO 2 PO 3 PO 4 PO 5
Mapping
CO/PO
CO 1 3 2 2 3 3
CO 2 2 2 - 3 -
CO 3 2 2 - 2 -

Syllabus

1. MOSFET device and CMOS inverter characterization.


2. CMOS NAND/NOR characteristics
3. Active loaded amplifier designs
4. Two stage CMOS OP-Amps with and without compensation technique
5. Logic Synthesis of ALU
6. Static Timing Analysis of gate level netlist
7. Placement and Routing of a sub-system
8. Design a CS amplifier and obtain its layout diagram, perform RC extraction and post layout
simulation.
9. Implement ALU using FPGA
10. Implement an Up Counter using FPGA
11. Floating-Point Design Using the Vivado HLS Tool
12. Implementation of direct digital synthesizer using system generator

Recommended Tools
Xilinx Vivado, Xilinx HLS, Synopsys/Cadence

References
1. Sanjay Churiwala, Designing with Xilinx® FPGAs: Using Vivado, Springer 2017.
2. Sklyarov, V., Skliarova, I., Barkalov, A., Titarenko, L., Synthesis and Optimization of FPGA-
Based Systems, Springer 2014.
3. Coussy, Philippe, Morawiec, Adam (Eds.), High-Level Synthesis from Algorithm to Digital
Circuit, Springer 2008.
4. Software manuals of Cadence/Synopsys.
List of Experiments

Exp Aim of the Experiment CO


No.
1 To design and analyze the transient characteristics for basic logic gates using CMOS logic in the CO1

schematic.

2 To design and analyze the transient Characteristics for Full Adder and Ripple Carry Adder using CMOS CO1
logic in the schematic.
3 To design and analyze the transient, DC and AC Characteristics of CMOS differential amplifier. CO1

4 Two stage CMOS OP-Amps with and without compensation technique CO1

5 To design and analyze the transient, DC and AC Characteristics Common Source Amplifier design CO1
using pFET as Active load
6 Functional Simulation and Logic Synthesis of ALU CO2

7 Static Timing Analysis of gate level netlist of 4-bit full adder CO2

8 Placement and Routing of a ALU sub-system CO2

9 Implement ALU using FPGA CO3

10 Implement Up Counter using FPGA CO3

11 System level design project CO3


Table of Contents
Expt. Date
Name of Experiment Marks Signature
No.
10/01/25 To design and analyze the transient characteristics
1. for basic logic gates using CMOS logic in the
schematic.
15/1/25 To design and analyze the transient Characteristics
2. for Full Adder and Ripple Carry Adder using
CMOS logic in the schematic.
29/01/25 To design and analyze the transient, DC and AC
3. Characteristics of CMOS differential amplifier.

31/01/25 To design and analyze the transient, DC and AC


4. Characteristics Two stage CMOS OP-Amps with
and without compensation technique
06/02/25 To design and analyze the transient, DC and AC
5. Characteristics Common Source Amplifier design
using pFET as Active load
12/02/25
6. Functional Simulation and Logic Synthesis of ALU

11/04/25 Static Timing Analysis of gate level netlist of 4-bit


7.
full adder
01/04/25 Placement and Routing of a ALU sub-system
8.

05/04/25 Implement ALU using FPGA


9.

05/04/25 Implement Up Counter using FPGA


10.
2nd Sem, VLSI, M.Tech. ASIC and FPGA Laboratory Report

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