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Machine Instructions & Addressing Modes

The document provides an overview of machine instructions and addressing modes relevant for GATE preparation in digital circuits. It details the structure of machine instructions, types of instructions, instruction cycles, and various addressing modes such as immediate, direct, indirect, and more. Additionally, it discusses performance considerations and emphasizes the importance of understanding addressing modes and their impact on instruction execution time.

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21 views3 pages

Machine Instructions & Addressing Modes

The document provides an overview of machine instructions and addressing modes relevant for GATE preparation in digital circuits. It details the structure of machine instructions, types of instructions, instruction cycles, and various addressing modes such as immediate, direct, indirect, and more. Additionally, it discusses performance considerations and emphasizes the importance of understanding addressing modes and their impact on instruction execution time.

Uploaded by

surajeeth.edurev
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Machine Instructions & Addressing Modes Formula

Sheet for GATE (Digital Circuits)

Machine Instructions
• Definition: A machine instruction is a binary code that a processor executes to
perform a specific operation.
• Instruction Format:

Instruction = Opcode + Operand(s)

where Opcode specifies the operation, and Operand(s) specify the data or memory
address.
• Types of Instructions:
– Data Transfer: e.g., MOV, LOAD, STORE.
– Arithmetic: e.g., ADD, SUB, MUL, DIV.
– Logical: e.g., AND, OR, XOR, NOT.
– Control Transfer: e.g., JMP, CALL, RET.
– Input/Output: e.g., IN, OUT.
• Instruction Cycle:

Fetch → Decode → Execute → (Store)

• Instruction Length: Depends on architecture (e.g., fixed-length in RISC, variable-


length in CISC).
• Program Counter (PC): Holds the address of the next instruction to be fetched.

PC ← PC + Instruction Length

• Instruction Execution Time:

Ttotal = N · CP I · Tclock

where N is the number of instructions, CPI is cycles per instruction, Tclock is clock
period (s).

Addressing Modes
• Definition: Specifies how the operand of an instruction is accessed (e.g., data location
in memory or registers).
• Common Addressing Modes:

1
– Immediate: Operand is part of the instruction.

Operand = Value

Example: ADD #5 (Add 5 directly).


– Direct (Absolute): Operand is the memory address specified in the instruction.

Effective Address (EA) = Address Field

Example: LOAD 1000 (Load from memory address 1000).


– Indirect: Instruction specifies the address of a memory location that contains
the operand’s address.
EA = [Address Field]
Example: LOAD (R1) (Load from address stored in register R1).
– Register: Operand is in a register.

Operand = Register Content

Example: ADD R1, R2 (Add contents of R1 and R2).


– Register Indirect: Register contains the address of the operand in memory.

EA = [Register]

Example: LOAD [R1] (Load from memory address in R1).


– Indexed: Effective address is the sum of a base address and an index.

EA = Base Address + Index Register

Example: LOAD 100(R2) (Load from address 100 + content of R2).


– Relative: Effective address is relative to the program counter.

EA = PC + Offset

Example: JMP +4 (Jump to PC + 4).


– Base Register: Uses a base register to calculate the effective address.

EA = Base Register + Offset

– Implied (Inherent): Operand is implicitly defined by the instruction.

Operand = Implied by Opcode

Example: CLR (Clear accumulator).


• Stack Addressing: Operands are accessed from the stack (e.g., PUSH, POP).

EA = Stack Pointer (SP)

SP ← SP ± 1 (after PUSH/POP)

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Performance Considerations
• Effective Address Calculation Time: Varies by addressing mode (e.g., immediate
is fastest, indirect is slower).
• Memory Accesses: Indirect and indexed modes may require multiple memory ac-
cesses.
• Instruction Size: Immediate and direct modes increase instruction length due to
address or data fields.

Key Notes
• For GATE, focus on identifying addressing modes from instruction examples.
• Understand the impact of addressing modes on instruction execution time.
• RISC architectures prefer simpler addressing modes (e.g., register, immediate).
• CISC architectures support complex modes (e.g., indirect, indexed).
• Practice problems involving PC updates and effective address calculations.

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