CMOS Digital Integrated Circuits

Lec 10
Semiconductor Memories

1 CMOS Digital Integrated Circuits

 Semiconductor Memory Types

Semiconductor Memories

Read/Write (R/W) Memory

or Random Access Memory (RAM) Read-Only Memory (ROM)

1. Mask (Fuse) ROM

Dynamic RAM Static RAM 2. Programmable ROM (PROM)
(DRAM) (SRAM) Erasable PROM (EPROM)
Electrically Erasable PROM (EEPROM)
3. Flash Memory
4. Ferroelectric RAM (FRAM)

2 CMOS Digital Integrated Circuits

 Semiconductor Memory Types (Cont.)
 Design Issues
• Area Efficiency of Memory Array:  of stored data bits per unit area
• Memory Access Time: the time required to store and/or retrieve a
particular data bit.
• Static and Dynamic Power Consumption
 RAM: the stored data is volatile
• DRAM
» A capacitor to store data, and a transistor to access the capacitor
» Need refresh operation
» Low cost, and high density  it is used for main memory
• SRAM
» Consists of a latch
» Don’t need the refresh operation
» High speed and low power consumption it is mainly used for
cache memory and memory in hand-held devices

3 CMOS Digital Integrated Circuits

 Semiconductor Memory Types (Cont.)
 ROM: 1, nonvolatile memories
2, only can access data, cannot to modify data
3, lower cost: used for permanent memory in printers,
fax, and game machines, and ID cards
• Mask ROM: data are written during chip fabrication by a photo mask
• PROM: data are written electrically after the chip is fabricated.
» Fuse ROM: data cannot be erased and modified.
» EPROM and EEPROM: data can be rewritten, but the number of
subsequent re-write operations is limited to 104-105.
• EPROM uses ultraviolet rays which can penetrate through the crystal
glass on package to erase whole data simultaneously.
• EEPROM uses high electrical voltage to erase data in 8 bit units.
• Flash Memory: similar to EEPROM
• FRAM: utilizes the hysteresis characteristics of a capacitor to overcome
the slow written operation of EEPROMs.

4 CMOS Digital Integrated Circuits

 Random-Access Memory Array Organization
Bit Lines(2M)

Col 1 Col 2 Col 2M

Row 1
Memory Cell
A1 Row 2
Row Decoder Bits

Word Decoder

Word Lines(2N)
A2
Row Decoder

(2N2M total)

AN
Row 2N

Data Line Control Circuits

Column Decoder

B1 B2 BM
Column Decoder Bits
5 CMOS Digital Integrated Circuits
 Nonvolatile Memory
4Bit  4Bit NOR-based ROM Array
VDD
R1 R2 R3 R4 C1 C2 C3 C4

1 0 0 0 0 1 0 1
R1 0 1 0 0 0 0 1 1
0 0 1 0 1 0 0 1
0 0 0 1 0 1 1 0
R2
• One word line “Ri” is activated by
raising its voltage to VDD
R3 • Logic “1” is stored: Absent transistor
Logic “0” is stored: Present transistor
• To reduce static power consumption,
R4 the pMOS can be driven by a periodic
pre-charge signal.
C1 C2 C3 C4

6 CMOS Digital Integrated Circuits

Layout of Contact-Mask Programmable NOR ROM
metal column (bit)
lines to load devices metal metal

R1 poly
poly row diffusion
(word) lines to GND
R2 poly

to output
contact no contact
(0 bit) (1 bit)
• “0” bit: drain is connected to metal line via a metal-to-diffusion contact
“1” bit: omission the connect between drain and metal line.
• To save silicon area: the transistors on every two adjacent rows share a
common ground line, also are routed in n-type diffusion

7 CMOS Digital Integrated Circuits

 Layout of Contact-Mask Programmable
4Bit  4Bit
metal metal
NOR ROM
metal metal

poly

diffusion
to GND
poly

metal-diff
contact
poly
diffusion
to GND
poly

C1 C2 C3 C4
• In reality, the metal lines are laid out directly on top of diffusion
columns to reduce the horizontal dimension.
8 CMOS Digital Integrated Circuits
 Implant-Mask Programmable NOR ROM Array
metal columns
Logic “0” is stored in each cell:
Present transistor
R1

R2
poly rows

R3

R4

C1 C2 C3 C4
• VT0 is implanted to activate 1 bit:
Let VT0 > VDD  permanently turn off transistor
 disconnect the contact

9 CMOS Digital Integrated Circuits

 Layout of Implant-Mask Programmable
4Bit  4Bit NOR ROM
metal metal metal metal threshold
voltage
implant
R1 poly

diffusion
to GND
R2 poly

R3 poly
diffusion
to GND
R4 poly
metal-diff
contact C1 C2 C3 C4
• Each diffusion-to-metal contact is shared by two adjacent transistors
 need smaller area than contact-mask ROM layout
1 CMOS Digital Integrated Circuits
 4Bit  4Bit NAND-based ROM Array
VDD

R1 R2 R3 R4 C1 C2 C3 C4

C1 C2 C3 C4 0 1 1 1 0 1 0 1
R1 1 0 1 1 0 0 1 1
1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 0
R2

• All word lines are kept at logic “1”

R3 level, except the selected line pulled
down by “0” level.
• Logic “0” is stored: Absent transistor
R4 Logic “1” is stored: Present transistor

1 CMOS Digital Integrated Circuits

 Layout of Implant-Mask Programmable
4Bit  4Bit NAND ROM
diffusion lines to load devices
C1 C2 C3 C4 threshold
voltage
implant
R1 poly

R2 poly

R3 poly

R4 poly

diffusion lines to GND

• No contact in the array  More compact than NOR ROM array

• Series-connected nMOS transistors exist in each column
 The access time is slower than NOR ROM

1 CMOS Digital Integrated Circuits

 Design of Row and Column Decoders
• Row and Column Decoders: To select a particular memory location in
the array.

A1 R1
Row R2 2 address bits
R3
A2 Decoder  4 word lines
R4

A1 A2 R1 R2 R3 R4

0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

1 CMOS Digital Integrated Circuits

 NOR-based Row Decoder Circuit
2 Address Bits and 4 Word
V
DD
Lines

R1 VDD

R2 VDD

R3 VDD

A1 A2 R1 R2 R3 R4
R4 0 0 1 0 0 0
0 1 0 1 0 0

A2 A1 1 0 0 0 1 0
1 1 0 0 0 1
A2 A1
1 CMOS Digital Integrated Circuits
 Implementation of Row Decoder and ROM

• Can be implemented as two adjacent NOR planes

2N word lines

NOR Row NOR ROM

Decoder Array

12 N 2M columns
Address bits

1 CMOS Digital Integrated Circuits

Implementation of Row Decoder and ROM (Cont.)
• Can also be implemented as two adjacent NAND planes
2N word lines

NAND Row NAND ROM

Decoder Array

12 N 2M columns A1 A2 R1 R2 R3 R4
Address bits
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
44 NAND ROM Array

1 CMOS Digital Integrated Circuits

 Column Decoder (1)
NOR Address Decoder and Pass Transistors
• Column Decoder: To select one out of 2M bits lines of the ROM array,
and to route the data of the selected bit line to the data output
• NOR-based column address decoder and pass transistors:
» Only one nMOS pass transistor is turned on at a time
» # of transistors required: 2M(M+1) (2M pass transistors, M2M decoder)

ROM Array
1 2 3 2M
1 1
2 2
3 NOR
Column Address 3
2M pass
address Decoder transistors
bits 2M
M Serial or Parallel
Data output

1 CMOS Digital Integrated Circuits

 Column Decoder (2)
Binary Tree Decoder
• Binary Tree Decoder: A binary selection tree with consecutive stages
» The pass transistor network is used to select one out of every two bit lines at
each stages. The NOR address decoder is not needed.
» Advantage: Reduce the transistor count (2M+1-2+2M)
» Disadvantage: Large number of series connected nMOS pass transistors 
long data access time
C1 C2 C3 C4 C5 C6 C7 C8

B1
B1

B2
B2

B3
B3
Column
address bits Data output: Serial or Parallel
1 CMOS Digital Integrated Circuits
 An Example of NOR ROM Array
• Consider the design of a 32-kbit NOR ROM array and the design
issues related to access time analysis
» # of total bits: 15 (215=32,768)
» 7 row address bits (27 = 128 rows)
» 8 column address bits (28 = 256 columns)
» Layout: implant-mask threshold
2 4
» W = 2 m, L = 1.5 m voltage
  nCox = 20 A/V2 n+ diffusion implant
» Cox = 3.47 F/cm2 2
» Rsheet-poly = 20 /square
4 unit memory
cell

n+ diffusion
• Rrow, and Crow / unit memory cell
» Crow = Cox·W·L = 10.4 fF/bit
» Rrow = (# of squares)  Rsheet-poly = 3  20 = 60 

1 CMOS Digital Integrated Circuits

 An Example of NOR ROM Array (Cont.)
• The poly word line can be modeled as a RC transmission line with
up to 256 transistors
R1=60 R2=60 R3=60 R256=60
V256

Vin C1=10.4fF C2=10.4fF C3=10.4fF C256=10.4fF

• The row access time trow: delay associated with selecting and
activating 1 of 128 word lines in ROM array. It can be
approximated as
trow  0.38·RT·CT = 15.53 ns V V
OH
RT =allcolsRi = 15.36 k Vin
V256
CT =allcolsCi = 2.66 pF V50%

t
trow

2 CMOS Digital Integrated Circuits

 An Example of NOR ROM Array (Cont.)
• A more accurate RC delay value: Elmore time constant for RC
ladder circuits
256
trow =  Rjk Ck = 20.52 ns
k=1
• The column access time tcolumn: worst case delay  PHL associated
with discharging the precharged bit line when a row is activated.

VDD

(4/1.5)
column output

Ccolumn
R1 R2 R3 R128 (2/1.5)

2 CMOS Digital Integrated Circuits

 An Example of NOR ROM Array (Cont.)
• Ccolumn = 128  (Cgd,driver+Cdb,driver)  1.5pF
where Cgd,driver+Cdb,driver = 0.0118 pF/word line
• Since only one word line is activated at a time, the above circuit can
be reduced to an inverter circuit
VDD

(4/1.5)
Remark:  PLH is not considered because
the bit line is precharged high before
each row access operation
R1 (2/1.5) Ccolumn

C load  2V T 0,n  4V OH  V T 0,n   

t column   PHL    ln   1   18ns
k n V OH  V T 0,n   V OH  V T 0,n  V OH  V OL  
taccess= trow + tcolumn = 20.52 + 18 = 38.52 ns

2 CMOS Digital Integrated Circuits

 Static Random Access Memory (SRAM)
• SRAM: The stored data can be retained indefinitely, without any
need for a periodic refresh operation.
bit line C bit line C

1-bit SRAM cell

VDD

bit line C bit line C

load load

word line word line

• Complementary Column arrangement is to achieve a more

reliable SRAM operation
2 CMOS Digital Integrated Circuits
 Resistive-Load SRAM Cell

undoped polysilicon resistor

VDD

bit line C bit line C

R R

SRAM cell is accessed via

word line word line two bit (column) lines C
and its complement for
reliable operation

pass transistors to
activated by a row select Basic cross-coupled 2-inverter
(RS) signal to enable latch with 2 stable op points for
read/write operators storing one-bit

2 CMOS Digital Integrated Circuits

 Full CMOS and Depletion-Load SRAM Cell
VDD

bit line C bit line C

Full CMOS SRAM

Cell
word line word line

VDD

bit line C bit line C

Depletion-Load
SRAM Cell
word line word line

2 CMOS Digital Integrated Circuits

 SRAM Operation Principles
Pull-up transistor (one per column)
VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS
• RS=0: The word line is not selected. M3 and M4 are OFF
 One data-bit is held: The latch preserves one of its two stable states.
 If RS=0 for all rows: CC and CC are charged up to near VDD by
pulling up of MP1 and MP2 (both in saturation)

V C  V C  V DD  V T 0   2 F  V C  2 F 
 Ex: VC = VC =3.5V for VDD = 5V, VT0=1V, |2 F|=0.6V, =0.4V1/2
2 CMOS Digital Integrated Circuits
 SRAM Operation Principles (Cont.)
Pull-up transistor (one per column)
VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

• RS=1: The word line is now selected. M3 and M4 are ON

Four Operations
1. Write “1” Operation (V1=VOL, V2=VOH at t=0-):
VC  VOL by the data-write circuitry. Therefore, V2  VOL, then
M1 turns off V1 VOH and M2 turns on pulling down V2  VOL.

2 CMOS Digital Integrated Circuits

 SRAM Operation Principles (Cont.)

Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

2. Read “1” Operation (V1=VOH, V2=VOL at t=0-):

VC retains pre-charge level, while VC  VOL by M2 ON. Data-read
circuitry detects small voltage difference VC – VC > 0, and amplifies
it as a “1” data output.

2 CMOS Digital Integrated Circuits

 SRAM Operation Principles (Cont.)

Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

3. Write “0” Operation (V1=VOH, V2=VOL at t=0-):

VC  VOL by the data-write circuitry.
Since V1  VOL, M2 turns off, therefore V2  VOH.

2 CMOS Digital Integrated Circuits

 SRAM Operation Principles (Cont.)

Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

4. Read “0” Operation (V1=VOL, V2=VOH at t=0-):

VC retains pre-charge level, while VC  VOL by M1 ON.
Data-read circuitry detects small voltage difference VC – VC < 0, and
amplifies it as a “0” data output.

3 CMOS Digital Integrated Circuits

 SRAM Operation Principles (Cont.)
Pull-up transistor (one per column)
VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

write 1 read 1 write 0 read 0

RS hold hold hold hold hold

VC 3.5V 3.0V
0V
VC 3.5V 3.5V
3.0V

3 CMOS Digital Integrated Circuits

 Static or “Standby” Power Consumption
Pull-up transistor (one per column)
VDD VDD
VDD
MP1 MP2

bit line C R R bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

• Assume: 1 bit is stored in the cell  M1 OFF, M2 ON  V1=VOH,

V2=VOL. I.E. One load resistor is always conducting non-zero current.
Pstandby = (VDD-VOL)2/R
with R = 100MΩ (undoped poly), Pstandby  0.25 W per cell for VDD
=5V

3 CMOS Digital Integrated Circuits

 Circuit of CMOS SRAM Cell
Pull-up transistor (one per column)
VDD (Column voltages can reach to full VDD) VDD
VDD
MP1 MP2

bit line C M5 M6 bit line C

VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS
 Advantages
• Very low standby power consumption
• Large noise margins than R-load SRAMS
• Operate at lower supply voltages than R-load SRAMS
 Disadvantages
• Larger die area: To accommodate the n-well for pMOS transistors
and polysilicon contacts. The area has been reduced by using multi-
layer polysilicon and multi-layer metal processes
• CMOS more complex process
3 CMOS Digital Integrated Circuits
 6T-SRAM — Layout

VDD
M6 M5

V2 V1
M2 M1

GND
M4 M3 RS

BL BL
Source: Digital Integrated Circuits 2nd

3 CMOS Digital Integrated Circuits

 CMOS SRAM Cell Design strategy
 Two basic requirements which dictate W/L ratios
1. Data-read operation should not destroy data in the cell
2. Allow modification of stored data during data-write operation
Pull-up transistor (one per column)
VDD (Column voltages can reach to full VDD) VDD
VDD
MP1 MP2

bit line C M5 M6 bit line C

VC VDD M3 V1=0V V2=VDD M4 VC=VDD

CC M1 M2 CC

word line
RS
• Read “0” operation
» at t=0-: V1=0V, V2=VDD; M3, M4 OFF; M2, M5 OFF; M1, M6 Linear
» at t=0: RS = VDD, M3 Saturation, M4 Linear; M2, M5 OFF; M1, M6
Linear
• Slow discharge of large CC: Require V1 < VT,2 Limits M3 W/L wrt
M1 W/L
3 CMOS Digital Integrated Circuits
 CMOS SRAM Cell Design Strategy (Cont.)
Pull-up transistor (one per column)
VDD (Column voltages can reach to full VDD) VDD
VDD
MP1 MP2

bit line C M5 M6 bit line C

VC VDD M3 V1=0V V2=VDD M4 VC=VDD

CC M1 M2 CC

word line
RS
• Design Constraint: V1,max < VT,2 = VT,n to keep M2 OFF
» M3 saturation, M1 linear 
kn,3(VDD-V1-VT,n)2/2 = kn,1(2(VDD-VT,n)V1-V12)/2
» Therefore,
 W  
Symmetry:
k n , 3   L  3  2V DD  1.5V T ,n  V T ,n
Same for kn,4/kn,2
k n ,1 
 
W  
V DD 2V T ,n  2

(M1 OFF for Read “1”)

 L1
3 CMOS Digital Integrated Circuits
 CMOS SRAM Cell Design Strategy (Cont.)
• Write “0” operation with “1” stored in cell:
Pull-up transistor (one per column)
VDD (Column voltages can reach to full VDD) VDD
VDD
MP1 MP2

bit line C M5 M6 bit line C

VC=0V M3 V1=VDD V2=0V M4 VC=VDD

CC M1 M2 CC

word line
RS
• VC is set “0” by data-write circuit (“1” stored)
 at t=0 : V1=VDD, V2=0V; M3, M4 OFF; M2, M5 Linear; M1, M6 OFF
-

 at t=0: VC=0V, VC=VDD; M3, M4 saturation; M2, M5 Linear; M1, M6 OFF

» Write “0”V1: VDD 0(<V2T,n) and V2:0 VDD(M2 OFF)

3 CMOS Digital Integrated Circuits

 CMOS SRAM Cell Design Strategy (Cont.)
• Design constraint: V1,max<VT,2= VT,n to keep M2 OFF
» When V1=VT,n: M3 Linear and M5 saturation
kp,5(0-VDD-VT,p)2/2 = kn,3(2(VDD-VT,n)VT,n-VT,n2)/2
» V1<VT,n, i.e. M2(M1) forced OFF
k p , 5  k p , 6  2V DD  1.5V T ,n  V T ,n 
k n ,3 k n,4  V DD  V T , p  2
By symmetry
 W  W
   
 L  5   L  6   n 2V DD  1.5V T ,n  V T ,n 
 W  W p  V DD  V T , p  2
   
VDD  L3  L 4 VDD
VDD
MP1 MP2

bit line C M5 M6 bit line C

VC=0V M3 V1=VDD V2=0V M4 VC=VDD

CC M1 M2 CC

word line
RS
3 CMOS Digital Integrated Circuits
 SRAM Write Circuit
VDD VDD

MP1 MP2
bit line C 1-bit bit line C
Shared by VC VC
several SRAM Cell
columns RS word line

W WB M2

DATA M1
WB

From Column M3
Decoder

W DATA WB WB Operation (M3 on)

0 1 0 1 M1 off, M2 on  VC  low
0 0 1 0 M1 on, M2 off  VC  low
1 X 0 0 M1 off, M2 off  VC, VC no change
3 CMOS Digital Integrated Circuits
 SRAM Read Circuit
VDD
Source coupled
differential R R
amplifier Vo1 Vo2
VC M1 M2 VC
VX

kn
I D1   V C  V X  V T 1 ,n  2
2
kn
I D2   V C  V X  V T 2 ,n  2

2
 V o 1  V o 2 
Asense    gm R Increase R
 V C  V C  Use active load
 I D 
gm 2k n I D Use cascade
V GS
4 CMOS Digital Integrated Circuits
 Sense Amp Operation

V BL V(1)

V PRE
DV(1)

V(0)
Sense amp activated t
Word line activated

Source: Digital Integrated Circuits 2nd

4 CMOS Digital Integrated Circuits

 Fast Sense Amplifier
VDD pMOS
current VDD
mirror
M4 M5
Vo MP2
VON
VC VC MN1
M1 M2
CC CC
CK M3
bit line C bit line C

• VC < VC: M1 OFF, Vo decreases, VON High

• VC > VC: M2 OFF, Vo remains high, VON =Low
Asense = -gm2(ro2||ro5)

4 CMOS Digital Integrated Circuits

 Two-Stage differential Current-Mirror Amplifier
Sense Circuit
VDD VDD

VC
VC VC

CK
VDD
VDD

VON

CK

4 CMOS Digital Integrated Circuits

 Typical Dynamic Response for One and Two
Stage Sense Amplifier Circuits
Voltage (V) Output-2 Stage

Output-1 Stage
5

3
VC
2

5 10 15 20 25 30 t (nsec)
4 CMOS Digital Integrated Circuits
 Cross-Coupled nMOS Sense Amplifier

VC VC

CC M1 M2 CC

bit line C CK M3 bit line C

• Assume: M3 OFF, VC and VC are initially precharged to VDD

• Access: VC drops slightly less than VC
• M3 ON and VC < VC : M1 ON first, pulling VC lower
M2 turns OFF, CC discharge via M1
and M3
Enhances differential voltage VC - VC
Does not generate output logic level

4 CMOS Digital Integrated Circuits

 Dynamic Read-Write Memory (DRAM) Circuits
• SRAM: 4~6 transistors per bit
4~5 lines connecting as charge on capacitor
• DRAM: Data bit is stored as charge on capacitor
Reduced die area
Require periodic refresh
WL

M1 M2
M3 M4

parasitic storage
BL BL
capacitances
Four-Transistor DRAM Cell

4 CMOS Digital Integrated Circuits

 DRAM Circuits (Cont.)

WL(read)

X M2
M1 M3

parasitic storage
WL(write) capacitances
BL(write) BL(read)

Three-Transistor DRAM Cell

No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = V WWL-VTn

4 CMOS Digital Integrated Circuits

 3T-DRAM — Layout

BLR BLW GND

RWL
M3

M2

WWL
M1

Source: Digital Integrated Circuits 2nd

4 CMOS Digital Integrated Circuits

 One-Transistor DRAM Cell
WL

M1 explicit storage
capacitances
BL

One-Transistor DRAM Cell

• Industry standard for high density dram arrays

• Smallest component count and silicon area per bit
• Separate or “explicit” capacitor (dual poly) per cell

4 CMOS Digital Integrated Circuits

 Operation of Three-Transistor DRAM Cell
VDD

MP1 Precharge devices MP2

PC
RS

M3
M1 M2
C2 C3
C1

WS

Data_in Data_out
DATA
C2, C3 >> C1(>10C1)
• The binary information is stored as the charge in C1
• Storage transistor M2 is on or off depending on the charge in C1
• Pass transistors M1 and M3: access switches
• Two separate bit lines for “data read” and “data write”
5 CMOS Digital Integrated Circuits
 Operation of Three-Transistor DRAM Cell (Cont.)
VDD PC write 1 PC read 1 PC write 0 PC read 0
① 2 ③ 4 ⑤ 6 ⑦ 8
MP1 Precharge devices MP2 PC
PC WS
RS

M3 DATA
M1 M2
C2 C3
Din
C1

WS Stored data

Data_in Data_out RS
DATA
Dout

• The operation is based on a two-phase non-overlapping clock scheme

» The precharge events are driven by  1, and the “read” and “write”
operations are driven by  2.
» Every “read” and “write” operation is preceded by a precharge
cycle, which is initiated with PC going high.

5 CMOS Digital Integrated Circuits

 Operation of Three-Transistor DRAM Cell (Cont.)
VDD

MP1 Precharge devices MP2

PC Pre-charge Cycle
C2 C3
RS

M3
M1 M2
C2 C3
C1

WS
Data_in Data_out
DATA

• Write “1” OP: DATA = 0, WS = 1; RS = 0

» C2, C1 Share charge due to M1 ON
» Since C2 >> C1, the storage node C1 attains approximately the
same logic level.
5 CMOS Digital Integrated Circuits
 Operation of Three-Transistor DRAM Cell (Cont.)

RS
M3
M1 M2
C2 C3
C1

WS
Data_in Data_out
DATA

• Read “1” OP: DATA = 0, WS = 0; RS = 1

» M2, M3 ON  C3, C1 discharges through M2 and M3, and the
falling column voltage is interpreted bt the “data read” circuitry
as a stored logic “1”.

5 CMOS Digital Integrated Circuits

 Operation of Three-Transistor DRAM Cell (Cont.)

RS

M3
M1 M2
C2 C3
C1

WS
Data_out
Data_in
DATA

• Write “0” OP: DATA = 1, WS = 1; RS = 0

» M2, M3 ON  C2 and C1 discharge to 0 through M1 and data_in
nMOS.

5 CMOS Digital Integrated Circuits

 Operation of Three-Transistor DRAM Cell (Cont.)

RS
M3
M1 M2
C2 C3
C1

WS
Data_in Data_out
DATA

• Read “0” OP: DATA = 1, WS = 0; RS = 1

» C3 does not discharge due to M2 OFF, and the logic-high level
on the Data_out column is interpreted by the data read circuitry
as a stored “0” bit.

5 CMOS Digital Integrated Circuits

 Operation of One-Transistor DRAM Cell
WL

M1
Column C2 C1
capacitance
BL
1-bit DRAM Cell
C2>>C1

• Write “1” OP: BL = 1, WL = 1 (M1 ON)C1 charges to “1”

• Write “0” OP: BL = 0, WL = 1 (M1 ON)C1 discharges to “0”
• Read OP: destroys stored charge on C1  destructive refresh is
needed after every data read operation

5 CMOS Digital Integrated Circuits

 Appendix
 W 
 Derivation of k n , 3   L  3  2V DD  1.5V T ,n  V T ,n
k n ,1  W 
 
 V DD  2V T ,n 
2

 L1
kn,3(VDD-V1-VT,n)2/2 = kn,1(2(VDD-VT,n)V1-V12)/2
 Therefore,

k n ,3
 
W
V DD  V T ,n  2  V  V  2
2V DD  1.5V T ,n 

 
 L 3
 1   1  DD T , n

k n ,1 W  V DD  V1  V T ,n  2
 V DD  2V T ,n   V DD  2V T ,n 
2 2

L 1

5 CMOS Digital Integrated Circuits