ESE 570 Chip Input and Output (I/O)

Circuits

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 1

 OVERVIEW
1. INPUT PADS – ESD PROTECTION

2. TTL-TO-CMOS LOGIC LEVEL SHIFTING

3. DIFFERENTIAL SIGNALING

4. OUTPUT PADS – L di/dt NOISE

5. BIDIRECTIONAL I/O PADS

6. ON-CHIP CLOCK GENERATION AND DISTRIBUTION

7. LATCH-UP PROTECTION IN OUTPUT PADS

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 2

 ESD PROTECTION
Human Body Model (HBM) Machine Model (MM)

Charged-Device Model (CDM)

1 MΩ
Electrostatic charge low
builds up on a chip B resistance,
due to improper low
Vesd Bulk or inductance
grounding and then Ground DUT
discharges probe
Pin
when a low-
resistance path Simulates ESD phenomena of packaged ICs
becomes available. during manufacturing and assembly.

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 3

 ATE HBM ESD and MM ESD TEST
SETUP

1.4
SPICE-generated short-
circuit HBM output
current waveform
current I (A)

specified by MIL-STD After exposure to the ESD waveform, a

883.C/3015.7 for Cc failed IC exhibits latch-up or fails one or
charged to 2kV more data sheet specifications.

0
0 100 200
time (ns)
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 4
 TYPICAL ESD PROTECTED INPUT PAD

VDD

I
R
200 Ω ≤ R ≤ 3 k
Ω

or 8A ≥ I ≥ 2.6 A.

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 5

 INPUT PAD WITH SERIES
TRANSMISSION GATE

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 6

 INVERTING INPUT PAD WITH TTL-TO-CMOS
LEVEL SHIFT

VDD = 5 V
CMOS

TTL

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 7

 VARIATIONS IN LEVEL-SHIFT VTC DUE 8x

TO PROCESS VARIATIONS

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 8

 WORST CASE SIMULATION METHOD

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 9

 Differential Signaling System

Two-wire pair Receiver

Transmitter
I = +i

I = -i
Terminator

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 10

 DIFFERENTIAL SIGNALING (LOGIC
LEVELS) FOR GBPS SYSTEMS

1.400 V
VOL 1.000 V 0.400 V

1.220 V

1.100 V

1
2

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 11

 OUTPUT PADS

CK or
ST CK D P N Z
1 1 0 0 1=D
1 0 1 1 0=D
00 xx 11 0 0 High
HIGH
Z Z

MP1

MP2

MN2
CK = 0 => MN2 & MP2 OFF => Z = HIGH Z
CK = 1 => MN2 & MP2 ON => Z = D MN1

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 12

 OUTPUT PADS – L di/dt NOISE

Cload

assume
Cload
I max charged
to VDD
ts/2

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 13

 OUTPUT PADS – L di/dt NOISE

REDUCE NOISE => lower VDD or increase ts -> limits speed

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 14
 OUTPUT PADS – REDUCE L di/dt NOISE

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 15

 DIFFERENTIAL DRIVER OUTPUT PAD

VDD/2

tD Delay Element

tD
“1” “1”
“0”
A = IN (t - tD)

“1” Much
“1”
“0” reduced
[di/dt]max
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 16
 BIDIRECTIONAL I/O PAD WITH TTL
INPUT CAPABILITY

D
1
E=1 X
D
E=0 0

E = 1 => Z = D
E = 0 => X = high Z
E = 0 => DI = Z
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 17
 Clock System Architecture

Global
Clock

● Chip receives external clock through I/O pad or an internal clock is included in
the Clock Generator.
● Clock generator adjusts the global clock to the external clock.
● Global clock is distributed across the chip.
● Local drivers and “clock gaters” drive the physical clocks to clocked elements.
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 18
 ON-CHIP CLOCK GENERATION AND
DISTRIBUTION

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 19

 TWO-PHASE CLOCK GENERATION

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 20

 Clock Skew and Jitter

• Clock should theoretically arrive simultaneously to all sequential

circuits.

• Practically it arrives in different times. The differences are called clock

skews.

• Most systems distribute a global clock and then use local “clock gaters”
located near clocked elements.

• Skews result from paths mismatches, process variations and ambient

conditions, resulting in physical clocks ≠ global clock.

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 21

 Clock Skew Components
Systematic is the portion of clock skew existing under nominal
conditions. It can be minimized by appropriate design.
Random is variable portion of clock skew caused by random process
variations like devices’ channel length, oxide thickness, threshold
voltage, wire thickness, width and space. It can be measured on
silicon and adjusted by DLL components.
Drift is time-dependent portion of clock skew caused by time-
dependent environmental variations, occurring relatively slowly.
Compensation of those must takes place periodically.
Jitter is rapid clock edge changes (deterministic and random
components), occurring by power noise and clock generator jitter.
It cannot be compensated.
Unit Interval
Reference Ideal Edge
Edge Location
Edge Location
Shifted
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 22
 PLL Clock Distribution & Buffers

VCO
Input Output
Clock Clock
LF Frequency/Phase
PD
Control

DLL Clock Distribution & Buffers

Variable Delay
Input Line
Clock Output
Delay Control Clock
PD LF

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 23

 Some Representative Clock Distribution
Networks

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 24

 H-TREE CLOCK DISTRIBUTION NET
FOR UNIFORM CLOCK DISTRIBUTION

CAD Techniques automate the generation of hierarchical clock distribution

networks.
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 25
 LATCH-UP IN CMOS CIRCUITS
2
BJT saturation A E q D n
n i
current I S =
N AW

2
1 1
x* +
NSUB nMOS − pMOS spacing

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 26

 LATCH-UP – POSITIVE FEEDBACK
Bipolar Current Gains
IC IC
-= )1 0(,= (1
IB IE
,
-= IB1 = IC2
1−,
IB1
IC2 = β2β1IB1
IB2
IC1 = β1IB1
Rwell = Rsub.=∞
IB2 = IC1

Latch-up
Analysis with
Rwell = Rsub.=∞
time = t1 > 0:
Prevent latch-up by reducing IB1 = x => IC1 = β1 x
positive feedback β1β2 ≤ 1
,1 ,2 time = t2 > t1
-1 - 1 = ≤ 1⇒ ,1 ',2 ≤ 1 IB2 = IC1 = β1 x => IC2 = β2β1 x
1−,1 1−, 2
positive feedback! if β2β1 ≥ 1
Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 27
 LATCH-UP PREVENTION
Latch-up prevention with
parasitic resistances Rwell RT RT
,1 ' ,2
and Rsub R well R sub Latch-up occurs
,1 ', 2 ≥≤ 1' if NOT satisfied
V DD
make small −2
V
V BE BE

Reduce α1, α2 ; Decrease VDD

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 28

 OUTPUT BUFFER CELL LAYOUT WITH
LATCH-UP PREVENTION

Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 29