ESE 570 Design for Manufacture

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 1

 OVERVIEW
Design Quality (Reminder)
What is Design for Manufacturability?
Modeling Process Variations
Impact of Process Variations on Circuit
Performance
Parametric Yield Estimation
Parametric Yield Optimization

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 2

 DESIGN QUALITY

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 3

 DESIGN QUALITY cont.

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 4

 WHAT IS DESIGN FOR
MANUFACTURABILITY?

Design goal: All fabricated circuits meet all performance specs under all
fab and operating conditions.

Impediments:
1. Random variations in fabrication process.
2. Random variations in operating conditions, e.g. V DD, Tambient.
3. Less than full chip testability (controllability and observability).

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 5

 WHAT IS DESIGN FOR
MANUFACTURABILITY?
DFM Practice:
1. Consider effects of random fabrication parameters and operating
conditions early in the design process.
2. Design and layout done to reduce sensitivity to these variations.
a. Design to performance specs with sufficient margins.
b. Satisfy Design Rules with some margin.
3. Design for Testability.

DFM Metrics:
1. Functional yield.
2. Parametric yield.
3. Worst-case performance.
4. Test fault coverage.

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 6

VLSI CAD Supports Design for Manufacturability

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 7

 IMPURITY DOSES
LITHOGRAPHY PROCESS
PARAMETRS

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 8

 MODELING PROCESS VARIATIONS

1. Make critical devices larger, i.e. increase L and W, keeping W/L constant.

+
+
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 9
MODELING PROCESS VARIATIONS cont.
2
1 s
−1 i
*si)+=
ff(s = exp [ ] *si)+ =
ff(s
i - si ( 2 , 2 - si i

0 0

= si0== 0
=
≠ Invaluable ally to IC designers
= =

where
-1 ≤ ρsisj ≤ 1
= =

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 10

 IMPACT OF PROCESS VARIATIONS ON
CIRCUIT PERFORMANCE MEASURES
=
=
0
)s mean values of )s usually s0 = 0

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 11

 IMPACT OF PROCESS VARIATIONS ON
CIRCUIT PERFORMANCE MEASURES cont.
= =
=

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 12

 IMPACT OF PROCESS VARIATIONS ON
CIRCUIT PERFORMANCE MEASURES cont.

mτp = 0.184 ns
στp = 0.023 ns

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 13

 Some Real Defects in Chips
Processing defects
Missing contact windows
Parasitic transistors
Oxide breakdown

Material defects
Bulk defects (cracks, crystal imperfections)
Surface impurities (ion migration)

Time-dependent failures (Age defects)

Dielectric breakdown
Electromigration

Packaging failures
Contact degradation
Seal leaks
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 14
 PARAMETRIC YIELD ESTIMATION

2-dimensional space

Acceptable Region
In Performance Space
Ar

0.5

p-dimensional space

= parametric yield
Y * )r + is a scalar, deterministic quantity that is difficult to evaluate.
pdf's for rk are usually not known specifically.
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 15
 PARAMETRIC YIELD ESTIMATION cont.

Actual values
(x1, x2) due Acceptable Region
statistical In Parameter Space
variations about Ax
d Allowed circuit
= = d parameter values
restricted to subset of
Acceptable circuit circuit parameter space
parameters for the
due to physical
considerations.
design point d
Ax =

Ax
Parametric yield = = Ax = Ax = ∫Af * d='s+ ds
x

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 16

PARAMETRIC YIELD MAXIMIZATION
== ==

2. Design Centering Method

Acceptable
Design Region
Ax

New Acceptable
Design Region
Ax

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 17

 VLSI DFM and Manufacturing Process

Test dies on wafer

Test packaged parts

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 18

 Types of Manufacturing Tests
● Characterization Testing
● Used to characterize devices and performed through production life to
improve the process, hence yield
● Production testing
● Factory testing of all manufactured chips for parametric faults and for
random defects.
● The test patterns may not cover all possible functions and data
patterns but must have a high fault coverage of modeled faults.
● The main driver is cost, since every device must be tested. Test time
must be absolutely minimized.
● Only a go/no-go decision is made.
● Burn-In testing
● Ensure reliability of tested devices by testing.
● Detect the devices with potential failures.
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 19
 Testing Principle

Device Under Test

(DUT)

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 20

EXAMPLE ADVANTEST Model T6682 ATE
Consists of
● Powerful computer

● Powerful DSP for analog

testing
● Probe head: actually touches

the bare dies or packaged chips

to perform fault detection
experiments
● Probe card: contains

electronics to measure chip pin

or pad

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 21

 ATE Test Operation

DUT

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 22

 Test Cost Trends
Two key factors are changing the way of VLSI ICs testing
The manufacturing test cost has been not scaling
The effort to generate tests has been growing geometrically along with
product complexity

Cost: $/transistor

0.01
0.001 Si cost/transistor
0.0001
0.00001
0.000001
0.0000001 Test cost/transistor
0.00000001
0.000000001

Source: SIA
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 23
 Defect, Fault, and Error
Defect (imperfection in hardware):
A defect in an electronic system is the unintended difference
between the implemented hardware and its intended design.

Error:
A wrong output signal produced by a defective system is
called an error. An error is an “effect” whose cause is some
“defect”.

Fault (imperfection in function):

A representation of a “defect” at the abstracted function level
is called a fault.

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 24

 Observability & Controllability
Observability: ease of observing a node by watching external
output pins of the chip

Controllability: ease of forcing a node to 0 or 1 by driving input

pins of the chip

Combinational logic is usually easy to observe and control

Sequential logic or finite state machines can be very difficult,

requiring many cycles to enter desired state

Good observability and controllability reduces number of test

vectors required for manufacturing test.
Reduces the cost of testing
Motivates design-for-test

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 25

 Common Fault Models
Single stuck-at faults

Transistor open and short faults

Memory faults

PLA faults (stuck-at, cross-point, bridging)

Functional faults (processors)

Delay faults (transition, path)

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 26

 Test Process

What faults to test (fault modeling)?

How are test patterns obtained (test pattern generation)?

How is test quality (fault coverage) measured (fault simulation)?

How are test vectors applied and results evaluated (ATE/BIST)?

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 27

 Single Stuck-at Fault
Three properties define a single stuck-at fault

Only one line is faulty

The faulty line is permanently set to 0 or 1

The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 28

 The Test Problem
Given a set of faults in the DUT, how do we obtain a certain (small) number of test
patterns which guarantees a certain (high) fault coverage?

s-a-1 C D Y Y(C is s-a-1)

0 0 1 0
0 1 0 0
test vector 1 0 0 0
1 1 0 0
Fault coverage (FC)
● The measure of the ability of a test (a collection of test patterns) to detect
faults that may occur on the DUT
Number of detected faults
● FC =
Number of possible faults
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 29
 AUTOMATIC TEST-PATTERN GENERATION (ATPG)

A U
B s-a-0
Y
Z
X
C
D
E
Determine the input pattern that exposes an s-a-0 fault occurring at node U at
the output Z.

a. Choose an input pattern that sets U = 1, i.e. A = B = 1 - controllability.

b. The fault at U needs to propagate to Z to be observed, i.e. Y = U iff X = 1
and Z = U if E = 0.
c. X = 1 => C = D = 1.
d. The (unique) test vector can now be assembled: A = B = C = D = 1, E = 0.

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 30

 Design for Test
Design the chip to increase observability and controllability.

If each register could be observed and controlled, test problem

reduces to testing combinational logic between registers.

Better yet, logic blocks could enter test mode where they generate
test patterns and report the results automatically.

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 31

 Scan Based Testing
Scan test is to obtain control and observability for FFs.
It reduces sequential Test Pattern Generation circuits (TPG) to
combinational TPG circuits.

With Scan, a synchronous sequential circuit works in two modes.

Normal mode and Test mode:
NORMAL TEST

In test mode, all FFs are configured as a shift register, with Scan-in and
Scan-out routed to a (possibly dedicated) Pin-IN (PI) and Pin-OUT (PO).
Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 32
 Scan Based Testing
Convert each flip-flop to a scan register
Costs one extra multiplexer
SCAN

Normal mode: flip-flops behave as usual SI

SCAN OUT
D
Scan mode: flip-flops behave as shift register
SCAN
scan-in
Contents of flops
can be scanned
out and new D- inputs
values scanned in Q- outputs

scan-out

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 33

 Boundary Scan for Board Test

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 34

 Some Important Boundary Standards

Digital Boundary Scan (IEEE 1149.1)

Analog Boundary Scan (IEEE 1149.4)

Boundary Scan for Advanced Networks (IEEE 1149.6)

Embedded Core Test Standard (IEEE 1500)

Kenneth R. Laker, University of Pennsylvania, updated 27Apr15 35