Digital Logic Note

Pokhara University
Faculty of Science and Technology

Course No.: xxx xxx Full marks: 100

Course title: Digital Logic Pass marks: 45
Nature of the course: Theory and Practical Time per period: 1 hour
Year: First, Semester I Total periods: 45
Level: Undergraduate Program: BE

1. Course Description
This course covers the various concepts of digital logic systems. This course emphasizes on
fundamental concept, principles and properties of Boolean algebra and its application in
simplification, circuit analysis and gate implementation. It covers the use of flip flops in the design
of synchronous and asynchronous sequential logic circuits. It also covers the ALU design.

2. General Objective
The main objectives of the course are
• To provide basic knowledge of logic systems.
• To introduce the basic tools to design various digital logic circuits.
• To design a basic digital computer.

3. Methods of Instruction
• Lecture
• Tutorial
• Laboratory work

4. Contents in Detail

Specific Objectives Contents

• Familiarize and compare Unit 1 : Introduction (2 hrs)

analog and digital signal and
system. 1.1 Analog and digital signal
• Familiarize and use the 1.2 Analog and digital system
information representation in 1.3 Numerical representation
any number system. 1.4 Digital number system
• Familiarize with binary Unit 2 : Number Systems and Codes (6 hrs)
number systems and their
conversions. 2.1 Number systems
• Understand the different
2.1.1 Decimal
codes to represent
information. 2.1.2 Binary

2.1.3 Octal

2.1.4 Hexadecimal

2.2 Number system conversion

2.3 Complements (radix and diminished-radix)

2.4 Subtraction using complements

2.5 Binary coding systems

2.5.1 Weighted codes ( BCD, 8 4 -2 -1, and 2 4 2 1)

2.5.2 Non-weighted codes (Excess-3 and Gray)

2.6 Alphanumeric and instruction codes

• To trace the simplification Unit 3 : Boolean Algebra and Logic Gates ( 4 hrs)
process using Boolean
Algebra. 3.1 Boolean algebra (definition, properties, postulates and
• To implement the simplified theorems)
functions using logic gates.
3.2 Logic gates, truth tables and Boolean function

3.3 Duality principle and complements

3.4 Gate implementation

3.5 Universality of NAND and NOR gates

• and standard forms. Unit 4 : Simplification of Boolean Function (5 hrs)

• Simplify the Boolean function
using map method. 4.1 Venn diagram
• Help to identify and use don’t
4.2 Canonical forms and standard forms
care conditions while
simplifying functions. 4.3 Karnaugh map up to 5 variables
 4.4 Minimum realization

4.5 Don’t care conditions

4.6 Simplification in SOP and POS using K-map

Unit 5 : Combinational Circuit (4 hrs)

• Describe how to design
various combinational logic 5.1 Design procedure
circuits.
5.2 Adder and subtractor
• Help to analyze the designed
combinational circuits.
5.3 Code conversion

5.4 Analysis procedure

5.5 NAND and NOR implementation

5.6 Multilevel NAND and NOR gates

5.7 Parity generator and checker

• Describes different Unit 6 : MSI and LSI Design (6 hrs)

generations of IC technology.
• Describe different MSI and LSI 6.1 Introduction to Integration technology
components, their design,
6.2 Parallel adder and subtractor
internal logic diagram,
operation and
6.3 Decimal / BCD adder
implementation.
6.4 Magnitude comparator

6.5 Multiplexer and demultiplexer

6.6 Encoder and Decoder,

6.7 ROM and PLA

• Distinguish between Unit 7 : Sequential Circuits (6 hrs)
synchronous and
asynchronous logic and latch 7.1 Synchronous and asynchronous logic
and flip flops.
7.2 Differences between Latch and fli-flop
• Give knowledge of different
flip flops and their use in Flip flops (RS, JK,D, T) and their truth table, excitation table and
sequential logic circuits.
characteristic equation
• Help to design and analyze
sequential logic circuits. 7.3 Triggering of flip flops

7.4 State diagram and state table

7.5 State reduction and binary assignment

7.6 Design and analysis of clocked sequential circuit

7.7 Master-slave flip flops

• Describe about registers, shift Unit 8 : Registers and Counters (6 hrs)

registers and types with timing
sequences. 8.1 Register, shift register and types of Shift register
• Design synchronous,
8.2 Synchronous counters
asynchronous and Mod
counters. 8.2.1 up to 4 bit counters

8. 3 Asynchronous counters

8.3.1 BCD ripple counter,

8.3.2 Mod counter

8.4 Ring counter

8.5 Output hazard race

• Describe about read and write Unit 9 : Memory Unit and ALU (6hrs)
operation in RAM.
• Design arithmetic circuit and 9.1 Random access memory
logic unit.
9.2 Design of arithmetic logic unit
• Describe about the processor
unit and its diagram. 9.3 Accumulator
 9.4 Shifter and status register

9.5 Processor unit

Note: The figures in the parentheses indicate the approximate periods for the respective units.

5. Laboratory work:
• Familiarization with logic gates.
• Familiarization with Boolean functions.
• Design of simple combinational circuits.
• Adder and subtractor
• Encoder and decoder
• Multiplexer and demultiplexer
• Design of flip flops.
• Registers and counters

6. Evaluation system and Students’ Responsibilities

Internal Evaluation
In addition to the formal exam(s), the internal evaluation of a student may consist of quizzes,
assignments, lab reports, projects, class participation, etc. The tabular presentation of the internal
evaluation is as follows. The components may differ according to the nature of the subject.

External Evaluation Marks Internal Evaluation Weight Marks

Semester-End examination 50 Assignments 12% 6
Attendance 6%
3
Unit test 14%
Assessment 28% 7
Practical 40% 14
20
Total External 50 Total Internal 100% 50
Full Marks 50+50 = 100

Student Responsibilities:
Each student must secure at least 45% marks in internal evaluation with 80% attendance in the class in
order to appear in the Semester End Examination. Failing to get such score will be given NOT
QUILIFIED (NQ) and the student will not be eligible to appear the End-Term examinations. Students
are advised to attend all the classes and complete all the assignments within the specified time period. If
a student does not attend the class(es), it is his/her sole responsibility to cover the topic(s) taught during
the period. If a student fails to attend a formal exam, quiz, test, etc. there won’t be any provision for re-
exam.

7. Prescribed Books and References

Text Book
1. M. Morris Mano, Digital Logic and Computer Design Pearson India, 2017.

Reference Books
1. M. Rafiquzzaman, Steven A. McNinch, Digital Logic, John Wiley and Sons, 2019.
2. M. Morris Mano, Digital Design, Prentice Hall of India, 1998.
 Introduction Unit 1
A signal is an electromagnetic or electrical current that carries data from one system or network to
another. In electronics, a signal is often a time-varying voltage that is also an electromagnetic wave
carrying information, though it can take on other forms such as current. There are two main types
of signals used in electronics: analog and digital signals.

1 Analog Signal
An analog signal is time-varying and generally bound to a range(e.g. +12V to -12V), but there is
an infinite number of values within that continuous range. An analog signal uses a given property
of the medium to convey the signal’s information, such as electricity moving through a wire. In an
electrical signal, the voltage, current, or frequency of the signal may be varied to represent the
information. Analog signals are often calculated responses to changes in light, sound, temperature,
position, pressure, or other physical phenomena. When plotted on a voltage vs time graph, an
analog signal produces a continuous curve. There should not be any discrete value changes as
shown in figure 1.

Figure 1: Analog Signal

2 Digital Signal
A digital signal is a signal that represents data as a sequence of discrete values. A digital signal
can only take on one value from a finite set of possible values at a given time. With digital signals,
the physical quantity representing the information can be many things:

➢ Variable electric current or voltage

➢ The phase of polarization of an electromagnetic field
➢ Acoustic pressure
➢ The magnetization of a magnetic storage media

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 Introduction Unit 1
Digital signals are used in all digital electronics, including computing equipment and data
transmission devices. When plotted on a voltage vs time graph, digital signals are of two values
and are usually between 0V and VCC(usually 1.8V, 3.3V, or 5V) as shown in figure 2.

Figure 2: Digital Signal

3 Digital System
A digital system is an interconnection of digital modules and it is a system that manipulates discrete
elements of information that are represented internally in binary form. Now a day’s digital systems
are used in a wide variety of industrial and consumer products such as automated industrial
machinery, pocket calculators’ microprocessors, digital computers, digital watches, TV games,
and signal processing, and so on.

3.1 Characteristics of Digital System

➢ Digital system manipulates discrete elements of information
➢ Digital systems use physical quantities called signals to represent discrete elements
➢ In a digital system, the signals have two discrete values and are therefore said to be binary
➢ A signal in a digital system represents one binary digit called a bit. The bit has a value of
either 0 or 1

4 Analog System
Analog system process information that varies continuously i.e; they process time-varying signals
that can take on any values across a continuous range of voltage, current, or any physical
parameter.

5 Advantages of Digital system over Analog system

1. Ease of programmability
Digital systems can be used for different applications by simply changing the program without
additional changes in hardware.

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 Introduction Unit 1
2. Reduction in cost of hardware
The cost of hardware gets reduced by the use of digital components and this has been possible due
to advances in IC technology. With ICs the number of components that can be placed in a given
area of Silicon is increased with help in cost reduction.

3. High speed
Digital processing of data ensures a high speed of operation which is possible due to advances in
digital signal processing.

4. High Reliability
Digital systems are highly reliable one of the reasons for that is the use of error correction codes.

5. Design is easy
The design of digital systems which requires the use of Boolean algebra and other digital
techniques is easier compared to analog designing.

6. The result can be reproduced easily

Since the output of digital systems unlike analog systems is independent of temperature, noise,
humidity, and other characteristics of components the reproducibility of results is higher in digital
systems than in analog systems.

6 Disadvantages of digital Systems

➢ Use of more energy than analog circuits to accomplish the same task, thus producing more
heat as well
➢ Digital circuits are often fragile, in that if a single piece of digital data is lost or
misinterpreted the meaning of large blocks of related data can completely change
➢ The digital computer manipulates discrete elements of information by means of a binary
code
➢ Quantization errors during analog signal sampling

7 Number Representation
There are several number systems that we normally use, such as decimal, binary, octal,
hexadecimal, etc. Amongst them, we are most familiar with the decimal number system. These
systems are classified according to the values of the base of the number system. The number

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 Introduction Unit 1
system having the value of the base as 10 is called a decimal number system, whereas that with a
base of 2 is called a binary number system. Likewise, the number systems having bases 8 and 16
are called octal and hexadecimal number systems respectively.

Figure 3: Different Number Systems

To define any number system, we have to specify:

➢ The base of the number system such as 2,8,10 or 16

➢ The base decides the total number of digits available in that number system
➢ The first digit in the number system is always zero and the last digit in the number system is
always base-1

7.1 Binary Number System

The binary number has a radix of 2. As r = 2, only two digits are needed, and these are 0 and 1. In
a binary system, weights are expressed as a power of 2.

Figure 4: Binary position values as a power of 2

The leftmost bit, which has the greatest weight is called the Most Significant Bit (MSB). And the
rightmost bit which has the least weight is called the Least Significant Bit (LSB).

7.2 Decimal Number system

The decimal system has ten symbols: 0,1,2,3,4,5,6,7,8,9. In other words, it has a base of 10.

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 Introduction Unit 1

Figure 5: Decimal position value as the power of 10

7.3 Octal Number System

Digital systems operate only on binary numbers. Since binary numbers are often very long, two
shorthand notations, octal and hexadecimal, are used for representing large binary numbers. Octal
systems use a base or radix of 8. It uses the first eight digits of the decimal number system. Thus,
it has digits from 0 to 7.

Figure 6: Octal position value as the power of 8

7.4 Hexa-Decimal Number System

The hexadecimal numbering system has a base of 16. There are 16 symbols. The decimal digits 0
to9 are used as the first ten digits in the decimal system, followed by the letters A, B, C, D, E, and
F, whichrepresent the values 10, 11,12,13,14, and 15 respectively.

Figure 7: Hexadecimal number system as a power of 16

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 Introduction Unit 1
Decimal Binary Octal Hexadecimal

0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

Review Questions
1. Explain different coding methods used to represent data.
2. Describe the characteristics of digital and analog signals?
3. Compare digital and analog systems? Which one is better and why?

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

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 Number System and Codes Unit 2
1 Number System Conversion
It is often required to convert a number in a particular number system to any other number system,
e.g., it may be required to convert a decimal number to binary or octal, or hexadecimal. The reverse
is also true, i.e., a binary number may be converted into a decimal, and so on. The methods of
interconversions are now discussed.
1.1 Decimal-to-binary Conversion
To convert a number in decimal to a number in binary we have to divide the decimal number by 2
repeatedly until the quotient of zero is obtained.
Example Convert 2610 into a binary number.
Division Quotient Generated remainder
26 13 0
2
13 6 1
2
6 3 0
2
3 1 1
2
1 0 1
2
Hence the converted binary number is 110102.
1.2 Decimal-to-octal Conversion
To convert a number in decimal to a number in octal we have to divide the decimal number by 8
repeatedly until the quotient of zero is obtained.
Example Convert 42610 into an octal number
Solution
Division Quotient Generated remainder
426 53 2
8
53 6 5
8
6 0 6
8

Hence the converted octal number is 6528.

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 Number System and Codes Unit 2
1.3 Decimal-to-hexadecimal Conversion
The same steps are repeated to convert a number in decimal to a number in hexadecimal.
Only here we have to divide the decimal number by 16 repeatedly, until the quotient of
zero is obtained.
Example 1.3. Convert 34810 into a hexadecimal number.
Solution
Division Quotient Generated remainder
348 21 12
16
21 1 5
16
1 0 1
16
Hence the converted hexadecimal number is 15C16.
1.4 Binary-to-decimal Conversion
To convert binary, octal, or hexadecimal numbers to decimal numbers we have to keep in mind
that each number systems is a positional number system and has a positional weight.
Example Convert 101102 into a decimal number.
Solution
The binary number given 1 0 1 1 0
Positional weights 43210
The positional weights for each of the digits are written in italics below each digit.

Hence the decimal equivalent number is given as:

4 3 2 1 0
1× 2 + 0 × 2 + 1× 2 + 1× 2 + 0 × 2
= 16 + 0 + 4 + 2 + 0
= 2210.

Hence, we find that here, for the sake of conversion, we have to multiply each bit with
its positional weights depending on the base of the number system.
1.5 Octal-to-decimal Conversion
Example Convert 34628 into a decimal number.
Solution
The octal number given is 3 4 6 2
Positional weights 3210
The positional weights for each of the digits are written in italics below each digit.

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 Number System and Codes Unit 2
Hence the decimal equivalent number is given as:
3 × 83 + 4 × 82 + 6 × 81 + 2 × 80
= 1536 + 256 + 48 + 2
= 184210

1.6 Hexadecimal-to-decimal Conversion

Example Convert 42AD16 into a decimal number.
Solution
The hexadecimal number given is 4 2AD
Positional weights 321 0

The positional weights for each of the digits are written in italics below each digit.
Hence the decimal equivalent number is given as:
4 × 163 + 2 × 162 + 10 × 161 + 13 × 160
= 16384 + 512 + 160 + 13
= 1706910.
2 Fractional Conversion
If the number contains the fractional part we have to deal in a different way when
converting the number from a different number system (i.e., binary, octal, or
hexadecimal) to a decimal number system or vice versa.
Example Convert 1010.0112 into a decimal number.
Solution
The binary number given is 1 0 1 0. 0 1 1
Positional weights 3 2 1 0 -1-2-3
The positional weights for each of the digits are written in italics below each digit. Hence
the decimal equivalent number is given as:

1 × 23 + 0 × 22 + 1 × 21 + 0 × 20 + 0 × 2–1 + 1 × 2–2 + 1 × 2–3

= 8 + 0 + 2 + 0 + 0 + 0.25 + 0.125
= 10.37510.

Example Convert 362.358 into a decimal number.

Solution
The oc ta l number given is 3 6 2. 3 5
Positional weights 2 1 0 -1-2

The positional weights for each of the digits are written in italics below each digit.
Hence the decimal equivalent number is given as:
3 × 82 + 6 × 81 + 2 × 80 + 3 × 8–1 + 5 × 8–2

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 Number System and Codes Unit 2
= 192 + 48 + 2 + 0.375 + 0.078125
= 242.45312510.

Example Convert 42A.1216 into a decimal number.

Solution
The hexadecimal number given is 4 2 A. 1 2
Positional weights 2 1 0 -1-2

The positional weights for each of the digits are written in italics below each digit.
Hence the decimal equivalent number is given as:
2 1 0 –1 –2
4 × 16 + 2 × 16 + 10 × 16 + 1 × 16 + 1 × 16
= 1024 + 32 + 10 + 0.0625 + 0.00390625
= 1066.0664062510.

Example Convert 25.62510 into a binary number.

Solution
Division Quotient Generated remainder
25 12 1
2
12 6 0
2
6 3 0
2
3 1 1
2
1 0 1
2
Therefore, (25)10 = (11001)2
Now, for the fractional part
0.625 0.250 0. 500
×2 ×2 ×2
1.250 0.500 1.000

1 0 1
i.e., (0.625)10 = (0.101)2

Therefore, (25.625)10 = (11001.101)2

Example Convert 34.52510 into an octal number.

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 Number System and Codes Unit 2
Solution
Division Quotient Generated remainder
34 4 2
8
4 0 4
8
Therefore, (34)10 = (42)8

Fractional Part
0.525 0.200 0. 600
×8 ×8 ×8
4.200 1.600 1.200

4 1 1

i.e., (0.525)10 = (0.411)8

Therefore, (34.525)10 = (42.411)8

Example Convert 92.8510 into a hexadecimal number.

Solution
Division Quotient Generated remainder
92 5 12
16
5 0 5
16

Therefore, (92)10=(5C)16

Fractional Part
0. 85 0.60
×16 ×16
13.60 9.60

13 9
i.e., (0.85)10 = (0.D9)16

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 Number System and Codes Unit 2
Therefore, (92.85)10 = (5C.D9)16

2.1 Conversion from a Binary to Octal Number and Vice Versa

We know that the maximum digit in an octal number system is 7, which can be
represented as 1112 in a binary system. Hence, starting from the LSB, we group three
digits at a time and replace them with the decimal equivalent of those groups and
we get the final octal number.
Example Convert 1011010102 into an equivalent octal number.
Solution
The binary number given is 101101010
Starting with LSB and grouping 3 bits 101 101 010
Octal equivalent 5 5 2
Hence the octal equivalent number is (552)8.

Example Convert 10111102 into an equivalent octal number.

Solution
The binary number given is 1 011 110
Starting with LSB and grouping 3 bits 001 011 1 1 0
Octal equivalent 1 3 6
Hence the octal equivalent number is (136)8

Since at the time of grouping the three digits in t h e above example starting from the
LSB, we find that the third group cannot be completed, since only one 1 is left out in
the third group, so we complete the group by adding two 0s in the MSB side. This is
called the left padding of the number with 0.

Now if the number has a fractional part then there will be two different classes of
groups—one for the integer part starting from the left of the decimal point and
proceeding toward the left and the second one starting from the right of the decimal
point and proceeding toward the right. If for the second class, and 1 is left out, we
complete the group by adding two 0s on the right side. This is called right-padding.

Example C o n v e r t 1101.01112 into an equivalent octal number.

Solution
The binary number given is 1101.0111
Grouping 3 bits 001 101. 011 100
Octal equivalent: 1 5 3 4
Hence the octal number is (15.34)8

Example Convert (247)8 into an equivalent hexadecimal number.

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 Number System and Codes Unit 2
Solution
Given octal number is 2 4 7
Binary equivalent is 010 100 111
= 010100111
Forming groups of 4 bits from the LSB 1010 0111
Hexadecimal equivalent A 7

Hence the hexadecimal equivalent of (247)8 is (A7)16

Example Convert (36.532)8 into an equivalent hexadecimal number.

Solution
Given octal number is 3 6 5 3 2
The binary equivalent i s 011 110 101 011 010
=011110.101011010
Forming groups of 4 bits 0001 1110 . 1010 1101
Hexadecimal equivalent 1 E . A D
Hence the hexadecimal equivalent of (36.532)8 is (1E.AD)16.

3 Complements
Complements are used in digital computers for simplifying the subtraction operation
and for logical manipulations. There are two types of complements for each number
system of base - r:
1. The radix complements or r’s complement
2. The diminished radix complements or (r-1)’s complement
When we deal with a binary system the value of r is 2 and hence the complements
are 2’s and 1’s complements. Similarly, for a decimal system, the value of r is 10 and
we get 10’s and 9’s complements. With the same logic if the number system is octal
we get 8’s and 7’s complement, while it is 16’s and 15’s complements for t h e
hexadecimal system.
3.1 The r’s Complement or Radix Complement
If a positive number N is given in base r with an integer part of n digits, the r’s complement of N
is given as:
𝑟 𝑛 − 𝑁 𝑓𝑜𝑟 𝑁 ≠ 0
r's complement = { }
0 𝑓𝑜𝑟 𝑁 = 0

Example find 10’s complement of 5252010

Here, base of digit (r) = 10

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 Number System and Codes Unit 2
Integer part of digits (n) = total number of positive digits = 5
Given number (N) = 52520

Therefore, 10’s complement = 𝑟 𝑛 − 𝑁 = 105 − 52520 = 1000000 − 52520 = 47480

Example Find 10’s complement of 0.324510
0
Since the number of digits in the integer part of the number is n = 0, we have 10 = 1.

0
The 10’s complement of (0.3245)10 is 10 – 0.3245 = 0.6755.
Similarly, for 23.324
2
The 10’s complement of (23.324)10 is 10 – 23.324 = 76.676.

If we consider a binary system then r = 2

5
The 2’s complement of (10110)2 is (2 )10–(10110)2 = (100000 – 10110)2 = 01010.
Here, r = 2, n = 5, and N = 10110 in binary
0
The 2’s complement of (0.1011)2 is (2 )10–(0.1011)2 = (1 – 0.1011)2 = 0.0101.
Now if we consider an octal system, then r = 8.
4
The 8’s complement of (2450)8 is (8 )10 – (2450)8
= (409610 – 24508)
= (409610 – 132010)
= 277610
= 53308

If we consider a hexadecimal system, then r = 16.

4
The 16’s complement of (4A30)16 is (16 )10 – (4A30)16
= (6553610 – 4A3016)

= (6553610 – 1899210)

= 4654410

= B5D016

3.2 The (r–1)’s Complement or diminished radix complements

If a positive number N is given in base r with an integer part of n digits and a fraction
part of m digits, then the (r-1)’s complement of N is given as
𝑟 𝑛 − 𝑟 −𝑚 − 𝑁 𝑓𝑜𝑟 𝑁 ≠ 0
(𝑟 − 1)′𝑠 = { }
0 𝑓𝑜𝑟 𝑁 =0
The following examples will clarify the definition.
Example Find 9’s complement of (23450)10

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 Number System and Codes Unit 2
Here, r = 10, n = 5, m = 0 (no fractional part) and N= (23450)10
The 9’s complement is given by 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁
Therefore, (23450)10 is 105 – 100 – 23450 = 76549.
Example Find 9’s complement of (0.3245)10
Here, r = 10, n = 0(number of integer part), m = 4 (number of fractional part) and N=
(0.3245)10
The 9’s complement is given by 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁
Therefore, (0.3245)10 is 100 – 10-4 – 0.3245 = 0.6754.
Example Find 9’s complement of (23.324)10
Here, r = 10, n = 2(number of integer part), m = 3 (number of fractional part) and N=
(23.324)10
The 9’s complement is given by 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁
Therefore, (23.324)10 is 102 – 10-3 – 23.324= 76.675

Example Find 1’s complement of (10110)2

Now if we consider a binary system, then r = 2, i.e., (r – 1) = 1.
Here, r = 2, n = 5(number of integer part), m = 0 (number of fractional part) and N=
(10110)2
The 1’s complement is given by 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁
Therefore, (10110)2 is (25 – 2-0)10– (10110)2 = (32-1)10-(10110)2 =11111 – 10110 = 01001

Example Find 1’s complement of (0.0110)2

Here, r = 2, n = 0(number of integer part), m = 4 (number of fractional part) and N=
(0.1011)2
The 1’s complement is given by 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁
Therefore, (0.0110)2 is (20 – 2-4)10– (0.1011)2 = (1-0.0625)10-(0.1011)2 =0.9375 – (0.0110)2
= 0.1111-0.0110= 0.1001
Note
➢ The 10’s complement of a decimal number can be formed by leaving all least significant
zeros unchanged, subtracting the first zero least significant digit from 10, and then
subtracting all other higher significant digits from 9.
➢ 2’s complement can be formed by leaving all least significant zeros and the first non-zero
digit unchanged, and then replacing 1’s by 0’s and 0’s by 1’s in all other higher significant
digits.
➢ 9’s complement of a decimal number is formed simply by subtracting every digit from 9
➢ 1’s complement of a binary number is formed simply by changing 1’s to 0’s and 0’s to 1’s.

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➢ r's complement can be obtained from the (r-1)’s complement after the addition of r-m to the
least significant digit.

4 Binary Subtraction
Binary subtraction is also carried out in a similar method to decimal subtraction. Binary
subtraction between two numbers can be performed in three ways.
1. the direct method,
2. the r’s complement method, and
3. the (r – 1)’s complement method.
4.1 Direct Method
In this method, we borrow a 1 from a higher significant position when the minuend digit
is smaller than the corresponding subtrahend digit.
Example Using the direct method to perform the subtraction 1001 – 1000.
Solution
1 0 0 1
(–) 1 0 0 0
0 0 0 1
4.2 Subtraction with r’s Complements
When subtraction is implemented in a digital system, complement methods is found to be more
efficient as it uses only complement hardware and adder unit.
The subtraction of two positive numbers (M — N), both of base r, may be done as follows:
1. Add the minuend M to the r’s complement of the subtrahend N.
2. Inspect the result obtained in step 1 for an end carry:
a. If an end carry occurs, discard it.
b. If an end carry does not occur, take the r’s complement of the number obtained in step
1 and place a negative sign in front.
Example Using 10’s complement, subtract 72532 – 3250.
Solution
Here, M = 72532, N= 3250

Now, r’s complement of N = 𝑟 𝑛 − 𝑁 𝑓𝑜𝑟 𝑁 ≠ 0

= 105-03250 = 96750
Now, M + N (r’s component) = 72530 + 96750

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= 169282
Here, 1 is end carry value so it is discarded. Then the required answer = 69282

Example Using 10’s complement subtracts 3250-72532

Here, M = 3250, N= 72532

Now, r’s complement of N = 𝑟 𝑛 − 𝑁 𝑓𝑜𝑟 𝑁 ≠ 0

= 105-72532 = 27468
Now, M + N(r’s component) = 03250 + 27468
= 30718
Here, no end carry present so take r’s complement i.e. r’s complement of M + N(r’s component)
is 105-30718 = 69282
Thus, the required solution is = -69282

Example using 2’s complement performs 1010100-1000100

Here, M= 1010100, and N= 1000100
Now, r’s complement of N, = (27)10 - (1000100)2 = (10000000)2 - (1000100)2 = 1111002
Now, M+Nr’s = 1010100 + 111100 = 10010000
Here, 1 is end carry so it is discarded. Then required answer is 100002

Example using 2’s complement performs 1000100 - 1010100

Here, M= 1000100, and N= 1010100
Now, r’s complement of N, = (27)10-(1010100)2 = (10000000)2-(1010100)2 = 1011002
Now, M+Nr’s = 1000100 + 101100 = 11100002
Here, no end carry present so takes r’s complement of M+Nr’s = (27)10 - 11100002
= (10000)2
Therefore, required solution is (-10000)2
Subtraction Using (r-1)’s Complement

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The subtraction of two positive numbers M-N, both of base r may be done as follows.
1. Add the minuend M to (r-1)’s complement of N
2. Inspect the result obtained in step 1
a. If an end carry occurs, add 1 to the least significant digit (end – around carry). The
result is answer
b. If an end carry doesn’t occurs, take (r-1)’s complement of number obtained in step
1 and placed negative (-ve) sign.
Subtract using (r-1)’s complement
Example using (r-1)’s complement performs 72532-3250
Here, M = 72532, N= 3250

Now, (r-1)’s complement of N = 𝑟 𝑛 − 𝑟 −𝑚 − 𝑁 𝑓𝑜𝑟 𝑁 ≠ 0

105-100-03250 = 96749
Now, M + N (r-1’s complement) = 72532 + 96749
= 169281
Here, end carry is present so, required answer is 169281 + 1= 69282

Example using (r-1)’s complement performs 1010100-1000100

Here, M= 1010100, and N= 1000100
Now, (r-1)’s complement of N = (27- 20)10 - (1000100)2
= (1111111)2 - (1000100)2
= 01110112
Now, M+N(r-1)’s = 1010100 + 0111011 = 100011112
Here, end carry is present so, the required answer is 0001111 + 1 = 100002

Example using (r-1)’s complement performs 1000100-1010100

Here, M= 1000100, and N= 1010100
Now, (r-1)’s complement of N = (27- 20)10 - (1010100)2
= (1111111)2 - (1000100)2
= 01010112

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Now, M+N(r-1)’s = 1000100 + 0101011 = 11011112
Here, no end carry is present so, (r-1)’s complement of M+N(r-1)’s is
(27- 20)10 – (1101111)2 = (1111111)2-(1101111)2
= (10000)2
Therefore, the required solution is (-10000)2

5 Binary Coding System

Computers and other digital circuits process data in binary format. Various binary codes
are used to represent data which may be numeric, alphabetic or special characters.
Electronic digital systems use signals that have two distinct values and circuit elements that have
two stable states. Binary code is the code used in digital computers based on a binary number
system in which there are only two possible states ‘0’ and ‘1’ usually called ‘OFF’ and ‘ON’. It is
possible to arrange ‘n’ bits to 2n possible states.
Binary codes are of two types
➢ Weighted Binary codes
➢ Non-weighted codes
5.1 Weighted Binary Codes
If each position of a number represents a specific weight then the coding scheme is called
weighted binary code. In such coding, the bits are multiplied by their corresponding individual
weight, and then the sum of these weighted bits gives the equivalent decimal digit.

Binary Coded Decimal (BCD) Code or 8421 Code

Binary codes for decimal digits require a minimum of 4 bits. Numerous different codes can be
obtained by arranging 4 or more bits in 10(ten) distinct possible combinations. BCD is the straight
assignment of binary equivalent.

The code is also known as 8-4-2-1 code. This is because 8, 4, 2, and 1 are the weights of the four
bits of the BCD code. The weight of the LSB is 20 or 1, that of the next higher order bit is 21 or 2,
that of the next higher order bit is 22 or 4, and that of the MSB is 23 or 8. Since four binary bits are
used the maximum decimal equivalent that may be coded is 1510 (i.e., 11112). But the maximum
decimal digit available is 910. Hence the binary codes 1010, 1011, 1100, 1101, 1110, 1111,
representing 10, 11, 12, 13, 14, and 15 in decimal are never being used in BCD code. So these six
codes are called forbidden codes and the group of these codes is called the forbidden group in BCD
code.

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Example Give the BCD equivalent for the decimal number 589.

Solution
The decimal number is 589
BCD code is 0101 1000 1001

Hence, (589)10 = (010110001001)BCD

Example Give the BCD equivalent for the decimal number 69.27.
Solution.
The decimal number 69.27
BCD code is 0110 1001 . 0010 0111

Hence, (69.27)10 = (01101001.00100111)BCD

84-2-1 Code
It is also possible to assign negative weights to decimal codes, as shown by the 84-
2-1 code. In this case, the bit combination 0101 is interpreted as the decimal digit 3, as
obtained from 0 × 8 + 1 × 4 + 0 × (–2) + 1 × (–1) = 3. This is a self-complementary
code, that is, the 9’s complement of the decimal number is obtained just by changing
the 1s to 0s and 0s to 1s, or in effect by getting the 1’s complement of the
corresponding number. For example, if we change the 1s to 0s and 0s to 1s in the previous
example we have 1010, which is interpreted as decimal 6, as obtained from 1 × 8 + 0
× 4 + 1 × (–2) + 0 × (–1) = 6. And 6 is the 9’s complement of 3. This property is
useful when arithmetic operations are done internally with decimal numbers (in a binary
code) and subtraction is calculated by means of 9’s complement.
2421 Code
Another weighted code is 2421 code. The weights assigned to the four digits are 2, 4,
2, and 1. The 2421 code is the same as that in BCD from 0 to 4; however, it varies
from 5 to 9. For example, in this case the bit combination 0100 represents decimal 4;
whereas the bit combination 1101 is interpreted as the decimal 7, as obtained from 2
× 1 + 1 × 4 + 0 × 2 + 1 × 1 = 7. This is also a self-complementary code, that is, the
9’s complement of the decimal number is obtained by changing the 1s to 0s and 0s to 1s.
5.2 Non-weighted Codes
These codes are not positionally weighted. It basically means that each position
of the binary number is not assigned a fixed value. Excess-3 codes and Gray codes
are such non-weighted codes.

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Excess-3 Code
A decimal code that has been used in some old computers is Excess-3 code. This is a non-
weighted code. This code assignment is obtained from the corresponding value of 4-bit
binary code after adding 3 to the given decimal digit. Here the maximum value may
be 11002. Since the maximum decimal digit is 9 we have to add 3 to 9 and then get the
BCD equivalent. Like 84-2-1 and 2421 codes Excess-3 is also a self-complementary code,
that is, the 9’s complement of the decimal number is obtained by changing the 1s to 0s
and 0s to 1s. This self-complementary property of the code helps considerably in
performing subtraction operation in digital systems.

Example Convert (367)10 into its Excess-3 code.

Solution
The decimal number is 3 6 7
Add 3 to each bit +3 +3 +3
Sum 6 9 10

Converting the above sum into 4-bit binary equivalent, we have a 4-bit binary
equivalent of 0110 1001 1010
Hence, the Excess-3 code for (367)10 = 0110 1001 1010

Example Convert (58.43)10 into its Excess-3 code.

Solution

The decimal number is 5 8 4 3

Add 3 to each bit +3 +3 +3 +3
Sum 8 11 7 6

Converting the above sum into 4-bit binary equivalent, we have a 4-bit binary
equivalent of 1000 1011 0111 0110
Hence, the Excess-3 code for (367)10 = 10001011.01110110
Table 1 Binary Code for Decimal Numbers

Decimal (BCD)
digit 8421 84-2-1 2421 Excess-3
0 0000 0000 0000 0011

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1 0001 0111 0001 0100
2 0010 0110 0010 0101
3 0011 0101 0011 0110
4 0100 0100 0100 0111
5 0101 1011 1011 1000
6 0110 1010 1100 1001
7 0111 1001 1101 1010
8 1000 1000 1110 1011
9 1001 1111 1111 1100

Gray Code (The Reflected Code)

The gray code belongs to a class of codes called minimum change codes, in which only one bit in
the code changes when moving from one code to the next. The Gray code is a non-weighted code,
as the position of bit does not contain any weight. The gray code is a reflective digital code which
has the special property that any two subsequent numbers codes differ by only one bit. This is also
called a unit- distance code. In digital Gray code has got a special place.
To obtain a different reflected code, one can start with any bit combination and proceed to
obtain the next bit combination by changing only one bit from 0 to 1 or 1 to 0 in any desired
random fashion, as long as two numbers do not have identical code assignments. The Gray
code is not a weighted code.
Table 2 Reflected Code

Reflected Code Decimal

Equivalent
m4 0000 0
m3 0001 1
0011 2
m2 0010 3
0110 4
0111 5
0101 6
m1 0100 7
1100 8
1101 9
1111 10
m5 1110 11
1010 12
m6 1011 13
m7 1001 14
1000 15

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Conversion of a Binary Number into Gray Code
Any binary number can be converted into equivalent Gray code by the following
steps:
➢ The MSB of the Gray code is the same as the MSB of the binary number;
➢ The second bit next to the MSB of the Gray code equals the Ex-OR of the
MSB and the second bit of the binary number; it will be 0 if there are same
binary bits or it will be 1 for different binary bits;
➢ The third bit for Gray code equals the exclusive-OR of the second and third
bits of the binary number, and similarly, all the next lower-order bits follow the
same mechanism.
Example Convert (101011)2 into Gray code.
Step 1. The MSB of the Gray code is the same as the MSB of the binary number.

1 0 1 0 1 1 Binary

1 Gray

Step 2. Perform the ex-OR between the MSB and the second bit of the binary.
The result is 1, which is the second bit of the Gray code.

1 ⨁ 0 1 0 1 1 Binary

1 1 Gray
Step 3. Perform the ex-OR between the second and the third bits of the binary. The
result is 1, which is the third bit of the Gray code.

1 0 ⨁ 1 0 1 1 Binary

1 1 1 Gray
Step 4. Perform the ex-OR between the third and the fourth bits of the binary.
The result is 1, which is the fourth bit of the Gray code.
1 0 1 ⨁ 0 1 1 Binary

1 1 1 1 Gray

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Step 5. Perform the ex-OR between the fourth and the fifth bits of the binary.
The result is 1, which is the fifth bit of the Gray code.
1 0 1 0 ⨁ 1 1 Binary

1 1 1 1 1 Gray
Step 6. Perform the ex-OR between the fifth and the sixth bits of the binary.
The result is 0, which is the last bit of the Gray code.
1 0 1 0 1 ⨁ 1 Binary

1 1 1 1 1 0 Gray
After completing the conversion, the Gray code of binary 101011 is 111110.

Example 2.6. Convert (564)10 into Gray code.

Solution
Step 1. Convert the decimal 564 into equivalent binary.
Decimal number 564
Binary number 1000110100
Step 2. Convert the binary number into equivalent Gray code.
1 ⨁ 0 ⨁ 0 ⨁ 0⨁ 1 ⨁ 1 ⨁ 0 ⨁ 1 ⨁ 0 ⨁ 0 Binary

1 1 0 0 1 0 1 1 1 0 Gray

Conversion of Gray Code into a Binary Number

Any Gray code can be converted into an equivalent binary number by the following steps:
➢ the MSB of the binary number is the same as the MSB of the Gray code;
➢ the second bit next to the MSB of the binary number equals the Ex-OR of the
MSB of the binary number and the second bit of the Gray code; it will be 0 if there
are some binary bits or it will be 1 for different binary bits;
➢ the third bit for the binary number equals the exclusive-OR of the second bit of the
binary number and t h e third bit of the Gray code, and similarly, all the next
lower-order bits follow the same mechanism.

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Example Convert the Gray code 101101 into a binary number.
Solution
Step 1. The MSB of the binary number is the same as the MSB of the Gray code.

1 0 1 1 0 1 Gray

1 Binary

Step 2. Perform the ex-OR between the MSB of the binary number and the second bit
of the Gray code and so on till last bit

1 0 1 1 0 1 Gray
⨁ ⨁ ⨁ ⨁ ⨁

1 1 0 1 1 0 Binary

After completing the conversion, the binary number of the Gray code 101101 is 110110
Alphanumeric
An alpha-numeric code is a binary code of a group of elements consisting of ten decimal digits.
The 26 letter of alphabets and certain number of special symbols such as #,& etc. The total number
of elements in an alpha-numeric code is greater than 36. It must be coded with the minimum of 6
bits. Two mostly used alpha-numeric code ra ASCII and EBCDIC.
ASCII (American Code for Information Interchange) Code
The ASCII code are widely used alpha-numeric code. It is basically a 7-bit code since it can create
27 = 128-bit pattern. The ASCII code can be used to encode both the lower case and upper-case
characters of alphabet and some symbol ‘#’, ‘&’ etc.
A→ 65 a→97 0→48 blank→32 and so on.
EBCDIC (Extended Binary Coded Decimal Interchange) Code
It is an 8-it alpha-numeric code. It can create 28 = 256 different bit patterns. EBCDIC cade can
encode all the symbols and characters found in ASCII code. It also encodes many other symbols
which are not encoded by ASCII code. In fact, many of the bit patterns in EBCDIC code are
unassigned.
A→193 a→129 0→240 blank → 64

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Character 7-bit 8-bit
ASCII code EBCDIC code
A 1000001 11000001
B 1000010 11000010
C 1000011 11000011
D 1000100 11000100
E 1000101 11000101
F 1000110 11000110
G 1000111 11000111
H 1001000 11001000
I 1001001 11001001
J 1001010 11010001
K 1001011 11010010
L 1001100 11010011
M 1001101 11010100

Instruction Code
An instruction code is a group of bits that instruct the computer to perform the specific operations.
It is divided into two parts: op-code and operands.
The most basic part of an instruction code is its operation part called as “op-code”. The operation
code of an instruction is a group of bits that defines particular operation add, substract, multiply,
divide etc. the number of bits required for the operation code of an instruction depends on the total
number of operation available in the computer. The operation code must consist of atleast n bits
for given 2n distinct operators.
Consider a computer with 64 distinct operation. One of then is add operation. The operation code
consist of six(6) bits with the bit configuration of “110010” assigned to the add operation. When
this operation is decoded in the control unit, the computer issue control signal to reas operatnd
from memory and add operand to the processor resistance.
Solved Problems
Example Encode the following decimal numbers in BCD code:
(a) 45 (b) 273.98 (c) 62.905
Solution
(a) Decimal number is 4 5
BCD code is 0100 0101
Hence the BCD coded form of 4510 is 0100 0101

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(b) Decimal number is 2 7 3 9 8
BCD code is 0010 0111 0011 1001 1000 Hence the
BCD coded form of
273.9810 is 0010 0111 0011.1001 1000

(c) Decimal number is 6 2 9 0 5

BCD code is 0110 0010 1001 0000 0101
Hence the BCD coded form of 62.90510 is 0110 0010.1001 0000 0101

Example W r i t e down the decimal numbers represented by the following BCD

codes:
(a) 100101001 (b) 100010010011 (c) 01110001001.10010010
Solution

(a) BCD code is 1 0010 1001

By padding up the first number with 3 zeros 0001 0010 1001
Decimal number is 1 2 9
Hence the decimal number is 129.
(b) BCD code is 1000 1001 0011
Decimal number is 8 9 3
Hence the decimal number is 893.
(c) BCD code is 011 1000 1001 1001 0010
By padding up the first number with 1 zero 0011 1000 1001 1001 0010
Decimal number is 3 8 9 9 2
Hence the decimal number is 389.92.
Example Encode the following decimal numbers to Excess-3 code:
(a) 38 (b) 471.78 (c) 23.105
Solution
(a) Decimal number is 3 8
BCD code is 0011 1000
Now adding 3 +0011 +0011
Excess-3 code is 0110 1011
Hence the Excess-3 coded form of 3810 is 0110 1011

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(b) Decimal number is 4 7 1 7 8

BCD code is 0100 0111 0001 0111 1000
Now adding 3 +0011 +0011 +0011 +0011 +0011
Excess-3 code is 0111 1010 0100 1010 1011

Hence the Excess-3 coded form of 471.7810 is 0111 1010 0100.1010 1011
(c) Decimal number is 2 3 1 0 5
BCD code is 0010 0011 0001 0000 0101
Now adding 3 +0011 +0011 +0011 +0011 +0011
Excess-3 code is 0101 0110 0100 0011 1000

Hence the Excess-3 coded form of 23.10510 is 0101 0110.0100 0011 1000
Example Express the following Excess-3 codes as decimal numbers:
(a) 0101 1011 1100 0111 (b) 0011 1000 1010 0100 (c) 0101 1001 0011
Solution
(a) Excess-3 code is 0101 1011 1100 0111
Subtracting 3 from each digit 0011 –0011 –0011 –0011
BCD number is 0010 1000 1001 0100
Decimal number is 2 8 9 4
Hence the decimal number is 2894.
(b) Excess-3 code is 0011 1000 1010 0100
Subtracting 3 from each digit 0011 –0011 –0011 –0011
BCD number is 0000 0101 0111 0001
Decimal number is 0 5 7 1
Hence the decimal number is 571.
(c) Excess-3 code is 0101 1001 0011
Subtracting 3 from each digit 0011 –0011 –0011

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BCD number is 0010 0110 0000
Decimal number is 2 6 0
Hence the decimal number is 260.

Example Encode the following decimal numbers to Gray codes:

(a) 61 (b) 83 (c) 324(d) 456
Solution
(a) Decimal number is 61
Binary code is 111101
Gray code is 100011
(b) Decimal number is 83
Binary code is 1010011
Gray code is 1111010
(c) Decimal number is 324
Binary code is 101000100
Gray code is 111100110
(d) Decimal number is 456
Binary code is 111001000
Gray code is 100101100

Example Express the following Gray codes as binary numbers:

Solution

(a) 10111 (b) 0110101 (c) 10100011

(d) 100111100 (e) 101010001 (f ) 10110010101
a. Gray code is 10111
Binary number is 11010

Example Express the following decimal numbers as 2421 codes:

a. 168 b. 254 c. 6735 d.1973 e.9021

Solution

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 Number System and Codes Unit 2

(a) Decimal number given is 1 6 8

Equivalent 2421 code is 0001 1100 1110
(b) Decimal number given is 2 5 4
Equivalent 2421 code is 0010 1011 0100
(c) Decimal number given is 6 7 3 5
Equivalent 2421 code is 1100 1101 0011 1011
(d) Decimal number given is 1 9 7 3
Equivalent 2421 code is 0001 1111 1101 0011
(e) Decimal number given is 9 0 2 1
Equivalent 2421 code is 1111 0000 0010 0001

Review Questions
1. Convert the following decimal numbers to binary: 12.0625, 104 , 673.23, and 1998. 1-5.
2. Convert the following binary numbers to decimal: 10.10001, 101110.0101, 1110101.110,
1101101.111
3. Convert the following numbers from the given base to the bases indicated
(a) decimal 225.225 to binary, octal, and hexadecimal
(b) binary 11010111.110 to decimal, octal, and hexadecimal
(c) octal 623.77 to decimal, binary, and hexadecimal
(d) hexadecimal 2AC5.D to decimal, octal, and binary
4. Obtain the l’s and 2’s complement of the following binary numbers: 1010101, 0111000,
0000001, 10000, 00000.
5. Perform the subtraction with the following decimal numbers using (1) 10’s complement
and (2) 9’s complement. Check the answer by straight subtraction.
a. 5250 - 321
b. 753 – 864
c. 3570 - 2100
d. 20 – 1000
6. Represent the decimal number 8620 (a) in BCD, (b) in excess-3 code, (c) in 2, 4, 2, 1 code,
and (d) as a binary number.
7. Convert the following decimal numbers to the indicated bases.
a. 7562.45 to octal
b. 1938.257 to hexadecimal

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 Number System and Codes Unit 2
c. 175.175 to binary
8. Convert the following hexadecimal number to decimal and octal numbers
a. 0FFF
b. 3FFF
9. Subtract (1010100 – 1000100) using 1’s complement.
10. Using 2’s complement, subtract (1000100-1010100).
11. Why is Gray code called the reflected code? Explain
12. What are the different types of Binary codes? Explain each in brief
13. How can you find the r’s complement using (r-1)’s complement? Explain with example
14. Excess 3 code is self-complementary code, verify the statement?
15. What do you mean by the Gray code? What are its application?
16. What is decimal code? Differentiate between BCD and excess-3 code.

Declaration: This document is prepared only for academic purposes, contents from different
sources are subject to their own copyright.

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 Boolean Algebra and Logic Gates Unit 3
Binary logic deals with variables that have two discrete values—1 for TRUE and 0 for
FALSE. A simple switching circuit containing active elements such as a diode and
transistor can demonstrate the binary logic, which can either be ON (switch closed) or
OFF (switch open).
The switching functions can be expressed with t h e Boolean equation. Boolean
Algebra, was invented by the mathematician George Boole in 1854. Boolean Algebra
deals with the rules by which logical operations are carried out.
1 Basic Definition
Boolean algebra may be defined with a set of elements, a set of operators, and a number of
assumptions and postulates. A set of elements refers to the collection of objects having common
properties.

➢ If S denotes a set, and X and Y are certain objects, then X ∈ S denotes X is

a member of set S, whereas Y ∉ S denotes Y is not a member of set S.
➢ A binary operator defined on a set S of elements is a rule, that assigns to each
pair of elements from S. If X*Y = Z, then ‘*’ is a binary operator if it specifies
a rule for finding Z from the objects (X,Y) if X ,Y and Z are of same set S. The
‘*’ cannot be a binary operator if X and Y are members of set S but Z is not
from the same set S.
1.1 Postulates
Boolean algebra is an algebraic structure defined on a set of elements (Boolean system) together
with two binary operators “ + (OR) ”, and “ • (AND) ” and unary operator “ ' (NOT) ” , provided
the following postulates are satisfied
1. Closer: A set S is closed with respect to a binary operator if, for every pair of elements of
S, the binary operator specifies a rule for obtaining a unique element of S.
For example, the set of natural numbers N = {1, 2, 3, 4,...} is closed with respect to the
binary operator plus (+) by the rules of arithmetic addition, since for any a, b ∈ N we obtain
a unique c ∈ N by the operation a + b = c. The set of natural numbers is not closed with
respect to the binary operator minus (-) by the rules of arithmetic subtraction because 2 −
3 = − 1 and 2, 3 ∈ N, while (−1) ∉ N.
2. Associative Law: A binary operator * on a set S is said to be associated
whenever (A*B)*C = A*(B*C) for all A,B,C ∈ S.
3. Commutative Law: A binary operator * on a set S is said to be commutative
whenever A*B = B*A for all A,B ∈ S

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 Boolean Algebra and Logic Gates Unit 3
4. Identity Element: A set S is to have an identity element with respect to a
binary operation * on S if there exists an element E  S with the property
E*A = A*X = A.
Example: The element 0 is an identity element with respect to the binary
operator + on the set of integers I = {.... –4, –3, –2, –1, 0, 1, 2, 3, 4, } as
A + 0 = 0 + A = A.
Similarly, element 1 is the identity element with respect to the binary operator ×
as A × 1 = 1 × A = A.
5. Inverse: If a set S has the identity element E with respect to a binary operator
*, there exists an element B  S, which is called the inverse, for every A  S,
such that A*B = E.

Example: In the set of integers I with E = 0, the inverse of an element A is (-

A) since A + (–A) = 0.

6. Distributive Law: If * and (.) are two binary operators on a set S, * is said
to be distributive over (.), whenever A*(B.C) = (A*B).(A*C).

2 Basic Rules in Boolean Algebra

In Boolean algebra, certain rules that are widely followed are:

1. Capital letters are used to represent variable and functions

2. The complement of variables are represented by a bar over letters or oblique, near letter
e.g. (𝐴̅ 𝑜𝑟 𝐴′ ).

3. The logical “AND” operation of two variables is represented by “dot”(.).

4. The logical “OR” operation of two variables is represented by “plus” (+).

5. The addition of variables in Boolean algebra involves the variable either a zero or one.

e.g. 0+0=0, 0+1=1, 1+0=0, and 1+1=1

6. Multiplication in Boolean algebra follows the same basic rules that are in binary
operations. e.g. 0.0=0, 0.1=0, 1.0=0, 1.1=1

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3 Principle of Duality
Postulates of Boolean algebra are found in pairs; one part may be obtained from the other if the
binary operators and the identity elements are interchanged. It states that “Every algebraic
expression deducible from the postulates of Boolean algebra remains valid if the operators and
identity elements are interchanged”. This means one expression can be obtained from the
other in each pair by interchanging every element i.e., every 0 with 1, every 1 with 0,
as well as interchanging the operators i.e., every (+) with (.) and every (.) with (+).
This important property of Boolean algebra is called principle of duality. In summary,

1. We can change each AND operation to an OR operation

2. We can change each OR operation to an AND operation
3. We can complement any 1 or 0 appearing in the expression

3.1 DeMorgan's Theorem

Two theorems that were proposed by DeMorgan play important parts in Boolean algebra.
1. The first theorem states that the complement of a product is equal to the sum
of the complements. That is, if the variables are A and B, then
(A.B) = A+ B

2. The second theorem states that the complement of a sum is equal to the product
of the complements. In equation form, this can be expressed as
(A + B) = A. B

The complements of Boolean logic function or a logic expression may be simplified or

expanded by the following steps of DeMorgan’s theorem.

a. Replace the operator (+) with (.) and (.) with (+) given in the expression.

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 Boolean Algebra and Logic Gates Unit 3
b. Complement each of the terms or variables in the expression.
DeMorgan’s theorems are applicable to any number of variables. For three variables
A, B, and C, the equations are
(A.B.C) = A + B + C and
(A + B + C) = A.B.C
4 Some Important Rules of Boolean Function
Name OR Form AND Form
Identity Law (a) A + 0 = A (b) A.1 = A
Inverse Law (a) A + A = 1 (b) A.A = 0
Impotence Law (a) A + A = A (b) A.A = A
Null Law (a) A + 1 = 1 (b) A.0 = 0
Double Inverse (A) = A
Commutative (a) A + B = B + A (b) A.B = B.A
Associative (a) A + (B + C) = (A + B) + C (b) A.(B.C) = (A.B).C
Distributive (a) A(B + C) = A.B + A.C (b) A + B.C = (A + B).(A + C)
DeMorgan (a) (A + B) = A.B (b) (A.B) = A + B
Absorption (a) A + A.B = A (b) A.(A + B) = A

4.1 Operator Precedence

The operator precedence for evaluating Boolean expressions is

1. Parentheses→()
2. NOT→'
3. AND→.
4. OR→+
In other words, the expression inside the parentheses must be evaluated before all other operations.
The next operation that holds precedence is the complement, then follows the AND, and finally
the OR.
Example: (a+b.c).d' → here we first evaluate ‘b.c’ and OR it with ‘a’ followed by ANDing with
complement of ‘d’.
Example Find the dual of the following Boolean Expression
1. A + AB = A
2. A + 𝐴̅B = A + B
3. A+𝐴̅ =1
4. (A+B) (A+C) = A+B+C

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Solution

S. N Given Expression Dual of given Expression

1. A + AB =A A.(A+B) =A
2. A + 𝐴̅B = A + B A.( 𝐴̅ + 𝐵) = 𝐴. 𝐵
3. A+𝐴̅ =1 A.𝐴̅ =1
4. (A+B) (A+C) = A+B+C (A.B)+(A.C) = A(B+C)

5 Digital Logic Gates

Logic gates are the basic building blocks of any digital system. It is an electronic circuit having
one or more than one inputs and only one output. The relationship between the input and output is
based on a certain logic. As Boolean functions are expressed in terms of AND, OR, and
NOT operations, it is easier to implement the Boolean functions with these basic types of
gates. However, for all practical purposes, it is possible to construct other types of logic
gates. The following factors are to be considered for construction of other types of
gates.
➢ The feasibility and economy of producing the gate with physical parameters.
➢ The possibility of extending to more than two inputs.
➢ The basic properties of the binary operator such as commutability and associability.
➢ The ability of the gate to implement the Boolean functions alone or in conjunction with
other gates
Logic Gates

Basic Gate Universal Gate Special Gates

- And gate - NAND gate - EX-OR gate
- Or gate - NOR gate - EX-NOR
- Not gate gate

5.1 Truth Table

The operation of a logic gate can be best understood with the help of a table called truth table. The
truth table consist of all the possible combination of the inputs and the corresponding states of
output of a logic gate.

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5.2 Boolean Expression
The relationship between the inputs and the outputs of a gate can be expressed mathematically by
means of the Boolean expression.

Name Graphic Symbol Algebraic Function Truth Table

A B F
0 0 0
AND F = AB 0 1 0
1 0 0
1 1 1

A B F

0 0 0
OR F = A + B 0 1 1
1 0 1
1 1 1

A F
Inverter F = A 0 1
or NOT 1 0

A F
Buffer F = A 0 0
1 1

A B F

0 0 1
NAND F = (AB) 0 1 1
1 0 1
1 1 0

A B F

0 0 1
NOR F = (A + B) 0 1 0
1 0 0
1 1 0

A B F

0 0 0
Exclusive-OR F = AB + AB 0 1 1
(XOR) = A  B 1 0 1
1 1 0

Equivalence A B F

Or F = AB + AB 0 0 1
Exclusive-NOR = A B 0 1 0
(XNOR) 1 0 0
1 1 1

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6 Introduction of Universal Gate
NAND gates and NOR gates are called universal gates or universal building blocks, as any type
of gates or logic functions can be implemented by these gates. NAND and NOR gates are called
Universal gates. All fundamental gates (NOT, AND, OR) can be realized by using either only
NAND or only NOR gate. A universal gate provides flexibility and offers enormous advantage to
logic designers.

6.1 NAND Gate as a universal gate

A NAND gate is expressed mathematically as
Q = ̅̅̅̅̅
𝐴. 𝐵

Hence, we have to bring the given Boolean expression into this form.

A. NOT gate using NAND gate

When input A = B
Q = ̅̅̅̅̅
𝐴. 𝐵 = ̅̅̅̅̅
𝐴. 𝐴
We know, A.A = A
Therefore, Q = 𝐴̅
B. AND gate using NAND gate
The Boolean expression for an AND gate is Q = A.B
̿̿̿̿̿
Taking double inversion of RHS we have Q = 𝐴. 𝐵

C. OR gate using NAND gate

The Boolean expression for OR gate is Q = A+B
Taking double inversion on RHS we get, Q = ̿̿̿̿̿̿̿̿
𝐴+𝐵
Using De-Morgan’s theorem,
̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = 𝐴̅ . 𝐵̅
Therefore, Q = ̅̅̅̅
𝐴̅𝐵̅ = 𝐴
̅̅̅̅̅̅̅̅
+𝐵 =𝐴+𝐵
D. NOR gate using NAND gate
The Boolean expression for NOR gate is Q = ̅̅̅̅̅̅̅̅
𝐴+𝐵

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Using De-Morgan’s theorem Q = ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = 𝐴̅ . 𝐵̅
Taking double inversion of RHS we get
̅̅̅̅̅̅
Q = 𝐴̅ . 𝐵̅ = 𝐴̅ . 𝐵̅ = ̅̅̅̅̅̅̅̅
𝐴+𝐵

E. X-OR gate using NAND gate

The Boolean expression for X-OR gate is

Q = A ⨁ B =𝐴̅ 𝐵 + 𝐴𝐵̅
Taking double inversion of RHS we get,
̅̅̅̅̅̅̅̅̅̅̅̅̅
Q = 𝐴̅ 𝐵 + 𝐴𝐵̅
̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅
Using De-Morgan’s theorem, 𝐴̅ 𝐵 + 𝐴𝐵̅ = ̅̅̅̅ 𝐴𝐵̅ = ̅̅̅̅
𝐴̅𝐵 . ̅̅̅̅ 𝐴̅𝐵 + ̅̅̅̅
𝐴𝐵̅
𝑄 = 𝐴̅ 𝐵 + 𝐴𝐵̅
F. X-NOR using NAND gate
The Boolean expression for X-NOR is given by
Q = A ⊙ B = 𝐴̅ 𝐵̅ + 𝐴𝐵
Taking double inversion of RHS we get
̅̅̅̅̅̅̅̅̅̅̅
Q = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴̅ 𝐵̅ + 𝐴𝐵 = ̅̅̅̅̅
𝐴̅ 𝐵̅ . 𝐴𝐵
̅̅̅̅ = 𝐴̅ 𝐵̅ + 𝐴𝐵 = A ⊙ B

6.2 NOR Gate as Universal Gate

The Boolean expression of the given logic circuit
must first convert into NOR format.

A. NOT gate using NOR gate

When input A = B
Q = ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = ̅̅̅̅̅̅̅̅
𝐴+𝐴
Since A + A = A , Therefore, Q = 𝐴̅
B. OR gate using NOR gate
Boolean expression for an OR gate is Q = A+B
Taking double inversion of RHS Q = ̅̅̅̅̅̅̅̅
𝐴+𝐵
Therefore, A+B = ̅̅̅̅̅̅̅̅
𝐴+𝐵 = Q
C. AND Gate using NOR gate

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Boolean expression for an AND gate is Q = A . B
̅̅̅̅̅
Taking double inversion of RHS Q = 𝐴. 𝐵 = ̅̅̅̅̅̅̅̅̅̅
𝐴̅ + 𝐵̅
Using De-Morgan’s theorem
Therefore, Q = ̅̅̅̅̅
𝐴. 𝐵 = 𝐴𝐵
D. NAND gate using NOR gate
̅̅̅̅̅
Boolean expression for NAND gate is Q = 𝐴. 𝐵
Using De-Morgan’s theorem Q = 𝐴̅ + 𝐵̅
Taking double inversion on RHS
̅̅̅̅̅̅̅̅̅̅̅̅
Q = 𝐴̅ + 𝐵̅ = 𝐴̅ + 𝐵̅ = 𝐴.
̅̅̅̅̅
𝐵
E. X-OR gate using NOR gate
Boolean expression for X-OR gate is
Q = A ⨁ B =𝐴̅ 𝐵 + 𝐴𝐵̅
Taking double inversion on RHS
̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅
Q = 𝐴̅ 𝐵 + 𝐴𝐵̅ = ̅̅̅̅ 𝐴̅𝐵 . ̅̅̅̅ 𝐴̅𝐵 + ̅̅̅̅̅
𝐴𝐵̅ = ̅̅̅̅ ̅̅̅̅
𝐴𝐵̅
̅̅̅̅̅̅̅̅
Q = 𝐴̅ + 𝐵̅ + ̅̅̅̅̅̅̅̅̅ 𝐴 + 𝐵̅ + ̅̅̅̅̅̅̅̅̅̅
𝐴̅ + 𝐵̅ = ̅̅̅̅̅̅̅̅̅̅ 𝐴̅ + 𝐵
Taking double inversion on RHS we get
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵̅ + ̅̅̅̅̅̅̅̅̅̅
Q = ̅̅̅̅̅̅̅̅̅̅ 𝐴 + 𝐵̅ + ̅̅̅̅̅̅̅̅̅̅
𝐴̅ + 𝐵 = ̅̅̅̅̅̅̅̅̅̅ 𝐴. 𝐵̅ + ̅̅̅̅̅̅
𝐴̅ + 𝐵 = ̅̅̅̅̅̅ 𝐴̅. 𝐵
= 𝐴̅ 𝐵 + 𝐴𝐵̅ = A ⨁ B
F. X-NOR gate using NOR gate
Boolean expression for X-NOR gate is
𝑄 = A ⊙ B = 𝐴̅ 𝐵̅ + 𝐴𝐵
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Taking double inversion on RHS Q = 𝐴̅ 𝐵̅ + 𝐴𝐵
̅̅̅̅̅̅̅̅̅̅̅
= ̅̅̅̅̅
𝐴̅ 𝐵̅ . ̅̅̅̅
𝐴𝐵
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + ̅̅̅̅̅̅̅̅̅̅
= 𝐴̅ + 𝐵̅ . 𝐴̅ + 𝐵̅ = ̅̅̅̅̅̅̅̅̅̅ 𝐴̅ + 𝐵̅
Taking double inversion on RHS,
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + ̅̅̅̅̅̅̅̅̅̅
Q = ̅̅̅̅̅̅̅̅̅̅ 𝐴 + 𝐵 + ̅̅̅̅̅̅̅̅̅̅
𝐴̅ + 𝐵̅ = ̅̅̅̅̅̅̅̅̅̅ 𝐴̅ + 𝐵̅
Q = 𝐴̅𝐵̅ . 𝐴̅ 𝐵̅ = 𝐴𝐵 + 𝐴̅ 𝐵̅

7 Boolean function
Binary variables have two values, either 0 or 1. A Boolean function is an expression
formed with binary variables, the two binary operators AND and OR, one unary operator

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NOT, parentheses and equal sign. The value of a function may be 0 or 1, depending on
the values of variables present in the Boolean function or expression. For example, if a
Boolean function is expressed algebraically as
F = ABC
then the value of F will be 1, when A = 1, B = 0, and C = 1. For other values of
A, B, C the value of F is 0.
Boolean function can also be represented by truth tables. For example, for three
variables the Boolean function F = AB+C, the truth table can be deduced as shown
below. We can also design the logic diagram from such table and minimize it as
F=AB+C

A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
8 Reduce the following Boolean expression
̅. 𝑪 = 𝟎
1. A.𝑨
2. ABCD+ABD = ABD(C+1) = ABD
3. xy+xyz+xy𝒛̅+𝒙 ̅𝒚𝒛
= xy+ xy𝑧̅ + xyz + 𝑥̅ 𝑦𝑧
= xy(1+𝑧̅) + yz(x+ 𝑥̅ )
=xy + yz
=y(x+z)

4. AB + ̅̅̅̅ ̅ 𝑪(𝑨𝑩 + 𝑪)
𝑨𝑪 + 𝑨𝑩
̅̅̅̅ + 𝐴𝐵̅ 𝐶𝐴𝐵 + 𝐴𝐵̅ 𝐶𝐶
= AB + 𝐴𝐶
= AB + ̅̅̅̅
𝐴𝐶 + 0 + 𝐴𝐵̅ 𝐶
= A(B+𝐵̅ 𝐶) + 𝐴𝐶̅̅̅̅
̅̅̅̅
= A(B+C) + 𝐴𝐶 [ B+𝐵̅ 𝐶 = 𝐵 + 𝐶]
=AB+AC+ ̅̅̅̅𝐴𝐶
=AB+1 [AC+ 𝐴𝐶 ̅̅̅̅ = 1]

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 Boolean Algebra and Logic Gates Unit 3
9 Prove the following Boolean expression
1. (A+B)(A+C)= A+BC
LHS = (A+B)(A+C)
= AA+AC+BA+BC
= A+AC+BA+BC
=A(1+C) + BA+BC
=A +BA+BC
=A(1+B) + BC
=RHS
2. (A+B)(A+ 𝑩 ̅ )(𝑨
̅ + 𝑪) = 𝑨𝑪
LHS = (A+B)(A+ 𝑩 ̅ )(𝑨
̅ + 𝑪) = 𝑨𝑪
= (A + A𝐵̅ + 𝐵𝐴 + 𝐵𝐵̅ )(𝐴̅ + 𝐶)
= A(1+𝐵̅ + 𝐵 + 0)(𝐴̅ + 𝐶)
= A(𝐴̅ + 𝐶)
= A𝐴̅ + 𝐴𝐶
= 0+AC=AC=RHS
3. ABC+ A𝑩 ̅ 𝑪 + 𝑨𝑩𝑪 ̅ = 𝑨(𝑩 + 𝑪)

LHS = ABC+ A𝐵̅ 𝐶 + 𝐴𝐵𝐶̅

=AC(B+𝐵̅ ) + 𝐴𝐵𝐶̅
=AC+ 𝐴𝐵𝐶̅
=A(C+ 𝐵𝐶̅ )
= A(B+C) [given by duality principle]

̅𝒀
4. 𝑿 ̅+𝑿 ̅ 𝒀 + 𝑿𝒀 = 𝑿 ̅+𝒀
LHS = 𝑋̅ 𝑌̅ + 𝑋̅ 𝑌 + 𝑋𝑌 = (𝑋̅ 𝑌 + 𝑋̅ 𝑌̅) + (𝑋̅ 𝑌 + 𝑋𝑌)
= 𝑋̅ (𝑌 + 𝑌̅) + Y(𝑋 + 𝑋̅ )
= 𝑋̅ + 𝑌

5. 𝑨 ̅ 𝑪̅ + 𝑨𝑩 + 𝑩
̅𝑩 + 𝑩 ̅𝑪 = 𝟏
LHS = (𝐴̅ 𝐵 + 𝐴𝐵) + ( 𝐵̅ 𝐶̅ + 𝐵̅ 𝐶 )
= B(𝐴̅ + 𝐴) + 𝐵̅ ( 𝐶̅ + 𝐶)
=B + 𝐵̅
=1

̅ 𝒁 + 𝑿𝒀̅ = 𝑿 + 𝒀 + 𝒁
6. 𝒀 + 𝑿
LHS = 𝑌 + 𝑋̅ 𝑍 + 𝑋𝑌 = (𝑌 + 𝑋)(𝑌 + 𝑌̅ ) + 𝑋̅ 𝑍
=(𝑌 + 𝑋) + 𝑋̅ 𝑍

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 Boolean Algebra and Logic Gates Unit 3
=Y+(X + 𝑋̅ )(X+Z)
=X
7. F=AB+ BC + BC.
LHS= F = AB + BC + BC
= AB + C(B + B)
= AB + C

8. F = AB + (AC) + ABC(AB + C).

LHS = F = AB + (AC) + ABC(AB + C)
= AB + A + C+ ABC.AB + ABC.C
= AB + A + C + 0 + ABC (B.B = 0 and C.C = C)
= ABC + ABC + A + C + ABC (AB = AB(C + C) = ABC + ABC)
= AC(B + B) + C(AB + 1) + A
= AC + C+A (B + B = 1 and AB + 1 = 1)
= AC + (AC)
=1

Review Questions
1. “ 8 4 -2 -1” code is self-complementary code” . Justify the statement
2. Determine the value of base x if (321)x =(57)8
3. Reduce the give expression in minimum number of literals using Boolean algebra and
derive the truth table and implement in NAND logic. A + B[AC + B{AC+(B+C’)D}]
4. Explain the universal property of NOR gate with appropriate logic gates.
5. State and prove De-Morgan’s theorem. List out the factors to be considered while
constructing the Logic gates.
6. Design the three bit EX-OR circuit using only Universal gates?
7. Simplify the following expressing using Boolean algebra.
a. (AB’ + AB’C’)’ + A(B’+AB’)
b. [(BC’+A’D)(AB’+C’D’)]’
c. A’B’+BC + A’BC’= A’+BC
d. XY’+YZ’+ZX’=X’Y+Y’Z+Z’X
8. Implement XNOR gate using only NAND gates and XOR gate using NOR gate only
9. Why NAND and NOR are called Universal gates? Construct F=AB+CD using universal
gates

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

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 Simplification of Boolean Function
1 Venn Diagram
Venn diagrams are illustrative methods of visualizing the relationships among the variables of the
Boolean expression. For example, if the variables are A and B, then A = 1 for inside the
circle A, A = 0 for outside of circle A, and B = 1 for inside the circle B, B = 0 for
outside of circle B. Now for two overlapping circles, four distinct areas are available inside
the rectangle area belonging to A only or AB', area belonging to B only or A'B, area
belonging to both A and B i.e., A.B and area belonging to neither A or B i.e., AB.

Figure 1 : Boolean equation representation

2 Canonical and Standard Forms

Logic functions can be expressed in different combinations of logical variables with their
true (x) as well as their complement (x’) form. Any arbitrary logic function can be
expressed in the following forms. Another way to express Boolean functions is in standard
form. In this configuration, the terms that form the function may contain one, two, or any
number of literals. There are two types of standard forms
a) Sum of products (SOP)
b) Products of Sums (POS)

2.1 Sum of products (SOP)

The logical sum of two or more logical products terms is referred as SOP. For example,
Y = AB + BC + AC or Y = AB + BC + AC are sum of products expressions.

2.2 Product of Sums (POS)

The logical products of two or more logical sum terms is referred as POS. For example,
Y = (A + B + C)(A + B + C)(A + B + C) or Y = (A + B + C)(A + B + C)
are products of sums expressions.

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 Simplification of Boolean Function

3 Minterms
It is a product term containing all n variables of the function in either true or
complemented form. Each minterm is obtained by an AND operation of the variables in
true or complemented form. So, if the number of variables is n, then the possible
number of minterms is 2n.
➢ Represents exactly one combination in the truth table
➢ Denoted by mj where j is the decimal equivalent of the minterm’s corresponding
binary combination (bj).
➢ A variable in mj is complemented if its value in bj is 0, otherwise is
uncomplemented.
4 Maxterms
It is a sum term containing all n variables of the function in either true or complemented
form. Each maxterm is obtained by an OR operation of the variables in their true form
or complemented form. So, if the number of variables is n, then the possible number of
maxterms is 2n. The main property of a maxterm is that it possesses the value of 0 for
only one combination of n input variables and the rest of the 2n –1 combinations have the
logic value of 1.
➢ Represents exactly one combination in the truth table
➢ Denoted by Mj where j is the decimal equivalent of the maxterm’s corresponding
binary combination (bj).
➢ A variable in Mj is complemented if its value in bj is 1, otherwise is
uncomplemented.
Truth table notation for Minterms and Maxterms

Table 1 Minterm and Maxterm truth table

A B C Minterm Maxterm
0 0 0 A’B’C’= m0 A + B + C =M0
0 0 1 A’B’C= m1 A + B + C’=M1
0 1 0 A’BC’= m2 A + B’ + C=M2
0 1 1 A’BC= m3 A + B’ + C’=M3
1 0 0 AB’C’= m4 A’ + B + C=M4
1 0 1 AB’C= m5 A’ + B + C’=M5
1 1 0 ABC’= m6 A’ + B’ + C=M6
1 1 1 ABC= m7 A’ + B’ + C’=M7

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 Simplification of Boolean Function
5 Method to obtain the canonical sum of products
1. Check each term in the given logic function. Retain if it is a minterm, and continue
to examine the next term in the same manner.
2. Examine the variables that are missing in each product which is not a minterm.
If the missing variable in the minterm is X, multiply that minterm with (X+X’).
3. Multiply all the products and discard the redundant terms.

Example Obtain the canonical sum of product form of the following function.
F (A, B) = A + B
Solution
The given function contains two variables A and B. The variable B is missing from the
first term of the expression and the variable A is missing from the second term of
the expression. Therefore, the first term is to be multiplied by (B + B) and the
second term is to be multiplied by (A + A) as demonstrated below.

F (A, B) = A + B
= A.1 + B.1
= A (B + B) + B (A + A)
= AB + AB + AB + AB
= AB + AB + AB (as AB + AB = AB)
Hence the canonical sum of the product expression of the given function is
F(A,B) = AB + AB + AB.

Example O b t a i n the canonical sum of product form of the following function.

F (A, B, C) = A + BC
Solution
Here neither the first term nor the second term is minterm. The given function contains
three variables A, B, and C. The variables B and C are missing from the first term
of the expression and the variable A is missing from the second term of the expression.
Therefore, the first term is to be multiplied by (B + B) and (C + C). The second term is
to be multiplied by (A + A). This is demonstrated below.
F (A, B, C) = A + BC
= A (B + B) (C + C) + BC (A + A)
= (AB + AB) (C + C) + ABC + ABC
= ABC + ABC + ABC + ABC + ABC + ABC
= ABC + ABC + ABC + ABC + ABC (as ABC + ABC = ABC)
Hence the canonical sum of the product expression of the given function is

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 Simplification of Boolean Function
F (A, B) = ABC + ABC + ABC + ABC + ABC.

Example Obtain the canonical sum of t h e product form of the following function.
F (A, B, C, D) = AB + ACD
Solution
F (A, B, C, D) = AB + ACD
= AB (C+C) (D+D) + ACD(B+B)
= (ABC+ABC) (D+D) + ABCD + ABCD
= ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
= ABCD + ABCD + ABCD + ABCD + ABCD
Hence above is the canonical sum of the product expression of the given function.

6 Method to obtain the canonical product of sums

1. Check each term in the given function. Retain it if it is a maxterm, and continue to examine
the next term in the same manner.
2. Examine the variable that is missing in each sum term that is not a maxterm. If the missing
variable in the maxterm is X, multiply that maxterm with (X.X’).
3. Expand the expression using the properties and postulates as described earlier and discard
the redundant terms.

Example Obtain the canonical product of the sum form of the following function.
F(A,B,C) = (A + B) (B + C) (A + C)
Solution
In the above three-variable expression, C is missing from the first term, A is missing
from the second term, and B is missing from the third term. Therefore, CC is to be
added with first term, AA is to be added with the second, and BB is to be added
with the third term. This is shown below.
F (A,B,C) = (A+B) (B+C) (A+C)
= (A+B+0) (B+C+0) (A+C+0)
= (A+B+CC) (B+C+AA) (A+C+BB)
= (A+B+C) (A+B+ C) (A+ B + C) (A+ B + C) (A+ B +C) (A+B+C) [using
the distributive property, as X + YZ = (X + Y)(X + Z)]
= (A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C) [as (A + B + C) (A +
B + C) = A + B + C]
Hence the canonical product of the sum expression for the given function is
F(A,B,C) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)

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 Simplification of Boolean Function
Example Obtain the canonical product of the sum form of the following function. F
(A, B, C) = A + BC
Solution
In the above three-variable expression, the function is given at sum of the product form.
First, the function needs to be changed to product of the sum form by applying the
distributive law as shown below.
F (A, B, C) = A + BC
= (A + B) (A + C)
Now, in the above expression, C is missing from the first term and B is missing
from the second term. Hence CC is to be added with the first term and BB is to be
added with the second term as shown below.
F (A,B,C) = (A+B)(A+C)
= (A+B+CC) (A+C+BB)
= (A+B+C)(A+B+C)(A+B+C)(A+B+C)
[using the distributive property, as X+YZ = (X + Y) (X + Z)]
= (A+B+C)(A+B+C)(A+B+C) [as (A+B+C)(A+B+C)=A+B+C]
Hence the canonical product of the sum expression for the given function is
F (A, B, C) = (A + B + C) (A + B + C) (A + B + C).

6.1 Shorthand: ∑ and ∏

➢ f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and
m(1,2,4,6) indicates that the minterms to be included are m1, m2, m4, andm6.
➢ f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and
M(0,3,5,7) indicates that the maxterms to be included are M0, M3, M5, andM7.
➢ Since mj = Mj’ for any j, ∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)

6.2 Conversion between Canonical Forms

1. To convert from one canonical form to another interchange the symbol
i.e. ∑ → ∏ or ∏ → ∑
2. List those number missing from the original form
e.g. F = ∑(0 , 1, 7)
F = ∏(2, 3, 4, 5, 6)

Example F (A,B,C) =  ( 2,4,5,6)

= m2 + m4 + m5 + m6
= ABC + ABC + ABC +ABC
To change into products of sums

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 Simplification of Boolean Function
F(A,B,C) = ∏(0,1,3,7)
= (A+B+C)(A+B+C’)(A+B’+C’)(A’+B’+C’)
= M 0M 1M 3M 7

7 Minimization Technique
The complexity of digital logic gates to implement a Boolean function is directly related
to the complexity of algebraic expression. Also, an increase in the number of variables
results in an increase in complexity.

7.1 Truth table to Karnaugh map

K-map is regarded as a diagrammatic or pictorial form of a truth table. It is composed of
a certain number of squares or cells, each of which is reserved for a term(minterm or
maxterm) of a logic function. For n variable problems it require 2 n location in K-map.

7.2 K-Map Structure - 2 Variable

➢ A & B are variables or inputs
➢ 0 & 1 are values of A & B
➢ 2 variable k-map consists of 4 boxes i.e. 22=4

7.3 K-map Structure -3 variables

➢ A, B & C are variables or inputs
➢ Variable k-map consists of 8 boxes i.e. 23=8

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 Simplification of Boolean Function
3 Variable K-map & its associated minterms

7.4 K-map Structure -4 variables

➢ A, B, C & D are variables or inputs
4
➢ 4 variable k-map consists of 16 boxes i.e. 2 =16

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 Simplification of Boolean Function
7.5 Variable K-map and its associated minterms

8 Representation of Standard SOP form expression on K-map

For example, SOP equation is given as Y = A’B’C’+ A’B’C+ AB’C’+ABC’+ABC
Each term from the above equation represents the minterm.
We have to enter ‘1’ in the boxes corresponding to each minterm as below.

8.1 Grouping of Functions

➢ Once we plot the logic function or truth table on K-map, we have to use the grouping
technique for simplifying the logic function.
➢ Grouping means combining the terms in adjacent cells.

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➢ The grouping of either 1’s or 0’s results in the simplification of a Boolean expression.
➢ While grouping, we should group most number of 1’s.
➢ The grouping follows the binary rule i.e. we can group 1,2,4,8,16,32…… a number of 1’s.
➢ We cannot group 3,5,7….. number of 1’s.
Note:
➢ If we group the adjacent 1’s then the result ofsimplification is SOP form.
➢ If we group the adjacent 0’s then the result ofsimplification is POS form.

Pair: A group of two adjacent 1’s is called Pair.

Quad: A group of four adjacent 1’s is called as Quad.
Octet: A group of eight adjacent 1’s is called as Octet.

8.2 Grouping of Two Adjacent 1’s: Pair

A pair eliminates 1 variable

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 Simplification of Boolean Function
8.3 Possible Grouping of Four Adjacent 1’s : Quad
A Quad eliminates two variables

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 Simplification of Boolean Function

8.4 Possible Grouping of Eight Adjacent 1’s : Octet

A Octet eliminates 3 variable

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 Simplification of Boolean Function
9 Rules for K-Map Simplification
1 Group may not include any cell containing a zero.

2 Group may be horizontal or vertical, but may not be diagonal

3 Each cell containing a one must be in at least one group

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 Simplification of Boolean Function

4 Group may be overlapped

5 Group may wrap around the table. The leftmost cell in a row may be grouped with
rightmost cell and the top cell in a column may be grouped with bottom cell

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 Simplification of Boolean Function
6 Redundant groups can be eliminated.
7 First of all we have to observe octets, if there are octets we have to group
them, secondly, we have to group quads, and last we have to group pairs.
Note:
➢ Pairs Quads and Octets
Two adjacent 1 is called pair.
Four adjacent 1 is called quads.
Eight adjacent 1 is called octets.
First of all we have to observe octets, if there is octets we have to group them,
secondly, we have to group quads and in last we have to group pair.

➢ K-MAP simplification.
A pair eliminates one variable and its complement, a quad eliminates two variables
and their complements, and octets eliminates three variables and their
complements. Because of this we have to use octets first then quad and in last go
for pair.

➢ Overlapping Group
We can use same 1 more than once, so always overlap the group if possible.

➢ Rolling groups
We can roll the map if it is possible. If there is a pair and rolling is possible at that
place to form a quad then we follow a rolling method.

➢ Redundant group
When there is a redundant group eliminate it.

Simplification in SoP and PoS using K-Map

1. Example 1 For the given K-map write a simplified Boolean Expression

Simplified Boolean expression Y= BC’+AB+AC’

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 Simplification of Boolean Function
2. For the given K-map write simplified Boolean expression

Simplified Boolean expression Y = B’ + A’C’

3. A Logical expression in the standard SOP form is as follows:
Y=A’B’C’+A’BC’+A’BC+AB’C minimize it using K-map technique.

Solution:
Here, Y=A’B’C’+A’BC’+A’BC+AB’C filling the K-map with relevant 1’s

A simplified Boolean expression can now be deduced as: Y= A’C’ + A’B + AB’C
4. A logic expression representing a logic circuit is Y =∑m( 0 , 1 , 2 , 5 , 1 3 , 1 5 )
Draw the K-map and find the minimized logical expression.
Solution:
Here, Y =∑m( 0 , 1 , 2 , 5 , 1 3 , 1 5 )

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 Simplification of Boolean Function

Y= A’B’D’+ A’C’D+ABD
5. Minimize the following Boolean expression using
K-Map
F(A,B,C,D) =∑m( 1,3,5,9,11,13)

Solution:
F(A, B,C,D) =∑m( 1,3,5,9,11,13)

Simplified Boolean expression

F = B’D+C’D
= D(B’+C’)

6. Minimize the following Boolean expression using K-Map

F(A, B,C,D) =∑m( 4,5,8,9,11,12,13,15)
Solution:
F(A, B,C,D) =∑m( 4,5,8,9,11,12,13,15)
F= BC’+AC’+AD

7. Solve the following expressing with K-maps

a. F1(A,B,C) =∑m(0,1,3,4,5)
b. F2(A,B,C) =∑m(0,1,2,3,6,7)
Solution
F1(A,B,C) =∑m(0,1,3,4,5) F2(A,B,C) =∑m(0,1,2,3,6,7)

Simplified Boolean equation Simplified Boolean expression

F1= A’C + B’ F 2= A’ + B

8. Solve the following expression with K-maps;

a. F1(A, B,C) = m(0,1,3,4,5)

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 Simplification of Boolean Function
b. F2(A, B,C) = m(0,1, 2,3,6,7)

Solution

F1(A, B,C) = m(0,1,3,4,5) F2(A, B,C) = m(0,1, 2,3,6,7)

Simplified Boolean equation Simplified Boolean expression

F1= AC + B’ F 2= A’ + B

9. Simplify F(A,B,C,D) = m(0,1, 4,5,7,8, 9,12,13,15)

Solution:

10. Solve the following expression with K-Maps

a. f 1(A, B,C, D) = m(0,1,3,4,5,7)
b. f 2(A, B,C) = m(0,1,3,4,5,7)

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 Simplification of Boolean Function

Simplified Boolean expression Simplified Boolean expression

F1 = A’C’+A’D F2= B’+C

8 K-MAP for Product of Sum

K-map can also be used for Boolean expression in the Product of Sum form (POS). The
procedure for simplification of expression by a grouping of cells is also similar. The letter
with bar (NOT) represents 1 and the unbarred letter represents 0 of Binary. A zero is put
in the cell for which there is a term in the Boolean expression.

1. Simplify f (A, B,C, D) = M (0,1,3,5,6,7,10,14,15)

Solution:

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 Simplification of Boolean Function

Simplified Boolean expression is f(A,B,C,D) = (A+B+C)(A+D’)(A’+C’+D)

2. Simplify f(A,B,C,D) = M (4, 6,10,12,13,15)

Solution:

Simplified Boolean expression f = (A’+B+C’+D)(A+B’+D)(A’+B’+D’)(A’+B’+C)

9 Don’t care Conditions

When a certain input condition in some digital system never occurs during the normal
operation so that output never occurs, then is called don’t care condition. It is indicated
by “x”. “x” represents either 0 or 1. We can make a pair, quad, and octet from “x” with 1
or 0.
➢ For SOP form we enter 1’s corresponding to the combinations of input variables which
produce a high output.
➢ For POS form we enter 0’s corresponding to the combinations of input variables which
produce a high output.
➢ For some function, the outputs corresponding to certain combination of inputs
variable do not matters and we have freedom to assume as 0 or 1.
➢ Such freedom assists in problem simplification.
Example Using the K-map method obtain the minimal sum of products expression for
the function.

F(A,B,C,D) = ∑ (0, 2, 3, 6, 7) +d (8, 10, 11, 15)

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 Simplification of Boolean Function
Solution:

The simplified Boolean expression for the function is F = AC + BD

Example Using the Karnaugh map method obtain the minimal product of the sums expression
for the function.
F(A,B,C,D) = ∑ (0, 2, 3, 6, 7) +d (8, 10, 11, 15)
Solution:

The simplified Boolean expression for the function is F′ = A + C′D + BC′.

So F = A′ (C + D′) (B′ + C).

Five Variable K-Map

It consists two copies of four variable map, one of which reflected or flipped horizontally.

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 Simplification of Boolean Function

Example:
Simplify the given function of five variables using K-Map. f(A,B,C,D,E) = ∑ (0,4,6,7,8,
11,12,16,20,22,23,24,26,27,28,30,31).

Review Questions
1. Simplify the following Boolean function in (a) sum of products and (b) product of sums.
F (A, B, C, D) = ∑(0, 1, 2, 5, 8, 9, 10)
2. Implement the following function with NAND gates and NOR gates:
F(x, y, z) = ∑ (0, 6)
3. Simplify the following equation by K-Map

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 Simplification of Boolean Function
a. F(A, B, C) = ∑m(0, 2, 4) + ∑d(1, 3, 5, 6, 7)
b. F(A, B, C, D) = ∑m(2, 4, 5, 13, 14) + ∑d(0, 1, 8, 10)
c. F(A,B,C) = π(0, 2, 3,6)
4. what are the don’t-care conditions? What is its relevance in Boolean expression?
5. Obtain the sum of the products expressions for the following functions and implement them
with NAND gates as well as NOR gates.
a. F = Σ (1, 4, 7, 8, 9, 11) + d (0, 3, 5)
b. F = Σ (0, 2, 3, 5, 6, 7, 8, 9) + φ(10, 11, 12, 13, 14, 15)
6. Convert the following term into standard minterms: A+B’C
[ans=(A+B+C)(A+B’+C)(A+B’+C’)
7. Simplify F(A,B,C,D) = π(0,2,5,8,10) + d(7,15) write its standard SOP and implement the
simplified circuit using NOR gate only.
8. Use K-map to simplify the given Boolean function and once by considering the don’t care
condition and once by ignoring the don’t care condition and realizing it using the basic
gates.
F(A,B,C,D)= Σ(1,4,8,12,13,15) and don’t care d(A,B,C,D) = Σ(3,14)
9. Simplify the following using K-map F= Σ(0,1,4,8,10,11,12) and d= Σ(2,3,6,9,15) also
convert the result in standard minterms.
10. Simplify the Boolean function; F(w, x,y, z) = ∑(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
11. Simplify F(A,B,C,D)= Σ1,4,5,6,12,14,15) and don’t care condition d(A,B,C,D)= Σ(10,11)
12. Obtain the minimal sum of the products for the function F (A, B, C, D, E) = Σ (0, 2, 4, 6,
9, 11, 13, 15, 17, 21, 25, 27, 29, 31).
13. Given the following truth table:
a. Express F1 and F2 in product of maxterms.
b. Obtain the simplified functions in sum of products.
c. Obtain the simplified functions in product of sums.

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 Simplification of Boolean Function

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

Compiled By: Deepesh Prakash Guragain |Unit 4 | References: Morris Mano 23

 Combinational Circuit
1 Introduction
The digital systems consist of two types of circuits,
i. Combinational circuits and
ii. Sequential circuits
2 Combinational Circuit
A combinational circuit consists of logic gates whose outputs at any time are determined directly
from the present combination of inputs without regard to previous inputs. The output does not
depend on the past value of inputs or outputs therefore, combinational circuits do not need any
memory elements. For n input variables, there are 2n possible combinations of binary input values.
For each possible input combination, there is one and only one possible output combination. A
combinational circuit can be described by m Boolean functions, one for each output variable. Each
output function is expressed in terms of the n input variables.

Figure 1: Block diagram of a combinational circuit

2.1 Combinational Circuit Design Procedure
Any combinational circuit can be designed by the following steps of design procedure.
1. The problem is stated or clearly understand the problem
2. Identify the number of input variables and output functions.
3. The input and output variables are assigned letter symbols.
4. The truth table is prepared that completely defines the relationship between the input
variables and output functions.
5. The simplified Boolean expression is obtained by any method of minimization—algebraic
method, Karnaugh map method, or tabulation method.
6. A logic diagram is realized from the simplified expression using logic gates.

A practical design method would have to consider certain constraints as:

➢ Minimum number of gates

➢ Minimum number of inputs to gates

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➢ Minimum propagation time of the signal through the circuit
➢ Minimum number of interconnection
Example A circuit has four inputs and two outputs. One of the outputs is high when the majority
of inputs are high. The second output is high only when all inputs are of the same type. Design the
combinational circuit.

Solution
Step 1: Understand the problem ok, here circuit has 4 inputs and 2 outputs. Out of two, outputs
one is high when majority of inputs are high i.e Y1 = 1, when number of 1 in input is high. The
second output is high Y2 =1 when inputs = 0000 or 1111
Step 2: Here, the number of inputs are 4 and outputs are 2.
Step 3: Let 4 inputs be A,B,C,D and outputs be Y1 and Y2
4: Step Truth table construction and finding relationship

Inputs Outputs

A B C D Y1 Y2
0 0 0 0 0 1
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 1

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Step 5: Simplification from the truth table using K-map

Y1 = ABD + BCD + ACD + ABC Y2 = A’B’C’D’ + ABCD

Step 6: Final circuit diagram

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3 Adders
Digital computers perform a variety of information-processing tasks. Among the basic function
encountered are the various arithmetic operations. the most basic arithmetic operation are addition
and subtraction.

3.1 Half Adder

➢ A combinational circuit that performs the addition of two bits is called a half-adder.
➢ The circuit needs two inputs and two outputs.

3.1.1 Half-adder can be represented as:

Sum

Inputs Outputs

Carry

Figure 2 : Half-adder diagram

1. Truth Table for Half Adder

Inputs Outputs
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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2. K-map for Sum (Output) K-map for Carry (Output)

Sum = A’B+AB’ Carry = AB

Sum = A  B
3. Final Logic Diagram:

4. Logic Diagram Using Basic gate only can be illustrated as

Sum = A  B

Carry = AB

Limitation:
The addition of three bits is not possible to perform using half-adder
3.2 Full Adder
➢ A Full adder is an arithmetic adder that sums three input bits.
➢ It has three inputs and two outputs

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Figure 3 Full adder

3.2.1 Truth Table

Inputs Outputs
A B Cin Sum(S) Carry(C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

3.2.2 K-Map for Sum Output

S= AB’C’+ A’B’C+ABC+A’BC’

S= A’B’C+ABC+A’BC’+AB’C’

S= C(A’B’+AB) + C’(A’B+AB’)

S=C(AB)’+C’(AB)

S=ABC

3.2.3 K-map for Carry Output:

C= AC+BC+AB

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3.2.4 Logic Diagram:

S=ABC

C= AC+BC+AB

3.3 Full Adder using Half Adders

Proof:
Here, Sum = (AB)Cin
= ABCin
This is the same as that obtained for a full adder.
Now, COUT = (AB)CIN + AB
= (A’B+AB’)CIN+AB = A’BCIN+AB’CIN+AB = A’BCIN+AB’CIN+AB(1+CIN)
= A’BCIN+AB’CIN+AB+ABCIN = BCIN(A’+A) + AB’CIN+AB
BCIN+ AB’CIN+ AB(1+CIN) = BCIN+ AB’CIN+ AB+ABCIN
= BCIN + AB + ACIN(B+B’) = AB+BCIN+ACIN
3.3.1 Application
A full adder acts as the basic building blocks of 4 bit / 8 bit binary/BCD adder IC.

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4 Subtractors
The subtraction of two binary numbers may be accomplished by taking the complements of the
subtrahend and adding it to the minuend. By this method, the subtraction operation becomes an
addition operation requiring full adders for its implementation. Binary subtractors may be
classified as
i. An Half-Subtractor
ii. A Full-Subtractors
4.1.1 Half Subtractor
Half subtractor is a combinational logic with two inputs and two outputs. It is a basic building
block for the subtraction of two single-bit numbers.

A Difference
Half Subtractor
B Borrow
Figure 4 Half Subtractor

4.1.2 Truth Table

Inputs Outputs
A B Difference(D) Borrow(B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
4.1.3 K-Map for Difference Output

D = A’B+AB’

D= AB

4.1.4 K-Map for Borrow Output

B =A’B

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4.1.5 Logic Diagram:

4.1.6 Logic Diagram using Basic Gates:

4.2 Full Subtractor

Full subtractor is a combinational logic circuit with three inputs and two outputs

Figure 5 Full Subtractor

4.2.1 Truth Table

Inputs Outputs
A B Bin(C) Difference(D) Borrow(B)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1

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1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

4.2.2 K-map for Difference Output:

D = A’B’C+ A’BC’+ABC+AB’C’
D= A’B’C+ABC + A’BC’+ AB’C’
D=C(A’B’+AB) + C’(A’B+AB’)
Let A’B+AB’ = X
Therefore, D= C(X’)+C’(X)
D = C  X = ABC
4.2.3 K-map for Borrow Output:
B0 = A’B+BC+A’C

4.2.4 Logic Diagram

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4.3 Full Subtractor using Half Subtractor
A full subtractor is a combinational circuit with three inputs A, B, and Bin, and two outputs D and
Bo. Here, A is the minuend, B is the subtrahend, Bin is the borrow produced by the previous stage,
D is the difference output and Bo is the borrow output.

D = ABBin
B0 = (AB)’Bin + A’B = (A’B+AB’)’Bin + A’B
= (A’B’ +AB)Bin + A’B = A’B’Bin + ABBin + A’B
= A’B’Bin + ABBin + A’B(1+Bin)
= A’B’Bin + BBin(A+A’) + A’B
= A’B’Bin + BBin + A’B
= A’B’Bin + BBin + A’B(1+Bin)
= A’B’Bin + BBin + A’B + A’BBin
= A’Bin(B’ + B) + BBin + A’B
B0 = A’Bin + BBin + A’B
5 Design of Binary to Gray Code Converter
B3 G3
B2 Binary-to-Gray G2
B1 Code G1
B0 G0

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5.1 Truth Table

Binary Inputs Gray Outputs Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1
0 0 0 1 0 0 0 1 1 0 1 1 1 1 1 0
0 0 1 0 0 0 1 1 1 1 0 0 1 0 1 0
0 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1
0 1 0 0 0 1 1 0 1 1 1 0 1 0 0 1
0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1

5.2 K-map for G0: K-map for G1

G0 = B1’B0 + B1B0’ G1 = B2’B1 + B2B1’

G0 = B0  B1 G1 = B2  B1

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K-map for G2: K-map for G3:

G2 = B3’B2 + B3B2’ G3 = B3
G2 = B3  B2

5.3 Logic Diagram:

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6 Design of Gray to Binary Code Converter

G3 B3
G2 Gray – to- Binary B2
Conversion
G1 B1
G0 B0

6.1 Truth Table

Gray Inputs Binary Outputs
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

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6.2 K-map for B0:

B0 = G3’G2’G1’G0 + G3’G2’G1G0 + G3’G2G1’G0 + G3’G2G1G0 +

G3G2’G1’G0+G3G2’G1G0+G3G2G1’G0+G3G2G1G0’
B0= G3G2G1G0
K-map for B1 : K-map for B2:

B1= G3’G2’G1 + G3’G2G1’+ G3G2G1+ G3G2’G1’ B2 = G3’G2 +G3G2’

B1= G3G2G1 B1 = G3G2

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K-map for B3: Logic Diagram:

B3 = G3

7 BCD(8421) to Excess -3 7.1 Truth Table

A W BCD Inputs EXCESS-3

B BCD-to-Excess - X A B C D W X Y Z
3
C Y 0 0 0 0 0 0 1 1
Conversion
D Z 0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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7.2 K-Map for W:

W = A + BC+BD

K-Map for X: K-Map for Y:

X= B’C+ B’D+BC’D’ Y = CD + C’D’

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Z = D’

Logic Circuit

8 Analysis Procedure
The design of combinational circuit starts from the verbal specification of a required function and
completes with set of outputs Boolean functions or a logic diagram. The analysis of a
combinational circuit is somewhat the reverse process. It starts wit a given logical diagram and
ends with sets of a Boolean functions, a truth table or a verbal explanation of the circuit operation.

Methods involved to obtain Boolean function from the logical diagram:

1. Label with arbitrary symbols all gate outputs that are function of the input variables. Obtain
the Boolean function for each gate.

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2. Label with other arbitrary symbols those gates which are a function of input variables
and/or previously labeled gates. Find the Boolean function for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
4. By repeated substitution of previously defined function, obtain the output Boolean function
in terms of input variable only.

8.1 Given Logical Diagram

1. Label Each significant Outputs

2. Deduce the Final Equation from simplification

From above figure
D = (A’B+C’)’(A+C) = ((A’B)’C(A+C)
D= [(A+B’)C](A+C)
D= AAC + AC + AB’C+ B’C
D= AC + AC + B’C(A+1) = AC + B’C(1)
D= (A+B’)C
3. Simplified Diagram if Possible

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Multilevel NAND Circuits
Process to obtain multilevel NAND diagram from Boolean expression
1. From the given algebraic expression, draw the logic diagram with AND, OR, and NOT
gates. Assume that both the normal and complement inputs are available.
2. Draw a second logic diagram with the equivalent NAND logic.
3. Remove any two cascaded inverters from the diagram, since double inversion does not
perform a logic function. Remove inverters connected to single external inputs and
complement the corresponding input variable. The new logic diagram obtained is the
required NAND get the implementation.
Example Given Circuit Diagram

Above, equation can be written as F = AB + CD

F=AB + CD
= ((AB + CD)) - complement to complement operation
= ((AB) (CD)) - applying DeMorgan’s theorem
1. Using only NAND gate only

2. Remove Double Complement

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Example Realize the following function by NAND gates only, F = B(A + CD) + AC
Solution:
The equivalent diagram from the function

Realization using NAND gate only

C
D
F
A

A
C

3. Realization of Logic Functions by NOR Gates

Process to obtain multilevel NOR diagram from Boolean expression
1. Draw the AND-OR logic diagram from the given algebraic expression. Assume that both
the normal and the complement inputs are available.

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2. Draw a second logic diagram with equivalent NOR gate, substituted for each AND, OR
and NOT gate.
3. Remove pairs of cascaded inverters from the diagram. Remove inverters connected to
single external inputs and complement the corresponding.

Example F = (A + B) (C + D)
This concept can also be explained by Boolean algebra and DeMorgan’s theorem.
F = (A + B) (C + D)
= (((A + B) (C + D))′)′ - complement to complement operation
= ((A + B)′ + (C + D)′)′ - applying DeMorgan’s theorem

Example Realize the following function by NOR gates only, F = A(B + CD) + BC’

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Solution

Example Realize the function F = BC + AC + AB by

i . NAND gates only
ii. NOR gates only
Solution:
NAND gates

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NOR gates

9 Parity Generator and Checker

Parity bit is an extra bit included with a binary message to make the number of 1’s either odd or
even. The message including the parity bit is transmitted and checked at the receiving end for
errors. An error is detected if the checked parity does not correspond to the one transmitted. The
circuit that generates the parity bit in the transmitter is called the parity generator, and the circuit
that checks the parity in the receiver is called the parity checker.
9.1 Parity Generator
It is combinational circuit that accepts an n-1 bit stream data and generates the additional bit that
is to be transmitted with the bit stream. This additional or extra bit is termed as a parity bit.
➢ In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data
stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.
➢ In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data
stream and the parity bit is ‘0’ if there are odd number of 1s in the data stream.
9.2 Even Parity Generator
Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs
A, B and C are applied to the circuits and output bit is the parity bit P. The total number of 1s must
be even, to generate the even parity bit P. The figure below shows the truth table of even parity
generator in which 1 is placed as parity bit in order to make all 1s as even when the number of 1s
in the truth table is odd.
3-bit Message Even Parity Generator(P)
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

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K-Map for Parity

P = A’B’C + A’BC’ + AB’C’+ ABC

P = A’(B’C+ BC’) + A(B’C’ +BC)
P = A’(BC) + A(BC)’
P = ABC

P = ABC

9.3 Even Parity Checker

Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit which checks the possibility of error
on the data. Since the data is transmitted with even parity, four bits received at circuit must have
an even number of 1s. If any error occurs, the received message consists of odd number of 1s. The
output of the parity checker is denoted by PEC (parity error check). The below table shows the
truth table for the even parity checker in which PEC = 1 if the error occurs, i.e., the four bits
received have odd number of 1s and PEC = 0 if no error occurs, i.e., if the 4-bit message has even
number of 1s.

4- Bit Received Message Parity error check

A B C P(D) CP
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0

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1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

9.4 The above truth table can be simplified using K-map as shown below

CP = A’B’(C’D + CD’) + A’B(C’D’ + CD) + AB(C’D + CD’) + AB’(C’D’ + CD)

= A’B’(CD) + A’B(CD)’ + AB(CD) + AB’(CD)’
= (A’B’+ AB) (CD) + (A’B + AB’) (CD)’
= (AB) (CD)

Final Logic Diagram

Some Solved
1. Design a combinational circuit that accepts a three-bit number and generates an output
binary number equal to the square of the input number.

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Truth Table

Inputs Outputs
X Y Z a b c d e f
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1

K-map

a = xy C = x y  z + x  yz
c = z( x  y )

b = x y  + xz d = y z’

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Logical Diagram

2. Design a combinational circuit whose input is a four-bit number and whose

output is the 2 s complement of the input number.
Truth Table
A3 A2 A1 A0 F3 F2 F1 F0
0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 0
0 0 1 1 1 1 0 1
0 1 0 0 1 1 0 0
0 1 0 1 1 0 1 1
0 1 1 0 1 0 1 0
0 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0
1 0 0 1 0 1 1 1
1 0 1 0 0 1 1 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1

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3. Design a combinational circuit that generated the 9's complement of a BCD digit.
Truth Table K-map

Logical Circuit

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2. Design a combinational circuit for converting 2421 code to BCD code.

Truth Table

K-map

A = XY B = XY′+WX′

C = W′Y + WY′ D = Z.

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Logical Circuit

3. Design a combinational circuit that converts 2421 code to 84-2-1 code, and also the converter
circuit for 84-2-1 code to 2421 code.

Truth Table

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K-map

W=A X = A′B + A′C + A′D + BCD

= A′(B + C + D) + BCD

Y = AC′D′ + ACD + A′C′D + A′CD′ Z=D

Logical Circuit Diagram

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4. Design a combinational circuit for a BCD-to-seven-segment decoder
Truth Table

K-map

a = A + CD + BD + B′D′ b = B′ + C′D′ + CD

c = B + C′ + D d = B′D′ + CD′ + B′C + BC′D

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e = B′D′ + CD′ f = A + C′D′ + BC′ + BD′

Logical Circuit Diagram

g = A + BC′ + CD′ + B′C.

Review Questions
1. Design even parity when a 3-bit message contains cycle code.
2. Reduce the given equation in minimum numbers of literals using Boolean algebra and
derive the truth table and implement in NAND logic. A +B[AC+B{AC + (B+C’)D}]

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3. A logic circuit implements the following Boolean function F = A’C + AC’D. It is found
that the circuit inputs combinations, find a simplified expression and implement it using
NAND gates only.
4. Design a combinational circuit with four input lines that represent a decimal digit in BCD
and four output lines that generate the 9’S complements of the input digits.
5. Design a combinational circuit that takes three input numbers and produces and output
equal to the square of the inputs.
6. Design a combinational circuit that accepts a 3-bit number as input and generates the output
binary number equal to the 2’s complement of the input number.
7. Design a combinational circuit that converts a decimal digit from the 2421 code to 84-2-1
code to binary.
8. Design a circuit for 4-bit full subtractor adder.
9. Design a single combinational logic circuit that performs the addition of two input bits (a
and b) when the third input bit c is set to 0, whereas, the same circuit performs the
subtraction of the same two input bits when c is set to 1.
10. Design a combinational circuit that converts a decimal digit from the 2421 code to BCD.
11. Design a circuit for a 3-bit parity generator and 4-bit parity checker using even parity.
12. Design a combinational circuit that converts decimal digits from 8-4-2-1 to Excess-3.
13. Design a combinational circuit that accepts a two-bit number and generates an output
binary number equal to the cube of the input number.
14. A combinational circuit has four inputs and one output. The output is equal to 1 when (1)
all the inputs are equal to 1 or (2) none of the inputs are equal to 1 or (3) an odd number of
inputs are equal to I. (a) Obtain the truth table. (b) Find the simplified output function in
the sum of products. (c) Find the simplified output function in the product of sums. (d)
Draw the two logic diagrams.
15. Design a combinational circuit for a BCD-to-seven-segment decoder.

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

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 MSI and LSI Design Unit-6
Introduction to Integration Technology
There are several combinational circuits that are employed extensively in the design of digital
systems. These circuits are available in integrated circuits and are classified as MSI components.
MSI components perform specific digital functions commonly needed in the design of digital
systems. Combinational circuit-type MSI components that are readily available in IC packages are
binary adders, subtractors, comparators, decoders, encoders, and multiplexers. These components
are also used as standard modules within more complex LSI and VLSI circuits and hence are used
extensively as basic building blocks in the design of digital computers and systems.

1 Binary Parallel Adders

A full adder is capable of adding only two binary number along with a carry input. But in practice,
we need to add binary number which are much longer than just two bits. To add two n-bits binary
number, we need to use the n-bit parallel adder. To construct such adder, different number of full
adders are cascaded. The carry output of the previous full adder is connected to the carry input of
next full adder.

1.1 A 4-bit Binary Parallel Adder

Input Carry 0 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi
Sum 1 1 1 0 Si
Output Carry 0 0 1 1 Ci+1

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A binary parallel adder is a digital function that produces the arithmetic sum of two binary number
in parallel. It consists of full-adders connected in cascade, with the output carry from one full adder
connected to the input carry of the next full adder.

1.2 4-bit parallel subtractor

The subtraction of binary number can be carried out most conveniently by means of complements,
the subtraction A-B can be done by taking the 2’s complement of B and adding it to A. The 2’s
complement can be obtained by taking the 1’s complement and adding 1 to the least significant
pair of bits.

The number to be subtracted (B) is first passed through inverters to obtain its 1’s complement.
Then 1 is added to 1’s complement of B, by making Cin = 1. Thus we obtain 2’s complement of B.
The 4-bit adder then adds A and 2’s complement of B to produce the subtractor. Also, S3S2S1S0
represents the result of binary subtraction(A-B) and carry output Cout represents the polarity of the
result. If A> B, then Cout =0, and the result is in true binary form but if A<B, then Cout = 1, and
the result is in the 2’s complement form.

=1

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1.3 Four-Bit Binary Parallel Adder/Subtract
The addition or subtraction of two 4-bit binary number can be obtained using the same circuit as
shown in figure below. The operation performed by this circuit (Addition or subtraction) depends
on the state of the mode select input.
Here, the number B is applied to the adder through a set of EX-OR gate. One input of each EX-
OR gate is connected to the mode select input(M).

Working Operation as Adder(M=0)

The mode selects (M) input is connected to the ground. Therefore, M= 0, since M=0, Cin = 0, and
the output of EX-OR gate will be the same number B applied at their inputs. This is because 0⊕
0 = 0 and 0⊕ 1 = 1. Hence, B3, B2, B1, and B0 will pass unchanged through EX-OR gates. The
adder then adds A+B+Cin = A+B since Cin = 0. Thus, with M=0, the addition will take place.

Working operation as Subtractor(M=1)

The mode selects(M) input is connected to the Vcc. Therefore, M= 1, since M=1, Cin =1, and one
input of each X-OR gate is now 1. Hence, each X-OR gate acts as an inverter. This is because 1⊕
0 = 1 𝑎𝑛𝑑 1 ⊕ 1 = 0. Hence, each bit of word B is inverted by the X-OR gates. The inverted
number B adds with Cin = 1 to give the 2’s complement of B. Hence, the adder will add A with the

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2’s complement of B and the result is actually the subtraction of A-B. Hence, with M=1, this circuit
works as 2’s complement subtractor.

1.4 BCD adder/ Decimal adder:

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in
BCD. Suppose we apply two BCD digits to a 4-bit binary adder. The adder will form the sum in
binary and produce a result which may range from 0 to 19. These numbers are listed in the table
below and are labeled by symbols K, Z8, Z4, Z2, and Z1 where K is carry.

➢ For 0-9 → Binary Sum = BCD Sum

➢ For 10-19 → Binary Sum + 0110 = BCD Sum

When C=1, it is necessary to add binary 0110 to the binary sum and provide an o/p carry to the
next stage. A correction is needed when the binary sum has an o/p carry K=1. Binary 1010-1111
need correction and have a 1 in position Z8. To distinguish them from binary 1001, which also
have a 1 in Z8 position, we specify further that either Z4 or Z2 must have a 1. The condition for
the correction and o/p carry can be

C = K+ Z8Z4+Z8Z2 =1

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2 Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers, A and B and
determines their relative magnitude. The outcome of the comparison is specified by three binary
variables that indicate whether A > B, A = B or A < B.

2.1 1-bit Digital Comparator Circuit

2.2 Digital Comparator Truth Table

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2.3 Equivalent Circuit Diagram

2.4 4-bit Digital Comparator Circuit

Consider two numbers A and B with four digits each

A = A3A2A1A0
B = B3B2B1B0

Case 1: A = B

The two number are equal if all pairs of significant digits are equal i.e. if A3 = B3 and A2= B2 and
A1=B1 and A0 = B0. The equality relation of each pair of bits can be expressed logically with an
equivalence function.

Xi = AiBi + Ai’Bi’ i = 0,1,2,3…

Where, Xi = 1 only if the pair of bits in position i are equal i.e. if both are 1’s or both are 0’s.
For equality conditions to exists, all Xi variables must be equal to 1. This dictate an AND
operation of all variables:

(A = B) = X3X2X1X0
The binary variable (A = B) is equal to 1 only if all pairs of digits of the two numbers are equal.

Case 2: A > B or A < B

To determine if A is greater than or less than B, we inspect the relative magnitude of pairs of
significant digits starting from the most significant position. If the two digits are equal, we compare
the next lower significant pair of digits. This comparison continues until a pair of unequal digits is
reached. If the corresponding digits of A is 1 and that of B is 0, we conclude that A > B. If the

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corresponding digits of A is 0 and that of B is 1, we have that A< B. The sequential comparison
can be expressed logically by the following two Boolean functions.

A > B = A3B3’ + X3A2B2’ + X3X2A1B1’ + X3X2X1A0B0’

A < B = A3’B3 + X3A2’B2 + X3X2A1’B1 + X3X2X1A0’B0
Note: For 2 bits Xi = AiBi + Ai’Bi’ for i = 0, 1
A = B → X1.X0

A > B → A1B1’ + X1A0B0’ X3

A < B → A1’B1 + X1A0’B0

X2

X1

X0

3 Multiplexers
Multiplexing means transmitting a large number of information over a smaller number of channels
or lines. A digital multiplexer is a combinational circuit that selects binary information from one
of many inputs lines and directs it to a single output line. The selection of a particular input lime
is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines
whose bit combinations determine which input is selected.

3.1 Application
1. It is used as a data selector to select one out of many data inputs
2. It is used for simplification of digital design.

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3. In the data acquisition systems
4. In designing the combinational circuits
5. In the D/A converters
6. To minimize the number of connections

3.2 Block Diagram of Multiplexers

➢ In general, a multiplexer contains, n data lines one output line, and m selector lines.
➢ To select n inputs, we need m select lines such that 2m = n

3.3 Types of Multiplexers

Different types of multiplexers are widely used in the different digital circuit as per the requirement
and design. Some common types of multiplexers are 2:1 Multiplexer, 4:1 Multiplexer, 8:1
Multiplexer, 16:1 Multiplexer, 32:1 Multiplexer,64:1 Multiplexer and so on.

2:1 Multiplexer
Enable i/p (E) Select i/p (S) Output (Y)
0 X 0
1 0 D0
1 1 D1

Realization of 2:1 Mux using gates

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4:1 Multiplexer

Realization using gates

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3.4 Mux Tree
The multiplexers having more number of inputs can be obtained by cascading two or more
multiplexers with less number of inputs. This is called multiplexers tree.

3.5 8:1 Multiplexer using 4:1 Multiplexer

16:1 Multiplexer using 4:1 Multiplexer

Inputs Outputs
S0 S1 S2 S3 Y
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15

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4 Boolean Function implementation
We can implement Boolean function (in SOP) with multiplexer since multiplexer is essentially a
decoder with the OR gate already available.
➢ If we have a Boolean function of n + 1 variables, we take n of these variables and connect
them to the selection lines of a multiplexer. The remaining single variable of the function
is used for the inputs of the multiplexer. If A is this single variable, the inputs of the
multiplexer are chosen to be either A or A' or 1 or 0. By judicious use of these four values
for the inputs and by connecting the other variables to the selection lines, one can
implement any Boolean function with a multiplexer.
➢ So, it is possible to generate any function of n + 1 variables with a 2n-1 multiplexer.

Rules for Implementation

Apply variables A and B to the select lines. The procedure for implementing the function are
➢ List the inputs of the multiplexers
➢ List under them all the min-terms in two rows as shown below.
The first half of the min-terms is associated with A’ and the second half with A. The given function is
implemented by circling the min-terms of the function and applying the following rules to find the values
for the inputs of the multiplexers.
1. If both the min-terms of the column are not circled, apply 0 to the corresponding inputs.
2. If both the min-terms in the column are circled, apply 1 to the corresponding inputs.
3. If the bottom min-terms is circled and the top is not circled, apply C to the input.
4. If the top min-terms is circled and the bottom is not circled apply C’ to the input.

Example: Implement the following Boolean function using 4:1 multiplexer

F (A, B, C) = ∑m (1, 3, 5, 6).

Solution:
Variables, n= 3 (A, B, C) Select lines= n-1 = 2 (S1, S0) 2n-1 to MUX i.e., 22 to 1 = 4 to 1
MUX Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)

The function can be implemented with a 4-to-1 multiplexer, as shown in Fig. below. Two of
the variables, A and B, are applied to the selection lines in that order, i.e., A is connected to
S1 and B to S0. The inputs of the multiplexer are 0, 1, C, and C'.

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Implementation table

Multiplexer Implementation

Example: F (x, y, z) = ∑m (1, 2, 6, 7)

Solution:
Implementation table: Multiplexer Implementation

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Example: Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
F (A, B, C, D) = ∑m (0, 1, 2, 4, 6, 9, 12, 14)

Variables, n= 4 (A, B, C, D) Select lines= n-1 = 3 (S2, S1, S0) 2n-1 to MUX i.e., 23 to 1 = 8:1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)

Implementation Table

Multiplexer Implementation

Example: F (P, Q, R, S)= ∑m (0, 1, 3, 4, 8, 9, 15)

Solution:
Variables, n= 4 (P, Q, R, S) Select lines= n-1 = 3 (S2, S1, S0) 2n-1 to MUX i.e., 23 to 1 = 8 to 1
MUX Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)

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Implementation Table

Multiplexer Implementation

5 Demultiplexers
A multiplexer takes several inputs and transmits one of them to the output. A demultiplexer
performs the reverse operation; it takes a single input and distributes it over several outputs, so
demultiplexers can be thought of as a ‘distributor’ since it transmits the same data to different
destinations. A demultiplexer is the logic circuit that receives information through a single input
line and transmits the same information over one of the possible 2n output lines.

5.1 1:4 Demultiplexer

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Select Code Outputs

S1 S2 O3 O2 O1 O0
0 0 0 0 0 D
0 1 0 0 D 0
1 0 0 D 0 0
1 1 D 0 0 0

5.2 De-mux Tree

Similar to multiplexer we can construct the demultiplexer with more number of lines using
demultiplexers having less number of lines. This is called as “De-mux Tree”.

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5.3 1:4 De-mux using 1:2 De-mux

A B C

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Example Implement the following Boolean expression using de-multiplexer
F(A, B, C ) =  m(0, 3, 5, 6)

Solution:
Since there are three variables, therefore a demultiplexer with three select inputs is required i.e.
1:8 demultiplexer is required. The 1:8 demultiplexer can be configured as below to implement the
given Boolean expression.

Truth Table

A(S2) B(S1) C(S0) F(A,B,C)

0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Example: Implement following Boolean expression using de-multiplexer

f ( A, B, C, D ) =  m(0, 2, 3, 6,8, 9,12,14)

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Solution:

Since there are four variables, therefore a demultiplexer with four select inputs is required i.e. 1:16
demultiplexer is required. The 1:6 demultiplexer can be configured as below to implement given
Boolean expression.

6 Decoder
A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. If the n-bit decoded information has unused or don’t care
combination, the decoder output will have less than 2n outputs.

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Typical applications of Decoders

➢ Code Converters
➢ BCD TO 7 Segment decoder
➢ Nixie tube decoders
➢ Relay actuators

6.1 3 to 8-line Decoder

The three inputs are decoded into eight outputs, each output representing one of the minterms of
the 3-input variables. In order to decode all possible combinations of 3-bit, 8 decoder gates are
required i.e 23 = 8.
This type of decoder is commonly called 3 to 8 line decoder. There are 3 inputs and 8 outputs. A
list of binary codes and their corresponding decoding functions is given below.

A logic symbol for 3x8 decoder with inputs and outputs is shown in the figure above. The binary
decimal label indicates that the binary inputs make the corresponding output active.

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D0
D1
D2
D3
D4
D5
D6
D7

6.2 Combinational Logic Implementation

Decoders gives multiple outputs equivalent to the minterms corresponding to the input variables.
Thus any Boolean expression in the sum of product form can be easily be implemented with the
help of decoder and it does not require minimization of expression through simplification process
like K-Map.

Example: Implement the function F (A,B,C) = Σ (1,3,5,6)

Solution:
No. of inputs = 3
Decoder size = 3:23 = 3:8
Number of Outputs = 1
F(A,B,C) = F (A,B,C) = Σ (1,3,5,6)
No. of OR gate = 1
F (A,B,C) = Σ (1,3,5,6) = (m1 + m3 + m5 + m6)
= A’B’C + A’BC + AB’C + ABC’

Since the above function has three input variables, a 3-to-8 line decoder may be employed. It is
the sum of products of the min-terms m1, m3, m5, m6 and so decoder output D1, D3, D5, and D6

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may be OR-gated to achieve the desired function. The combinational circuit of the above function
is shown below.

EXAMPLE: Implement a full-adder circuit with a decoder and two OR gates.

Solution:
For full adder number of inputs = 3 i.e (A, B, C)
Decoder size = 3:23 = 3:8 (n:2n)
From the truth table as illustrated

Sum = 𝚺(𝟏, 𝟐, 𝟒, 𝟕)
Carry = 𝚺(𝟑, 𝟓, 𝟔, 𝟕)

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Example: Construct a 3-to-8-line encoder with the use of a 2-to-4-line encoder
Solution:
Lower-order decoders can be cascaded to build higher-order decoders. Normally every
commercially available decoder ICs have a special input other than normal working input variables
called ENABLE. The use of this ENABLE input is that when activated the complete IC comes to
the working condition for its normal functioning. If ENABLE input is deactivated the IC goes to
sleep mode, the normal functioning is suspended, and all the outputs become logic 0 irrespective
of normal input variables conditions. This behavior of ENABLE input makes good use of a cascade
connection.

Example: Construction of 4:16 line decoder using 2:4-line decoder with enable

Enable

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7 Encoder
An encoder is a digital function that produces a reverse operation from that of a decoder. An
encoder has 2n (or less ) input lines and n output lines. The outputs line generates the binary code
for the 2n input variables.

7.1 Basic Principle of 4:2 Encoder:

Encoder convert four signals into two, it can be understood by taking a look at the truth table
below. It is also important to know that an ordinary Encoder like the one shown here has a rule
that at given time only one input pin should be high so in the following truth table only one input
will be high.

Boolean Expression:
O1 = I3 + I2
O0 = I3 + I1

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7.2 Types of Encoders

1. Priority Encoder
2. Decimal to BCD Encoder
3. Octal to BCD Encoder
4. Hexadecimal to Binary Encoder
7.3 Priority Encoder:
The block diagram of a 4:2 Priority Encoder is shown below

A priority 4:2 Encoder has 4 inputs and 2 outputs, but we will add another output called V which
stands for a valid bit. This valid bit will check if all the four input pins are low (0) if low the bit
will also make itself low stating that the output is not valid.

Priority Encoder Truth Table:

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Boolean Expression:

O0

O1

O1 = I3 + I2
O0 = I2 I1’ + I3
V = I3 + I2 + I1 + I0

7.4 Octal to Binary Encoder

An octal to binary encoder consists of eight input lines and three output lines. Each input line
corresponds to each octal digit and three outputs generate the corresponding binary code. In
encoders, it is to be assumed that only one input is active or has a value 1 at any given time
otherwise the circuit has no meaning. The figure below shows the logic symbol of octal to binary
encoder along with its truth table.

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From the above table, the output Y2 becomes 1 if any of the digits D4 or D5 or D6 or D7 is one.
Thus, we can write its expression as
Y2 = D4 + D5 + D6 + D7
Y1 = D2 + D3 + D6 + D7 and
Y0 = D1 + D3 + D5 + D7

Also, it is to be observed that D0 does not exist in any of the expressions so it is considered as
don’t care. From the above expressions, we can implement the octal to binary encoder using set of
OR gates as shown in figure below.

D
0

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8 Read-Only Memory (ROM)
A ROM is essentially a memory (or storage) device in which a fixed set of binary information is
stored. The binary information must first be specified by the user and is then embedded in the unit
to form the required interconnection pattern. Once a pattern is established for a ROM, it remains
fixed even when power is turned OFF and then ON again.

A block diagram of a ROM is shown in the figure below. It consists of n input lines and m outputs
lines. Each bit combination of the input variable is called a word. The
number of bits per word is eual to the number of output lines m. an
address is essentially is equal to the number of output lines m. an
address is essentially a binary number that denotes one of the
minterms of n variable. The number of distinct addresses possible
with n input variables is 2n. an output word can be selected by a
unique address s and since there are 2n distinct addresses in a ROM,
there are 2n distinct words which are said to be stored in the unit. The
word available on the output lines at any given time depends on the
address value applied to the input lines. A ROM is characterized byy the number of words 2n and
the number of bits per word m.

Internally, the ROM is a combinational circuit with AND gates connected as a decoder and a
number of OR gates equal to the number of outputs in the unit.

8.1 Types of ROM

ROMs: For simple ROMs, mask programming is done by the manufacturer during the fabrication
process of the unit. The procedure for fabricating a ROM requires that the customer fill out the
truth table the ROM is to satisfy. The truth table may be submitted on a special form provided by
the manufacturer. The manufacturer makes the corresponding mask for the paths to produce the
1's and 0's according to the customer's truth table. This procedure is costly because the vendor
charges the customer a special fee for custom masking a ROM. For this reason, mask programming
is economical only if large quantities of the same ROM configuration are to be manufactured.

PROMs: Programmable read-only memory or PROM units contain all 0's (or all 1's) in every bit
of the stored words. The approach called field programming is applied for fuses in the PROM

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which are blown by application of current pulses through the output terminals. This allows the user
to program the unit in the laboratory to achieve the desired relationship between input addresses
and stored words. Special units called PROM programmers are available commercially to facilitate
this procedure. In any case, all procedures for programming ROMs are hardware procedures even
though the word programming is used.

EPROMs: The hardware procedure for programming ROMs or PROMs is irreversible and, once
programmed, the fixed pattern is permanent and cannot be altered. Once a bit pattern has been
established, the unit must be discarded if the bit pattern is to be changed. A third type of unit
available is called erasable PROM, or EPROM. EPROMs can be restructured to the initial value
(all 0's or all 1's) even though they have been changed previously. When an EPROM is placed
under a special ultraviolet light for a given period of time, the shortwave radiation discharges the
internal gates that serve as contacts. After erasure, the ROM returns to its initial state and can be
reprogrammed.

EEPROMs: Certain ROMs can be erased with electrical signals instead of ultraviolet light, and
these are called electrically erasable PROMs, or EEPROMs.

8.2 ROM as PLD

k-input- provides address for memory

n outputs – data bits of the stored word selected by address
k address input lines specify 2k words
Rom does not have data inputs because it does not have write operations.

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Example: Implement following functions using ROMs

F1= ∑(1,3,4,6) F2= ∑(2,4,5,7)
F3= ∑(0,1,5,7) F4= ∑(1,2,3,4)

Solution:
First we have to decide that which decoder has been used to implement given example. We have
3 variable functions, so 3-to-8 decoder will be used.

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9 Programmable Logic Array(PLA)
A PLA is similar to a ROM in concept, however, the PLA does not provide full decoding of the
variables and does not generate all the minterms as in the ROM. In PLA, the decoder is replaced
by a group of AND gates, each of which can be programmed to generate product terms of the input
variables. The AND and OR gates inside the PLA are initially fabricated with links among them.
The specific Boolean function is implemented in the sum of products form by opening appropriate
links and leaving the desired connections.

9.1 Block Diagram of PLA

A block diagram of the PLA is shown in Fig. below. It consists of n inputs, m outputs, k product
terms, and m sum terms. The product terms constitute a group of k AND gates and the sum terms
constitute a group of m OR gates. Fuses are inserted between all n inputs and their complement
values to each of the AND gates. Fuses are also provided between the outputs of the AND gates
and the inputs of the OR gates.

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9.2 Simplified diagram of PLA

Example Let us implement the following Boolean functions using PLA.

A=XY+XZ′
B=XY′+YZ+XZ′

The given two functions are in the sum of products form. The number of product terms present in
the given Boolean functions A & B are two and three respectively. One product term, XZ’ is
common in each function.
So, we require four programmable AND gates & two programmable OR gates for producing those
two functions. The corresponding PLA is shown in the following figure.

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The programmable AND gates have the access of both normal and complemented inputs of
variables. In the above figure, the inputs X, X′, Y, Y′, Z & Z′, are available at the inputs of each
AND gate. So, program only the required literals in order to generate one product term by each
AND gate.
All these product terms are available at the inputs of each programmable OR gate. But, only
program the required product terms in order to produce the respective Boolean functions by each
OR gate. The symbol ‘X’ is used for programmable connections.

Example: Realize a Boolean functions F1(A, B, C) = ∑ m(1, 3, 6, 7) and F2(A, B, C) = ∑ m(0, 2,

4, 5) using PLA.

Here, two boolean functions are given in terms of minterms. To obtain the expression, the given
function is implemented using Karnaugh map.

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The realization of the given Boolean function is drawn below.

10 PLA program table and Boolean function Implementation

The use of a PLA must be considered for combinational circuits that have a large number of inputs
and outputs. It is superior to a ROM for circuits that have a large number of don't-care conditions.
Let me explain the example to demonstrate how PLA is programmed.

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10.1 Consider a truth table of the combinational circuit:

PLA implements the functions in their sum of products form (standard form, not necessarily
canonical as with ROM). Each product term in the expression requires an AND gate. It is necessary
to simplify the function to a minimum number of product terms in order to minimize the number
of AND gates used. The simplified functions in sum of products are obtained from the following
maps:

There are three distinct product terms in this combinational circuit: AB’, AC and BC. The circuit
has three inputs and two outputs; so, the PLA can be drawn to implement this combinational
circuit.

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Programming the PLA means, we specify the paths in its AND-OR-NOT pattern. A typical PLA
program table consists of three columns.

First column: lists the product terms numerically.

Second column: specifies the required paths between inputs and AND gates.
Third column: specifies the paths between the AND gates and the OR gates.
Under each output variable, we write a T (for true) if the output inverter is to be bypassed, and C
(for complement) if the function is to be complemented with the output inverter.

Review Questions
1. Derive a PLA program table for the combinational circuit that squares 3-bit numbers to
minimize the number of product terms.
2. Differentiate between PLA and ROM. Implement the given four Boolean functions using
8x4 PLA.
A(x,y,z) = ∑(1,2,4,6)
B(x,y,z) = ∑(0,1,6,7)
C(x,y,z) = ∑(2,6)
D(x,y,z) = ∑(1,2,3,5,7)
3. Design a combinational circuit with four input lines that represent decimal digits in BCD
and four output lines that generate the 9’S complement of the input digits.
4. Design a combinational circuit which takes three input numbers and produces an output
equal to square of inputs.
5. A combinational circuit is defined by the following three functions

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 MSI and LSI Design Unit-6
F1 = x’y’ + xyz’ F2 = x’ + y F3 = xy + x’y’. Design the circuit with a decoder ad
external gate.
6. Design a combinational circuit that accepts a 3-bit number as input and generates the output
binary number equal to the 2’s complement of the input number.
7. Show how a full adder can be converted to a full subtractor with the addition of one inverter
circuit.
8. Implement the following
a. F(A,B,C) = ∑(1,3,5,6) (USING MUX)
b. F(A,B,C) = ∑(0,2,5) F(A,B,C) = ∑(3,4,7) F(A,B,C) = ∑(6,7) USING ROM
9. Design a combinational circuit that converts a decimal digit from 2421 to 84-2-1 code to
binary.
10. Design a comparator circuit that compares two 4-bit numbers. The two numbers are A and
B. It is required to obtain three possible outcomes. i.e. A>B, A<B, and A=B.
11. Design a single combinational logic circuit that performs the addition of two input bits( a
and b) when third-bit c is set to 0 whereas, the same circuit performs the subtraction of the
same two input bits when c is set to 1.
12. What do you mean by Decoder? Implement the following Boolean function F = ∑(1,3,5,6)
using 4:1 MUX.
13. Design a combinational circuit that converts decimal digits from 2421 code to BCD.
14. Design a circuit for 3-bit parity generation and 4-bit parity checker using even parity.
15. Design a combinational circuit that has four inputs and two outputs one of the outputs is
high when all inputs are of the same type.
16. With the help of an example, show how you can construct a higher-order mux using two
or more number of lower-order muxes.
17. Implement a full adder circuit with the help of two half adder circuit along with the truth
table.
18. Design a combinational circuit that has four inputs and two outputs one of the outputs is
high when majority of inputs are high. The second output is high only when all inputs are
of same type.

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 MSI and LSI Design Unit-6
19. Design a combinational circuit using PLD devices as PLA(4*8*4) which is used to
implement the full adder function in which the sum is represented as Si and carry is
represented as Ci+1
20. Implement the following Boolean functions using 16:1 Multiplexers F(A,B,C,D,E) =
∑m(2,4,5,7,10,14,15,16,17,25,26,30,31)
21. Design a code conversion circuit to convert Binary Code into Gray Code.
22. Design a combinational circuit that converts decimal digits from 8-4-2-1 to Excess-3.
23. Design a combinational circuit using PLD devices as PLA(4X8X4) that is used to
implement full subtraction or function in which difference is represented as Di and borrow
as Br.
24. Define the term LSI and MSI. Design a 3:8 decoder with its logic circuit and block diagram,

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

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 Sequential Circuit Unit 7
1 Sequential Switching Circuits
Sequential switching circuits are circuiting whose output levels at any instant of time are dependent
on the level present at the inputs at that time and on the state of the circuit, i.e. on the prior input
level conditions (i.e. on its past inputs). The past history is provided by feedback from the output
back to the input. Such sequential circuits are made up of combinational circuits and memory
elements, e.g. counters, shift registers, serial adders, etc.

Combinational Circuits Sequential Circuits

1. In combinational circuits, the output 1. In sequential circuits, the output variables
variables at any instant of time are at any instant of time are dependent not
dependent only on the present input only on the present input variables but also
variables. on the present state, i.e on the past history
of the system.

2. Memory unit is not required in 2. Memory units are required to store the past
combinational circuits. history of the input variables in sequential
circuits.
3. Combinational circuits are fasters because 3. Sequential circuits are slower than
the delay between the input and the output combinational circuits in output.
is due to the propagational delay of gates
only.
4. Combinational circuits are comparatively 4. Sequential circuits are comparatively harder
easy to design. to design and debug.

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1.1 Synchronous and asynchronous logic

There are two main types of sequential circuits. They can be classified depending on the timing of
their signals.
1. Synchronous sequential circuits.
2. Asynchronous Sequential circuits.

1.2 Synchronous Sequential Circuits

A synchronous sequential logic system must employ signals that affect the memory elements only
at the discrete instant of time. Synchronization is achieved by a timing device called a master clock
generator which generates a periodic train of clock pulses. Synchronous sequential circuits that
use clock pulses in the input of memory elements are called clocked sequential circuits. The
memory elements used in clocked sequential circuits are called a flip-flop.

1.3 Asynchronous Sequential circuit

The behavior of an asynchronous circuit depends upon the order in which its input signals change
and can be affected at any instant in time. The memory elements commonly used in asynchronous
sequential circuits are time-delay devices. The memory capability of a time-delay device is due to
the fact that it takes a finite time for the signal to propagate through the device.

1.4 Clock
It is a control signal that periodically makes a transition from zero to one (0 to 1) and then back to
zero (0) again. We usually denote the clock by the symbol clk, cp.

2 Flip-Flops
The memory elements used in clocked sequential circuits are called flip-flops. These circuits are
binary cells capable of storing one bit of information. A flip-flop circuit has two outputs, one for

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the normal value and one for the complement value of the bit stored in it. Binary information can
enter a flip-flop in a variety of ways, a fact that gives rise to different types of flip-flops.

➢ A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to
the circuit) until directed by an input signal to switch states.
➢ The major differences among various types of flip-flops are in the number of inputs they
possess and in the manner in which the inputs affect the binary state.

2.1 Basic Flip-Flop Circuit (R-S Flip-Flop Circuit)

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These
constructions are shown in the logic diagrams below. Each circuit forms a basic flip-flop upon
which other more complicated types can be built. The cross-coupled connection from the output
of one gate to the input of the other gate constitutes a feedback path. For this reason, the circuits
are classified as asynchronous sequential circuits. Each flip-flop has two outputs, Q and Q', and
two inputs, set and reset.

2.1.1 Nor gate S-R Latch (Active High)

➢ When the SET input is made HIGH, Q becomes 1.

➢ When the RESET input is made HIGH, Q becomes 0.
➢ If both the inputs S and R are made LOW, there is no change in the state of the latch.
➢ If both the inputs are made HIGH, the output is unpredictable i.e. invalid.

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➢ The figure above shows the logic diagram of an active HIGH S-R latch composed of two
cross-coupled NOR gates.
➢ Note that the output of each gate is connected to one of the inputs of the other gate. The
latch works as per the truth table of the figure, where Qn represents the state of the flip-flop
before applying inputs and Qn+1 represents the state of the flip-flop after applying inputs.

2.1.2 NAND gate S-R Latch(Active Low)

➢ The NAND gate is equivalent to an active LOW OR gate, an active LOW S-R latch using
OR gates may also be resented.
➢ The operation of this latch is the reverse of the operation of the NOR gate latch.
➢ If the 0s are replaced by 1s and 1s by 0s, we get the same truth table as that of NOR gate
latch.
➢ The SET and RESET inputs are normally resting in the HIGH state and one of them will
be pulsed LOW, whenever we want to change the latch output.

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2.2 S-R Flip-flop(Gated S-R Latch)

➢ A gated S-R latch requires an ENABLE (EN) input.

➢ Its S and R input will control the state of the flip-flop only when the EN is HIGH.
➢ When EN is LOW, the inputs become ineffective and no change of state can take place.
➢ The EN input may be a clock. So, a gated S-R latch is also called a clocked S-R latch.
➢ Since this type of flip-flop responds to the changes in inputs only as long as the clock is
HIGH, these types of flip-flops are called triggered flip-flops.

2.3 D Flip-flop(Gated D Latch)

➢ It differs from the S-R latch in that it has only one input in addition to EN.

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➢ When D=1, we have S=1 and R=0, causing the latch to SET when ENABLED.
➢ When D=0, we have S=0 and R=1, causing the latch to RESET when ENABLED.
➢ When EN is LOW, the latch is ineffective, and any change in the value of D input does not
affect output at all.
➢ When EN is HIGH, a LOW D input makes Q LOW, i.e. resets the flip-flop and a HIGH D
input makes Q HIGH, i.e. sets the flip-flop. In other words, we can say that the output Q
follows the D input when EN is HIGH.

2.4 J-K Flip-flop (Gated J-K Latch)

➢ The J-K flip-flop is very versatile and also the most widely used.
➢ The functioning of the J-K flip-flop is identical to that of the S-R flip-flop, except that it
has no invalid state like that of the S-R flip-flop.
➢ When J=0 and K=0, no change of state place even if a clock pulse is applied.
➢ When J=0 and K=1, the flip-flop resets at the HIGH level of the clock pulse.
➢ When J=1 and K=0, the flip-flop sets at the HIGH level of the clock pulse.
➢ When J=1 and K=1, the flip-flop toggles, i.e goes to the opposite state at a HIGH level of
the clock pulse.
➢ We can make edge-triggered flip-flops as well as by using positive and negative edges of
the clock instead of HIGH and LOW levels.

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2.5 T Flip-flop (Gated T Latch)

➢ A T flip-flop has a single control input, labeled T for the toggle.

➢ When T is HIGH, the flip-flop toggles on every new clock pulse.
➢ When T is LOW, the flip-flop remains in whatever state it was before.
➢ Although T flip-flops are not widely available commercially, it is easy to convert a J-K
flop to the functional equivalent of a T flip-flop by just connecting J and K together and
labeling the common connection as T.
➢ Thus, when T=1, we have J=K=1 and the flip-flop toggles. When T=0, we have J=K=0,
and so there is no change of state.

2.6 Master-Slave J-K Flip-flop

➢ As shown in figure, the external control inputs J and K are applied to the master section.

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➢ The master section is basically a gated JK latch, with Q output connected back to the input
of G2 and Q output is connected back to the input of G1 and responding to the external J-
K inputs applied to it at the positive edge of the clock signal.
➢ The slave section is the same as the master section except that it is clocked on the inverted
clock pulse and thus responds to its control inputs at the negative edge of the clock pulse.
➢ Thus, the master section assumes the state determined by the J and K inputs at the positive
edge of the clock pulse and the slave section copies the state of the master section at the
negative edge of the clock pulse. The state of the slave then immediately appears on its Q
and Q’ outputs.

3 Triggering of flip-flop
The state of a flip-flop is switched by a momentary change in the input signal. This momentary
change is called a trigger and the transition it causes is said to trigger the flip-flop. Asynchronous
flip-flops require an input trigger defined by a change of signal level clocked flip-flops are
triggered by pulses. There are two types of triggering:

1. Pulse width triggering

2. Edge triggering

3.1 Pulse width triggering

In pulse width triggering the flip-flop changes its state when the clock pulse is equal to logic 1 and
does not change its state when the clock pulse is equal to logic 0.

3.2 Edge triggering

A clock pulse may be either positive or negative. The pulse goes through two signal transitions:
from 0 to 1 and the return from 1 to 0. The positive transition is defined as the positive edge and

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the negative transition as the negative edge. An edge-triggering flip-flop changes its state either at
the positive edge or at a negative edge.

4 Master-slave Flip-Flop
A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master
and the other as a slave, and the overall circuit is referred to as a master-slave flip-flop.

4.1 RS master-slave flip-flop

It consists of a master flip-flop, a slave flip-flop, and an inverter. When the clock pulse CP is 0,
the output of the inverter is 1. Since the clock input of the slave is 1, the flip-flop is enabled and
output Q is equal to Y, while Q' is equal to Y'. The master flip-flop is disabled because CP = 0.
When the pulse becomes 1, the information then at the external R and S inputs is transmitted to
the master flip-flop. The slave flip-flop, however, is isolated as long as the pulse is at its 1 level
because the output of the inverter is 0. When the pulse returns to 0, the master flip-flop is isolated;
this prevents the external inputs from affecting it. The slave flip-flop then goes to the same state
as the master flip-flop.

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4.2 JK Master-slave Flip-Flop
Master-slave JK flip-flop constructed with NAND gates is shown in Fig. below. It consists of two
flip-flops; gates 1 through 4 form the master flip-flop, and gates 5 through 8 forms the slave flip-
flop. The information present at the J and K inputs is transmitted to the master flip-flop on the
positive edge of a clock pulse and is held there until the negative edge of the clock pulse occurs,
after which it is allowed to pass through to the slave flip-flop.

Operation

➢ The clock input is normally 0, which prevents the J and K inputs from affecting the master
flip-flop.
➢ The slave flip-flop is a clocked RS type, with the master flip-flop supplying the inputs and
the clock input being inverted by gate 9.
➢ When the clock is 0, Q = Y, and Q' = Y'.
➢ When the positive edge of a clock pulse occurs, the master flip-flop is affected and may
switch states.
➢ The slave flip-flop is isolated as long as the clock is at the 1 level
➢ When the clock input returns to 0, the master flip-flop is isolated from the J and K inputs
and the slave flip-flop goes to the same state as the master flip-flop.

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5 Excitation table of a flip-flop

5.1 Interconversion of flip-flops

In many applications, we are being given a type of flip-flop, whereas we may require some other
type. In such cases, we may have to convert the given flip-flop to our required flip-flop. Now we
may follow a general model for such conversions of flip-flops. The model is shown in the Figure
below. From the model, we see that it is required to design the conversion logic for converting
new input definitions into input codes that will cause the given flip-flop to work like the desired
flip-flop. To design the conversion logic, we need to combine the excitation table for both flip-
flops and make a truth table with data input(s) and Q as the inputs and the input(s) of the given
flip-flop as the output(s).
Example: With the help of SR flip-flip, realize T flip-flop
Step 1 : (Logic Diagram)

Step 2: Truth Table of required (T) flip-flop

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Step 3: Excitation table of given (SR) flip-flop

Step 4: Truth table of the required flip-flip (combining truth table and excitation table)

Step 5: Finding the expression of given flip in terms of required flip-flop

S = TQ'
and R = TQ.
Step 6 Logic Diagram of the converted Flip-flop

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6 Analysis of Clocked Sequential Circuits

The behavior of a sequential circuit is determined by the inputs, the outputs, and the state of its
flip-flops. The outputs and the next state are both a function of the inputs and the present state.
The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states. It is also possible to write Boolean expressions that describe
the behavior of the sequential circuit. A logic diagram is recognized as a clocked sequential circuit
if it includes flip-flops. The flip-flops may be of any type and the logic diagram may or may not
include combinational circuit gates.

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Let’s discuss the analysis process, along with different terms, with the help of a specific example.

6.1 State Table

The time sequence of input, outputs and flip-flop states may be enumerated in a state table. It
consists of three sections labeled present state, next state, and output. The ‘present state’ designated
the state of flip-flop before the occurrence of clock pulse. The ‘next-state’ shows the state of flip-
flops after the application of a clock pulse and the output section lists the values of the output
variables during the present state. Both the next state and output section has two columns one for
x=0 and the other for x=1.

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6.2 State Diagram
The information available in a state table may be represented graphically in a state diagram. In this
diagram, a state is represented by a circle, and the transition between states is indicated by direct
lines connecting the circles. The binary number inside each circle identifies the state the circle
represents. The directed lines are labeled with two binary numbers represented by a “/”. The input
value that causes the state transition is labeled first; the number after the symbol “/” gives the value
of the output during the present state.

Figure 1: State diagram

6.3 State equation

A state equation (also known as an application equation) is an algebraic expression that specifies
the condition for a flip-flop state transition. The left side of the equation denotes the next state of
a flip-flop and the right side, a Boolean function that species the present state conditions that make
the next state equal to 1.

From the state table, we can reformulate the state table along with the flip-flop and Final
circuit diagram.

7 Design Procedure of Sequential circuit

The design of a clocked sequential circuit starts from a set of specifications (state table) and ends
in a logic diagram or a list of Boolean functions from which the logic diagram can be obtained.
Procedure:

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The procedure can be summarized by a list of consecutive recommended steps:

1. State the word description of the circuit behavior. It may be a state diagram, a timing diagram,
or other pertinent information.
2. From the given information about the circuit, obtain the state table.
3. Apply state-reduction methods if the sequential circuit can be characterized by input-output
relationships independent of the number of states.
4. Assign binary values to each state if the state table obtained in steps 2 or 3 contains letter
symbols.
5. Determine the number of flip-flops needed and assign a letter symbol to each. (6) Choose the
type of flip-flop to be used.
6. From the state table, derive the circuit excitation and output tables.
7. Using the map or any other simplification method, derive the circuit output functions and the
flip-flop input functions.
8. Draw the logic diagram.

Example: The state diagram is shown below. Design the circuit with an appropriate flip-flop.

Step 1: State Diagram

➢ The state diagram consists of four states with binary values already assigned.
➢ Directed lines contain a single binary digit without a slash, we conclude that there is one
input variable and no output variables. (The state of the flip-flops may be considered the
outputs of the circuit).

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➢ The two flip-flops needed to represent the four states are designated A and B.
➢ The input variable is designated x.

Step 2: State Table

➢ The state table for this circuit, derived from the state diagram. Note that there is no output
section for this circuit.

Step 3: Excitation Table

➢ In the derivation of the excitation table, the present state and input variables are arranged
in the form of a truth table.
➢ JK type is used here, Since JK flip-flops are used we need columns for the J and K inputs
of flip-flops A (denoted by JA and KA) and B (denoted by JB and KB)

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Step 4: K-map for circuit reduction

Step 5: Final Logical Circuit

8 State Reduction and Assignment

The analysis of sequential circuits starts from a circuit diagram and culminates in a state table or
diagram. The design of a sequential circuit starts from a set of specifications and culminates in a
logic diagram. Any design process must consider the problem of minimizing the cost of the final
circuit (reducing the number of gates and flip-flops during the design).

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8.1 State Reduction
The reduction of the number of flip-flops in a sequential circuit is referred to as the state-reduction
problem. State-reduction algorithms are concerned with procedures for reducing the number of
states in a state table while keeping the external input-output requirements unchanged.

Example

Consider a sequential circuit with the following specification. States marked inside the circles are
denoted by letter symbols instead of by their binary values.

Consider the input sequence 01010110100 starting from the initial state a. Each input of 0 or 1
produces an output of 0 or 1 and causes the circuit to go to the next state. From the state diagram,
we obtain the output and state sequence for the given input sequence as follows:

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Algorithm:

"Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the
same output and send the circuit either to the same state or to an equivalent state. When two states
are equivalent, one of them can be removed without altering the input-output relationships."

➢ First, we need the state table (from state diagram above)

➢ Look for two present states that go to the same next state and have the same output for both
input combinations. State g and e are two such states: they both go to states a and f and
have outputs of 0 and 1 for x=0 and x=1, respectively. Therefore, states g and e are
equivalent; one can be removed.

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➢ Final reduced table and state diagram for the reduced table consists of only five states.

8.2 State Assignment

The cost of the combinational-circuit part of a sequential circuit can be reduced by using the known
simplification methods for combinational circuits. However, there is another factor, known as the
state assignment problem that comes into play in minimizing the combinational gates. State-
assignment procedures are concerned with methods for assigning binary values to states in such a
way as to reduce the cost of the combinational circuit that drives the flip-flops. Consider a example
shown in state reduction, 3 examples of possible binary assignments are shown in Table below for
the five states of the reduced table. Assignment 1 is a straight binary assignment for the sequence
of states from a through e. The other two assignments are chosen arbitrarily. In fact, there are 140
different distinct assignments for this circuit. The binary form of the state table is used to derive

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the combinational-circuit part of the sequential circuit. The complexity of the combinational circuit
obtained depends on the binary state assignment chosen.

Review Questions
1. Explain in detail about the positive edge triggered J.K flip-flop. Write its advantages over
the S-R flip-flop.
2. With a suitable example explain state reduction and assignment. Also, write the advantages
of state reduction and assignment.
3. Explain the operation of the RS flip-flop with its logic diagram, truth table, and excitation
table.
4. Explain the operation of the JK flip-flop with its logic diagram, truth table, and excitation
table. Why JK flip-flop is preferred over the RS flip-flop?
5. What is the significance of a flip-flop? Explain the J-K flip-flop along with its logic
diagram truth table and excitation table.
6. Differentiate between latches and Flip-flop. Draw JK flip-flop circuit to further convert it
into T flip-flop with state table and state equation.
7. Explain the negative edge triggered S-R flip-flop with the necessary logic diagram,
characteristic table, characteristic equation, and waveform.

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8. How the drawback of the RS flip-flop is overcome in the J-K flip-flop? Explain the J-K
flip-flop in detail?
9. Explain the operation of RS flip-flop with the help of the characteristics table. How it can
be converted into T Flip-flop?
10. Explain the operation of clocked R-S flip-flop with the help of its logic diagram,
characteristics table, and characteristic equation. Differentiate RS and JK flip-flops.
11. With a suitable example explain state reduction and assignment. Also, write the advantages
of state reduction and assignment.
12. Design a sequential circuit corresponding to the given state diagram using J-K flip-flop.

13. Design a sequential circuit corresponding to the given state diagram using S-R flip-flop for
the following state diagram.

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

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1 Register
A register is a group of binary storage cells capable of holding binary information. A group of flip-
flops constitutes a register since each flip-flop can work as a binary cell. An n-bit register has n
flip-flops and is capable of holding n-bits of information. In addition to flip-flops, a register can
have a combinational part that performs data-processing tasks.
Various types of registers are available in MSI circuits. The simplest possible register is one that
contains no external gates and is constructed of only flip-flops. The figure below shows such a
type of register constructed of four S-R flip-flops, with a common clock pulse input. The clock
pulse enables all the flip-flops at the same instant so that the information available at the four
inputs can be transferred into the 4-bit register. All the flip-flops in a register should respond to
the clock pulse transition. Hence, they should be either the edge-triggered type or the master-slave
type. A group of flip-flops sensitive to pulse duration is commonly called a gated latch. Latches
are suitable to temporarily store binary information that is to be transferred to an external
destination. They should not be used in the design of sequential circuits that have feedback
connections.

Figure 1 Basic structure of Register

1.1 Register with parallel load

The transfer of new information into a register is referred to as loading the register. If all the bits
of the register are loaded simultaneously with a single clock pulse, we say that the loading is done
in parallel. A pulse applied to the CP input of the register of figure below will load all four inputs
in parallel. When CP goes to 1, the input information is loaded into the register. If CP remains at

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0, the content of the register is not changed. Note that the change of state in the outputs occurs at
the positive edge of the pulse.

Figure 2 Register with parallel Load

A 4-bit register with a load control input using RS flip-flop is shown in figure above. The CP input
of the register receive continuous synchronized pulses which are applied to all flip-flops. The
inverter in the CP path causes all flip-flop to be triggered by the negative edge of the incoming
pulses.

1.2 Shift Registers

➢ A register capable of shifting its binary information either to the right or to the left is called
a shift register. The logical configuration of a shift register consists of a chain of flip-flops
connected in cascade, with the output of one flip-flop connected to the input of the next
flip-flop. All flip-flops receive a common clock pulse that causes the shift from one stage
to the next.
➢ The Shift Register is used for data storage or data movement and are used in calculators or
computers to store data such as two binary numbers before they are added together, or to

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convert the data from either a serial to parallel or parallel to serial format. The individual
data latches that make up a single shift register are all driven by a common clock (Clk)
signal making them synchronous devices. Shift register IC's are generally provided with a
clear or reset connection so that they can be "SET" or "RESET" as required.

Generally, shift registers operate in one of four different modes with the basic movement of data
through a shift register being:

➢ Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time,
with the stored data being available in parallel form.
➢ Serial-in to Serial-out (SISO) - the data is shifted serially "IN" and "OUT" of the register,
one bit at a time in either a left or right direction under clock control.
➢ Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously
and is shifted out of the register serially one bit at a time under clock control.
➢ Parallel-in to parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.

The effect of data movement from left to right through a shift register can be presented graphically
as:

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1.2.1 Serial-in to Parallel-out (SIPO) Shift Register
Operation
➢ Let’s assume that all the flip-flops (FFA to FFD) have just been RESET (CLEAR input) and
that all the outputs QA to QD are at logic level "0" i.e., no parallel data output.
➢ If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other
outputs still remaining LOW at logic "0".
➢ Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us
one data pulse or 0-1-0.
➢ The second clock pulse will change the output of FFA to logic "0" and the output of FFB and
QB HIGH to logic "1" as its input D has the logic "1" level on it from QA. The logic "1" has
now moved or been "shifted" one place along the register to the right as it is now at QA. When
the third clock pulse arrives this logic "1" value moves to the output of FFC (Q ) and so on
until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to
logic level "0" because the input to FFA has remained constant at logic level "0".
➢ The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in
the register.

Figure 3 Serial input parallel output

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1.2.2 Serial-in to Serial-out (SISO)

This shift register is very similar to the SIPO above, except were before the data was read directly
in a parallel form from the outputs QA to QD, this time the data is allowed to flow straight through
the register and out of the other end. Since there is only one output, the DATA leaves the shift
register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift Register
or SISO. The SISO shift register is one of the simplest of the four configurations as it has only
three connections, the serial input (SI) which determines what enters the left-hand flip-flop, the
serial output (SO) which is taken from the output of the right-hand flip-flop and the sequencing
clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift
register.

Figure 4 Serial input Serial Output

What's the point of a SISO shift register if the output data is exactly the same as the input data?

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→ Well this type of Shift Register also acts as a temporary storage device or as a time delay device
for the data, with the amount of time delay being controlled by the number of stages in the register,
4, 8, 16 etc or by varying the application of the clock pulses.

→Commonly available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register all with
3-state outputs.

1.2.3 Parallel-in to Serial-out (PISO)

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format i.e. all the data bits enter their
inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read out
sequentially in the normal shift-right mode from the register at Q representing the data present at
PA to PD. This data is outputted one bit at a time on each clock cycle in a serial format. It is
important to note that with this system a clock pulse is not required to parallel load the register as
it is already present, but four clock pulses are required to unload the data.

Figure 5 Parallel in Serial Out

→Advantage: As this type of shift register converts parallel data, such as an 8-bit data word into
serial format, it can be used to multiplex many different input lines into a single serial DATA
stream which can be sent directly to a computer or transmitted over a communications line.
→Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

1.2.4 Parallel-in to Parallel-out (PIPO)

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of register
also acts as a temporary storage device or as a time delay device similar to the SISO configuration
above. The data is presented in a parallel format to the parallel input pins PA to PD and then

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transferred together directly to their respective output pins QA to QD by the same clock pulse.
Then one clock pulse loads and unloads the register. This arrangement for parallel loading and
unloading is shown below.

Figure 6 Parallel in Parallel Out

The PIPO shift register is the simplest of the four configurations as it has only three connections,
the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the
sequencing clock signal (Clk). Similar to the Serial-in to Serial-out shift register, this type of
register also acts as a temporary storage device or as a time delay device, with the amount of time
delay being varied by the frequency of the clock pulses. Also, in this type of register, there are no
interconnections between the individual flip-flops since no serial shifting of the data is required.

2 Counters
Counters are one of the simplest types of sequential networks. A counter is usually constructed
from one or more flip-flops that change state in a prescribed sequence when input pulses are
received. A counter driven by a clock can be used to count the number of clock cycles. Since the
clock pulses occur at known intervals, the counter can be used as an instrument for measuring time
and therefore period of frequency. Counters can be broadly classified into three categories:

➢ Asynchronous and Synchronous counters.

➢ Single and multimode counters.
➢ Modulus counters.

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2.1 Ripple Counters (Asynchronous Counters)

These counters are very simple in hardware as well as in operation. It is a series

combination of a flip-flop, where the output of 1st flip-flop is connected as clock input
of 2nd flipflop, the output of 2nd is connected as the clock input of 3rd and so on, it is
called a binary counter, or series counter or ripple counter. The counter in which the
output of one flip-flop drives the clock input of another counter are called a ripple
counter or asynchronous counter.
But these counters have the disadvantage of speed limitation because here each flip-flop
is triggered by previous flip-flop and the total propagation delay time becomes equal
to the sum of the individual propagation delay thereby decreasing the speed of
operation.
2.2 Describe the operation of 4 bit Ripple counter with help of circuit diagram

It uses four negative edge triggered JK flip-flop. All the flip-flop will operate in the toggle mode
because there J and K input are tied to Vcc. The clock pulse are applied to the flip-flop A. The
output of flip-flop A drives clock input of flip-flop B, the output of flip-flop B drives clock input
of flip-flop C and the output of flip-flop C drives clock input of flip- flop D. Since all flip-flop are
negative edge triggered flip-flop they require a transition of 1 to 0 at their clock input to toggle or
change the state.

Truth Table for 4 bit Aysnchronous Counter

Clock D C B A Count
0 (Initially) 0 0 0 0 1
1 0 0 0 1 2

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2 0 0 1 0 3
3 0 0 1 1 4
4 0 1 0 0 5
5 0 1 0 1 6
6 0 1 1 0 7
7 0 1 1 1 8
8 1 0 0 0 9
9 1 0 0 1 10
10 1 0 1 0 11
11 1 0 1 1 12
12 1 1 0 0 13
13 1 1 0 1 14
14 1 1 1 0 15
15 1 1 1 1 16
16 0 0 0 0 17(0)

Operation of Counter
Initially all the flip-flop are cleared by using a common low clear signal. Therefore
DCBA = 0000
On the first clock pulse A flip-flop will toggle from 0 to 1 this will not trigger B flip-flop
because it requires a change in 1 to 0 in A. Therefore B remain in last state and since B does
change its state also C and D remain in last state. Hence on the first clock pulse we get output
as,
DCBA = 0001
On the second clock pulse A flip-flop again toggles from 1 to 0. This now triggers B flip-flop,

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Now B FlipFlop toggles from 0 to 1. This will not affect C flip-flop because C flip-flop requires
a change of 1 to 0 in B flip-flop. Therefore C remains 0 and so is D flip-flop. Hence on 2nd clock
pulse we get
DCBA = 0010.
On the 3rd clock pulse A flip-flop changes from 0 to 1, B flip-flop remains at 1 and C and D flip-
flop remain at 0 therefore,
DCBA = 0011.
On 4th clock pulse A flip-flop changes from 1 to 0 therefore B flip-flop now changes from 1 to
0. Now C flip-flop is triggered which will change from 0 to 1 but this will not effect D because it
requires a change from 1 to 0 in C flip-flop. Hence D remains 0. Therefore or 4th clock pulse we
get,
DCBA = 0100.
Thus it is observed that A flip-flop toggles with every clock pulse it receives. B flip-flop toggles
whenever A flip-flop changes from 1 to 0.
C flip-flop toggles whenever B flip-flop changes from 1 to 0 and D flip-flop toggles whenever C
changes from 1 to 0.
Hence on 15th clock pulse we get DCBA = 1111. On the next clock pulse A flip-flop changes
from 1 to 0, B flip-flop change from 1 to 0. Therefore C flip-flop changes from 1 to 0. Hence D
changes from 1 to 0, therefore all flip-flop are cleared again & we get,
DCBA = 0000
Thus this counter can count from 0 to 15 i.e. totally 16 count (or states). The number of discrete
states through which the counter can progress on the application of pulse is given by 2n where n=
number of flip-flop used into the counter. If we connect 5 flip-flop the counter will progress
through 00000 to 11111 i.e. 32 counts (0 to 31).

Describe operation of Mod 7 or divide by 7 counter

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Mod 7 counter can be constructed from nearest highest modulus counter i.e. mod8 but skipping 1
of state. Fig. Shows mod7 counter with some feedback to skip one of the state. It is convenient to
skip last state i.e. CBA=111 in natural count sequence of the counter. The arrangement is shown
in fig.

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Truth table
Clock C B A
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1(0) (0) 1(0)
Working

During count 7 CBA= 111, if CBA are connected to NAND gate, whenever 111 occurs at the input
of NAND gate the output of NAND gate is low(0). If the output of NAND gate is connected to all
clear inputs of all the flip-flop, as soon as CBA=111 occurs immediately all the flip-flop will clear.
Therefore the counter progress from 110 to 000 and count 111 is skipped. Since remaining states
are only 7 it is called as mod7 counter. fig. Shows the waveform for mod7 counter.

2.2.1 BCD Ripple Counter (Decade Counter)

A decimal counter follows a sequence of ten states and returns to 0 after the count of 9. Such a
counter must have at least four flip-flops to represent each decimal digit, since a decimal digit is
represented by a binary code with at least four bits. The sequence of states in a decimal counter is
dictated by the binary code used to represent a decimal digit.

Figure 7 BCD Ripple Counter

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If BCD is used, the sequence of states is as shown in the state diagram. This is similar to a binary
counter, except that the state after 1001 (code for decimal digit 9) is 0000 (code for decimal digit
0).
Truth Table
➢ This type of asynchronous counter counts upwards on
each trailing edge of the input clock signal starting
from 0000 until it reaches an output 1001 (decimal 9).
Both outputs QA and QD are now equal to logic “1”.
On the application of the next clock pulse, the output
from the 74LS10 NAND gate changes state from logic
“1” to a logic “0” level.
➢ As the output of the NAND gate is connected to the
CLEAR ( CLR ) inputs of all the 74LS73 J-K Flipflops,
this signal causes all of the Q outputs to be reset back
to binary 0000 on the count of 10.
➢ As outputs QA and QD are now both equal to logic “0”
as the flip-flop’s have just been reset, the output of the
NAND gate returns back to a logic level “1” and the
counter restarts again from 0000. We now have a decade or Modulo-10 up-counter.

By using the same idea of truncating counter-output sequences, the above circuit could easily be

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adapted to other counting cycles be simply changing the connections to the inputs of
the NAND gate or by using other logic gate combinations.
Waveform Diagram

2.3 Disadvantages of Asynchronous Counters:

➢ An extra “re-synchronizing” output flip-flop may be required.
➢ To count a truncated sequence not equal to 2n, extra feedback logic is required.
➢ Counting a large number of bits, propagation delay by successive stages may become
undesirably large. This delay gives them the nickname of “Propagation Counters”.
➢ Counting errors occur at high clocking frequencies.
➢ Synchronous Counters are faster and more reliable as they use the same clock signal for
all flip-flops.

2.4 Synchronous Counters

Synchronous counters are distinguished from ripple counters in that clock pulses are applied to the
CP inputs of all flip-flops. The common pulse triggers all the flip-flops simultaneously, rather than
one at a time in succession as in a ripple counter. The decision whether a flip-flop is to be
complemented or not is determined from the values of the J and K inputs at the time of the pulse.

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If J = K = 0, the flip-flop remains unchanged. If J = K = 1, the flip-flop complements. Major types
of Synchronous counters are:

1. Binary Counter
2. Binary-up-down counter
3. BCD decade synchronous counter

2.5 Design Procedure of a Synchronous Counter

The general steps widely adopted to design synchronous counters of any given count sequence can
be designed using the following steps:
Step 1. From the given word description of the problem, draw a state diagram that describes the
operation of the counter.
Step 2. From the state table, write the count sequences in the form of a table.
Step 3. Find the number of flip-flops required using the formula( The number of flip-flops required
in a modulo N counter is [log2(N)])
Step 4. Decide the type of flip-flop to be used for the design of the counter. Then determine the
flip-flop inputs that must be present for the desired next state from the present state using the
excitation table of the flip-flops.
Step 5. Prepare K-maps for each flip-flop input in terms of flip-flop outputs as the input variables.
Simplify the K-maps and obtain the minimized expressions.
Step 6. Connect the circuit using flip-flops and other gates corresponding to the minimized
expressions.
2.6 Example Design of BCD or Decade Synchronous Counter
It is a counter which count binary sequence which has ten distinct states.

Step 1: State Diagram

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Figure 8 State diagram

Step 2: From the state table, write the count sequences in the form of a table as shown in Table.

Figure 9 State table from state diagram

Step 3: Find the number of flip-flops required

In order to design such counter, which has ten distinct states, the number of flip-flops required can
be found using the equation, (2n-1 = N ‘number of distinct states’) where n is the number of flip-
flops required and N is the number of states present in the counter. For N = 10, from the above
equation,

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2n-1 = 10 → 2n =11 → n= 4(since each flip-flop can hold 2 bit 0/1)
Therefore, n = 4, i.e., three flip-flops are required.

Step 4: Decide the type of flip-flop and excitation table

Present State Next State Output Flipflop Inputs

A3 A2 A1 A0 A3+ A2+ A1+ A0+ Y TA3 TA2 TA1 TA0
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 1 0 0 1

Step 5: Prepare K-maps for each flip-flop input in terms of flip-flop outputs as the input variables

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Step 6: Connect the circuit using flip-flops and other gates corresponding to the minimized
expressions

2.7 Synchronous 3 bit up/down counter

1. Decide the number and type of FF
Here we are performing 3 bit or mod-8 Up or Down counting, so 3 Flip Flops are required,
which can count up to 23-1 = 7. Here, T flip-flop is selected
2. Decision for Mode control input M
➢ When M=0 ,then the counter will perform up counting.

➢ When M=1 ,then the counter will perform down counting.

3. Draw the state transition diagram and circuit excitation table

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4. Circuit excitation table

The circuit excitation table represents the present states of the counting sequence and the next
states after the clock pulse is applied and input T of the flip-flops. By seeing the transition between
the present state and the next state, we can find the input values of 3 Flip Flops using the Flip Flops
excitation table. The table is designed according to the required counting sequence.

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5. Find a simplified equation using k map –

Here we are finding the minimal Boolean expression for each Flip Flop input T using k
map.

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6. Create a circuit diagram

The simplified expression for Flip Flops is used to design circuit diagrams. Here all the
connections are made according to simplified expressions for Flip Flops.

Figure 10 UP/DOWN Counter

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3 Mod-N counter
Modulus counters are defined based on the number of states they are capable of counting. This
type of counter can again be classified into two types: Mod N and MOD < N. For example, if there
are n bits then the maximum number counted can be 2n or N. If the counter is so designed that it
can count up to 2n or N states, it is called MOD N or MOD 2n counter. On the other hand, if the
counter is designed to count sequences less than the maximum value attainable, it is called a MOD
< N or MOD < 2n counter

4 Binary Counter
The design of synchronous binary counters is so simple that there is no need to go through a
rigorous sequential-logic design process. In a synchronous binary counter, the flip-flop in the
lowest-order position is complemented with every pulse. This means that it’s J and K inputs must
be maintained at logic-1. A flip-flop in any other position is complemented with a pulse provided
all the bits in the lower-order positions are equal to 1, because the lower-order bits (when all 1's)
will change to 0's on the next count pulse.

Synchronous binary counters have a regular pattern and can easily be constructed with
complementing flip-flops and gates. The regular pattern can be clearly seen from the 4-bit counter
depicted in Fig by side.

The CP terminals of all flip-flops are connected to a common clock-pulse source. The first stage
A1 has its J and K equal to 1 if the counter is enabled. The other J and K inputs are equal to 1 if
all previous low-order bits are equal to 1 and the count is enabled. The chain of AND gates
generates the required logic for the J and K inputs in each stage. The counter can be extended to
any number of stages, with each stage having an additional flip-flop and an AND gate that gives
an output of 1 if all previous flip-flop outputs are 1's.

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4.1.1 Shift Register Counter
Shift registers may be arranged to form different types of counters. These shift registers use
feedback, where the output of the last flip-flop in the shift register is fed back to the first flip-flop.
Based on the type of this feedback connection, the shift register counters are classified as
1. ring counter and
2. twisted ring or Johnson or Shift counter.
4.1.2 Ring Counter
It is possible to devise a counter-like circuit in which each flip-flop reaches the state Q = 1 for
exactly one count, while for all other counts Q = 0. Then Q indicates directly an occurrence of the
corresponding count. Actually, since this does not represent binary numbers, it is better to say that
the outputs of the flip-flops represent a code. Such a circuit is shown in Figure below, which is
known as a ring counter. The Q output of the last stage in the shift register is fed back as the input
to the first stage, which creates a ring-like structure. Hence a ring counter is a circular shift register
with only one flip-flop being set at any particular time and all others being cleared. The single bit
is shifted from one flip-flop to the other to produce the sequence of timing signals.

The circuit shown in Figure below consists of four flip-flops and their outputs are QA, QB, QC, and
QE respectively. The PRESET input of the last fl ip-fl op and the CLEAR inputs of the other three
fl ip-fl ops are connected together. Now, by applying a LOW pulse at this line, the last fl ip-fl op
is SET and all the others are RESET, i.e., QAQBQCQE = 0001. Hence, from the circuit it is clear
that DA = 1, DB = 0, DC = 0, and DE = 0. Therefore, when a clock pulse is applied, the first flip-
flop is set to 1, while the other three flip-flops are reset to 0 i.e., the output of the ring counter is
QAQBQCQE = 1000. Similarly, when the second clock pulse is applied, the 1 in the

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first flip-flop is shifted to the second flip-flop and the output of the ring counter becomes
QAQBQCQE = 0100; on occurrence of the third clock pulse, the output will be QAQBQCQE = 0010;
on occurrence of the fourth clock pulse the output becomes QAQBQCQE = 0001, i.e., the initial
state. Thus, the 1 is shifted around the register as long as the clock pulses are applied. The truth
table that describes the operation of the above 4-bit ring counter is shown in Table above.

Figure 11 Ring Counter

4.1.3 Johnson Counter

The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with feedback
exactly the same as the standard Ring Counter above, except that this time the inverted output Q
of the last flip-flop is now connected back to the input D of the first flip-flop as shown below.

The main advantage of this type of ring counter is that it only needs half the number of flip-flops
compared to the standard ring counter i.e its modulo number is halved. So a “n-stage” Johnson
counter will circulate a single data bit giving sequence of 2n different states and can therefore be
considered as a “mod-2n counter”.

Operation:

This inversion of Q before it is fed back to input D causes the counter to “count” in a different
way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a
4-bit counter, “0001”(1), “0010”(2), “0100”(4), “1000”(8) and repeat, the Johnson counter counts
up and then down as the initial logic “1” passes through it to the right replacing the preceding logic
“0”.

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A 4-bit Johnson ring counter passes blocks of four logic “0” and then four logic “1” thereby
producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern
continually repeats. For example, “1000”, “1100”, “1110”, “1111”, “0111”, “0011”, “0001”,
“0000” and this is demonstrated in the following table below.

Truth Table for a 4-bit Johnson Ring Counter

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5 HAZARDS IN DIGITAL CIRCUITS

In asynchronous sequential circuits it is important that undesirable glitches on signals should not
occur. The designer should be aware of the possible sources of glitches and ensure that the
transitions in a circuit will be glitch free. The glitches caused by the structure of a given circuit
and the propagation delays in the circuit are referred to as hazards.
If, in response to an input change and for some combination of propagation delays, a network
output may momentarily go to 0 when it should remain a constant 1, we say the network has a
static 1-hazard. Similarly, if the network output may momentarily go to 1 when it should remain a
constant 0, we say the network has a static 0-hazard. If when, the output is supposed to change
from 1 to 0 (or 0 to 1), the output may change three or more times, we say the network has a
dynamic hazard.

Figure 12 Hazards in digital design

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 Registers and Counters Unit 8
5.1 Static Hazards
A circuit with a static hazard is shown in Figure below. Suppose that the circuit is in the state
where x1 = x2 = x3 = 1, in which case f = 1. Now let x1 change from 1 to 0. Then the circuit is
supposed to maintain f = 1.

Now we take into consideration the propagation delays through the gates. The change in x1 will
probably be observed at point p before it will be seen at point q. This is since the path from x1 to
q has an extra NOT gate in it. Hence the signal at p will become 0 before the signal at q becomes
equal to 1. Thus, for a short time both p and q will be zero. This causes f to drop to 0 before it can
recover back to 1. This gives rise to a static 1-hazard.

The hazard can be eliminated by including a redundant gate.

5.2 Dynamic Hazards

Dynamic Hazard occurs during a multilevel circuit where the output must make a transition from
0 to 1 or from 1 to 0 but the output makes multiple transitions then settles to a final value. Dynamic
hazard occurs when the output changes for 2 adjacent input combinations while changing, the
output should change on just one occasion . But it’s going to change three or more times briefly
intervals due to different delays in several paths. Dynamic hazards are not easy to detect nor easy
to deal with. The designer can avoid dynamic hazards simply by using two-level circuits and
ensuring that there are no static hazards.

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 Registers and Counters Unit 8
Some Solved

1. Design a synchronous counter that counts the sequence 0,2,3,7 and so on.

Solution:

Step 1: The state diagram is shown in the figure below

Note: Usually unused states are either directed to starting of the counter or end of counter

Step 2: The flip-flops is three and let us assume that J-K flip flops are used.
Three flip-flops are required to represent eight unique states.
Step 3: The excitation table is basically a truth table that gives the necessary J and K inputs to
enable a change in the current output Q to next state Q+. The table below shows the general
excitation table for a J-K flip-flop (with don’t care conditions, X).
Step 4: Using the excitation table, we can obtain the K-maps for each input as shown in the figure
below where present states should be used to draw the K-maps.

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 Registers and Counters Unit 8

K-map construction

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Step 5: Final circuit

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2. A 3-bit Gray code counter (using JK flip-flops)
State diagram

Excitation table

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 Registers and Counters Unit 8
K-MAP

Logical Circuit diagram

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 Registers and Counters Unit 8
Difference between Synchronous and Asynchronous Counter
Synchronous VS Asynchronous Counter
Synchronous Counter Asynchronous Counter
In the synchronous counter, there are continuous clock In Asynchronous counters, different clock
input signals with flip-flops used to produce the output. signals are used to produce the output.

In the Asynchronous counter, the operation

In the synchronous counter, the operation is faster.
is slower.
A synchronous counter is also known as a Parallel The asynchronous counter is also known as
counter. the Serial counter.
A synchronous counter produces less error than the An asynchronous counter produces more
asynchronous counter. errors than a synchronous counter.
The design of the Asynchronous counter is
The design of the Synchronous counter is complex.
simple.
Synchronous counters can work with a flexible number Asynchronous counters can work with a
of count sequences. fixed number of count sequences.

Review Questions
1. What is a shift register? Explain the operation of the Serial-In Serial-Out shift register with
its circuit diagram and timing diagram.
2. Design a 3-bit synchronous binary up counter using JK flip-flop.
3. Describe the read and write operation in RAM with a diagram. Draw a circuit for a 6-bit
SIPO shift register.
4. Design a counter with the following binary sequence 0,1,3,2,6,4,5,7 and repeat. Using T
flip-flop.
5. Design a BCD synchronous up counter using a T-flip-flop.
6. What is a counter? Differentiate between serial in serial out register and parallel in serial
out register with associated diagram.
7. What are the major five differences between synchronous and asynchronous counters?
Design a 4-bit up-down binary counter.
8. Design a MOD 11 asynchronous counter using J K flip-flop and show its working, counting
sequence, and timing diagram.
9. Design a synchronous 4-bit binary up counter using a T flip-flop that counts all possible
odd numbers.

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 Registers and Counters Unit 8
10. What is a modulo-7 counter? Design such a counter using a JK flip-flop.
11. Design a BCD counter that counts the binary sequence from 0000 to 1001 and returns to
0000 to repeat the sequence using T flip-flops.
12. Design a synchronous Mod-6 counter using clocked D flip-flop.
13. Design a 3-bit synchronous Down counter using a T flip-flop.
14. Differentiate between latches and flip-flops. Draw the JK flip-flop circuit to further convert
it into a T flip-flop with a state table and state equation.
15. Differentiate between synchronous and Ripple Counter. Design a 2-bit synchronous UP
counter by using a JK flipflop.
16. . Describe the clocked RS flip-flop and Jonson Counter
17. What is the difference between a serial and parallel transfer? Explain how to convert serial
data to parallel and parallel data to serial. What type of register is needed?
18. Design a counter as shown in the state diagram below

19. Design a sequential circuit using T flop-flip the state diagram is shown below.

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

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 Memory and ALU Unit-9
1 The Memory Unit
The registers in a digital computer may be classified as either operational or storage type. An
operational register is capable of storing binary information in its flip-flops and, in addition, has
combinational gates capable of data-processing tasks. A storage register is used solely for the
temporary storage of binary information. This information cannot be altered when transferred in
and out of the register. A memory unit is a collection of storage registers together with the
associated circuits needed to transfer information in and out of the registers. The storage registers
in a memory unit are called memory registers.
Some of the important basic properties that a memory register should have are:
➢ It must have a reliable two-state property for binary representation
➢ It must be small in size
➢ The cost per bit of storage should be as low as possible
➢ The time of access to a memory register should be reasonably fast.
Examples: Magnetic cores, semiconductor ICs, Drums, disks, etc.
A memory unit stores binary information in groups called words each word being stored in a
memory register. The memory address register specifies the memory word selected. Each word in
memory is assigned a number identification starting from 0 up to the maximum number of words
available. To communicate with a specific memory word its location number, or address, is
transferred to the address register. The internal circuits of the memory unit accept this address from
the register and open the paths needed to select the word called. An address register with n bits
can specify up to 2n memory words. The two control signals applied to the memory unit are called
read and write. A write signal specifies a transfer-in function; a read signal specifies a transfer-out
function. Each is referenced from the memory unit. Upon accepting one of the control signals, the
internal control circuits inside the memory unit provide the desired function.

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 Memory and ALU Unit-9

Figure 1 Block diagram of a memory unit showing communication with the environment

1.1 Memory address register

The memory address register specifies the memory word selected. To communicate with a specific
memory word, its location number or address is transferred to the address register. An address
register with n bits can specify up to 2n memory words.
1.2 Control Signal
The two control signals applied to the memory unit are called read and write. A write signal
specifies a transfer-in function, a and read control signal specifies a transfer-out function.
1.3 Memory Buffer Register
The information transfer to and from the register in memory and the external environment is
communicated through one common register called the memory buffer register [information
register or storage register].
1.4 Read and Write Operation
The sequence of operations needed to communicate with the memory unit for the purpose of
transferring a word out to the Memory Buffer Register (MBR) is:
1. Transfer the address of the selected word into Memory Address Register (MAR).
2. Activate the read control unit.
The binary information presently stored in the memory register is transferred into MBR. The
sequence of operations needed to store a new word in memory is
1. Transfer the address bits of the selected word into MAR

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 Memory and ALU Unit-9
2. Transfer the data bits of the word into MBR
3. Activate the write control input
The data bits from MBR are stored in memory register

2 Random-access Memories
The internal construction of random-access memory of m words with n bits per word consists
of m × n binary storage cells and the associated logic for selecting individual words. The binary
storage cell is the basic building block of a memory unit. IC RAMs are constructed internally with
cells having a wired-OR capability. The figure below shows an IC RAM which consists of 2 words
of 3 bits each, for a total of 6 binary cells.

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 Memory and ALU Unit-9
There are two types of RAM. These are static RAM(SRAM) and dynamic (DRAM).
2.1 Static RAM vs Dynamic RAM

3 Processor Unit
The processor is an important part of a digital computer that performs the various operations in the
system. It may consist of Arithmetic, logical units, control unit, and registers. Different operations
are executed by arithmetic and logic units stored in the register using the instruction set
architecture.

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 Memory and ALU Unit-9
3.1 Arithmetic Logic Units
An arithmetic logic unit (ALU) is a multioperation, combinational-logic digital function. It can
perform a set of basic arithmetic operations and a set of logic operations. The ALU has a number
of selection lines to select a particular operation in the unit. The selection lines are decoded within
the ALU so that the K selection variables can specify up to 2K distinct operations.

The four data inputs from A are combined with the four inputs from B to generate an operation at
the F outputs. The mode selects inputs S2 distinguishes between arithmetic and logic operations.
the two functions’ select inputs S1 and S0 specify the particular arithmetic or logic operations to
be generated. With three selection variables, it is possible to specify four arithmetic operations
(with S2 in one state) and four logic operations (with S2 in another state). The input and output
carries have meaning only during arithmetic operations.
4 Arithmetic Circuit design
Design and adder subtractor circuit with one selection variable and two inputs A and B where S=0,
the circuit performs A+B, and when S=1 circuit performs A-B.
Step 1: General Circuit

Xi Yi Xi Yi

Step 2: Function Selection

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 Memory and ALU Unit-9
S Xi Yi Cin
0 A B 0
1 A B’ 1

Step 3: Truth Table

S A B Xi Yi
0 0 0 0 1
0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0

Step 4: K-map implementation

AB 00 01 11 10
S

0 0 1 1 0
1 1 0 0 1
Yi = S’B+SB’=S XOR B
Xi = A
S= Cin
Step 5: Final Circuit Diagram

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 Memory and ALU Unit-9
4.1 Design an Arithmetic circuit that performs the following operations
1. Addition (A+B) 5. Transfer A F=A(Using B = 0)
2. Addition with carry(A+B+1) 6. Increment A (A+1), B=0
3. A plus 1’s complement of B (A+B’) 7. Decrement A (A-1), B=1
4. Subtraction(A+B’+1) 8. Transfer A (A), Using B=all 1’s

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 Memory and ALU Unit-9
4.2 Design an 4-bit Arithmetic circuit that performs the following operations
1. Addition (A+B) 5. Transfer A F=A(Using B = 0)
2. Addition with carry(A+B+1) 6. Increment A (A+1), B=0
3. A plus 1’s complement of B (A+B’) 7. Decrement A (A-1), B=1
4. Subtraction(A+B’+1) 8. Transfer A (A), Using B=all 1’s

Function Inputs Output Equals Function Selection

Selection X Y Rules :
S1 S0 Cin Note:
0 0 0 A 0 D=A+B Add S0 S1 → 00
SELECTS B
0 0 1 A 0 D= A+B+1 Add with carry S0 S1 → 01
0 1 0 A B D= A+B’ Subtract with borrow SELECTS B’
S0 S1 → 10
0 1 1 A B D= A+B’+1 Subtract SELECTS 0
S0 S1 → 11
1 0 0 A B’ D=A Transfer A SELECTS 1
1 0 1 A B’ D=A+1 Increment A
1 1 0 A ALL 1 D=A-1 Decrement A
1 1 1 A 0/1 D=A Transfer A
Solution:

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 Memory and ALU Unit-9
4.3 Design of Logic Unit
The logic micro-operations manipulate the bits of the operands separately and treat each bit as a
binary variable. With ‘n’ variables we can create 22n functions. If n=2, we create 16 functions but
all these 16 functions can be generated using ‘AND’, ‘OR’, and ‘NOT’ operations.

Example: Design a logic circuit, which can perform following logic operation.

1. OR 5. NOT A
2. NOR 6. NOT B
3. AND 7. X-OR
4. NAND 8. X-NOR

Solution:
For 8 function we use 3 selection line, i.e S2, S1,S0 and input A, B.

Function Table:
Function Output Function
Selection Equals
S2 S1 S0
0 0 0 A+B OR
0 0 1 ̅̅̅̅̅̅̅̅
𝐴+𝐵 NOR
0 1 0 A.B AND
0 1 1 ̅̅̅̅̅
𝐴. 𝐵 NAND
1 0 0 𝐴̅ NOT A
1 0 1 𝐵̅ NOT B
1 1 0 𝐴⨁𝐵 XOR
1 1 1 𝐴⨀𝐵 XNOR

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 Memory and ALU Unit-9
4.4 Design of Arithmetic Logic Unit:
Here, we design an ALU with eight arithmetic operations and four logic operations. Three
selection variables S2, S2 and S0 select eight different operations, and the input carry Cin is used
to select four additional arithmetic operations. With S2=0, selection variables S1 and S0 together
S1 and S0 will select the four logic operations OR, XOR, AND, and NOT.

The steps involved in the design of an ALU are as follows:

1. Design the arithmetic section independent of the logic section.
2. Determine the logic operations obtained from the arithmetic circuit in step 1, assuming that
the input carries to all stages is 0.
3. Modify the arithmetic circuit to obtain the required logic operations.

The Function Table

The circuit whose one stage is given in the below diagram provides 8 arithmetic operations, 4 logic
operations, and 2 shift operations, and Each operation is selected by the 5 variables S3, S2, S1, S0,
and Cin. The table shows the 14 operations perform by the Arithmetic Logic Unit:

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 Memory and ALU Unit-9
The first 8 are arithmetic operations which are selected by S3 S2 = 00
The next 4 are logic operations which are selected by S3 S2 = 01
The last two are shift operations which are selected by S3 S2 = 10 & 11

Final Circuit diagram

Combining the logic above we can get the final circuit as

Figure 2 Alu design

4.5 Status Register:

It is sometimes convenient to supplement the ALU with a status register where these status bit
conditions are stored for further analysis. Status-bits conditions are sometimes called condition-
code bits or flag bits.

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 Memory and ALU Unit-9
The figure below shows the block diagram of an 8-bit ALU with a 4-bit status register. The four
status bits are symbolized by C, S, Z & V. The bits are set or cleared as a result of operations
performed in the ALU.

➢ Bit C is set if the output carry of the ALU is 1. It is cleared if the output carry is 0.
➢ Bit S is set if the highest-order bit of the result in the output of the ALU is 1. It is cleared
if the highest-order bit is 0.
➢ Bit Z is set if the output of the ALU contains all 0’s and cleared otherwise.
➢ Bit V is set if exclusive-OR of carries C8 and C9 is 1, and cleared otherwise. This is the
condition for overflow when the numbers are in sign 2’s complement representation. For
the 8-bit ALU, V is set if the result is greater than 127 or less than -128.

4.6 Shifter:
The shift unit attached to a processor transfers the output of the ALU onto the output bus. The
shifter may transfer the information directly without a shift or it may shift the information to the

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 Memory and ALU Unit-9
right or left. Provision is sometimes made for no transfer from the ALU to the output Bus. The
shifter provides the shift micro operation commonly not available in an ALU.

4.7 Accumulator
Some processor unit distinguish one register from all other and called the accumulator register.
Accumulator register is essentially bi-directional shift register with parallel load which is corrected
to an ALU, the accumulator register and its associated logic when taken as one unit constitute a
sequential circuit. The register A in the figure is referred to as accumulator and is sometimes
denoted by the symbol AC. The external input to the accumulator are the data inputs and ontrol
variables determine the micro-operation for the register. An accumulator is a multifunction register
that by itself can be made to perform all the micro-operation of the processor unit.

Worked out Examples

Design a basic ALU that performs a basic arithmetic function with basic logical function.

Solution:

The design of ALU has three stages.

1. Design the arithmetic section
The basic component of the arithmetic circuit is a parallel adder which is constructed with a
number of full adder circuits connected in cascade. By controlling the data inputs to the parallel
adder, it is possible to obtain different types of arithmetic operations. Below figure shows the
arithmetic circuit and its functional table.

Proposed Function Table

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2. Design the logical section

The basic components of logical circuit are AND, OR, XOR and NOT gate circuits connected
accordingly. Below figure shows a circuit that generates four basic logic micro-operations. It
consists of four gates and a multiplexer. Each of four logic operations is generated through a gate
that performs the required logic. The two selection input S1 and S0 choose one of the data inputs
of the multiplexer and directs its value to the output. Functional table lists the logic operations.

Proposed Function Table

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 Memory and ALU Unit-9

3. Combine these 2 sections to form the ALU

Below figure shows a combined circuit of ALU where n data input from A are combined with n
data input from B to generate the result of an operation at the G output line. ALU has a number of
selection lines used to determine the operation to be performed. The selection lines are decoded
with the ALU so that selection lines can specify distinct operations. The mode select S2
differentiate between arithmetic and logical operations. The two functions select S1 and S0 specify
the particular arithmetic and logic operations to be performed. With three selection lines, it is
possible to specify arithmetic operation with S2 at 0 and logical operation with S2 at 1.

Review Questions
1. Design a 4-bit arithmetic circuit that performs eight different operations. With the help of
a diagram explain how Read/Write operations is performed in RAM.
2. Design an arithmetic circuit with one selection variable and two data inputs A and B, when
S=0, the circuit performs the addition operation F=A+B when S=1, the circuit performs the
addition operation F=A+1(only show the block diagram).

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 Memory and ALU Unit-9
3. Design an adder/subtractor circuit with one selection variable S and two inputs A and B.
When S=0 the circuit performs A+B when S=1 the circuit performs A-B by taking the 2’s
complement of B.
4. Illustrate the process how does binary value of 4 flags in status register change with
necessary diagram.
5. Design
6. Design an arithmetic circuit with two selection variables, S1 and S0, that generates the
following arithmetic operations. Draw the logic diagram of one typical stage.

7. What do you mean by ALU? Design an arithmetic circuit to implement the following
function table A and B are 4 bit binary numbers

8. Explain the process how does binary value of 4 flags in status register change with
necessary diagram.

Write Short Notes on:

1. Status Register
2. Nibble Adder
3. Master Slave F/F
4. PLA
5. Output Hazards Races

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 Memory and ALU Unit-9
6. Magnitude Comparator
7. Universality of NAND and NOR gates
8. Self-Complementing Codes
9. Random Access Memory
10. Universal Gates
11. PLA / Shift register/ D-flip flop
12. Parity method of error detection
13. SOP and POS
14. Accumulator
15. Don’t care conditions
16. Venn diagrams / Edge Triggered Flipflops
17. State Reduction and State Assignment
18. Johnson Counter

Declaration: This document is prepared for academic purposes only, contents from different
sources are subject to their own copyright.

Compiled By: Deepesh Prakash Guragain | Unit 9 | References: Morris Mano 17