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Lecture 10

The document provides an overview of TTL and MOS technology in digital logic design, detailing the structure and operation of various logic gates including NOT, NAND, and NOR gates. It highlights the advantages of MOSFETs and introduces CMOS technology, explaining how it simplifies circuit design by using complementary MOS transistors. Additionally, it poses questions for further exploration of implementing logic gates using TTL and CMOS logic.

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3 views33 pages

Lecture 10

The document provides an overview of TTL and MOS technology in digital logic design, detailing the structure and operation of various logic gates including NOT, NAND, and NOR gates. It highlights the advantages of MOSFETs and introduces CMOS technology, explaining how it simplifies circuit design by using complementary MOS transistors. Additionally, it poses questions for further exploration of implementing logic gates using TTL and CMOS logic.

Uploaded by

shafahtasfia5071
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 33

Heaven’s Light is Our Guide

Department of Computer Science & Engineering


Rajshahi University of Engineering & Technology, Bangladesh

Course Code: CSE 2103


Course Title: Digital Logic Design

Presented by,
Md. Zahirul Islam
The TTL Logic Family
• Most TTL circuits have a similar structure
– NAND and AND gates use multiple-emitter
transistor or multiple diode junction inputs.
– NOR and OR gates use separate input transistors.
• The input will be the cathode of a P-N junction
– A HIGH input will turn off the junction.
• Only a leakage current is generated.
– A LOW input turns on the junction.
• Relatively large current is generated.
• Most TTL circuits have some type of totem-
pole output configuration.
The TTL Logic Family
1. Internal circuit for a TTL NOT gate (Case 1)
The TTL Logic Family
1. Internal circuit for a TTL NOT gate (Case 2)
The TTL Logic Family
2. Internal circuit for a TTL NAND gate (Case 1)
The TTL Logic Family
2. Internal circuit for a TTL NAND gate (Case 2)
The TTL Logic Family
2. Internal circuit for a TTL NAND gate (Case 3)
The TTL Logic Family
2. Internal circuit for a TTL NAND gate (Case 4)
The TTL Logic Family
3. Internal circuit for a TTL NOR gate (Case 1)
The TTL Logic Family
3. Internal circuit for a TTL NOR gate (Case 2)
The TTL Logic Family
3. Internal circuit for a TTL NOR gate (Case 3)
The TTL Logic Family
3. Internal circuit for a TTL NOR gate (Case 4)
Some Questions/Home Works
1. How can you implement AND gate using TTL
Logic?

2. How can you implement OR gate using TTL


Logic?

3. How can you implement Boolean function


using TTL Logic ?
MOS Technology
• MOS technology derives its name from the
basic structure of a metal electrode, over an
oxide insulator, over a semi-conductor
substrate.

– Transistors of MOS technology are field-effect


transistors—called MOSFETs.

The electric field on the metal electrode side of the oxide


insulator has an effect on the resistance of the substrate.
MOS Technology
• Most of the MOS digital ICs are constructed
entirely of MOSFETs and no other components.

Advantages of MOSFETS

• MOSFETs are
1. relatively simple
2. inexpensive to fabricate
3. small and
4. consume very little power
MOS Technology
• There are presently two general types of
MOSFETs—depletion and enhancement.
– MOS ICs use enhancement MOSFETs exclusively.

The direction of the arrow indicates either P- or N-channel. The symbols


show a broken line between the source and the drain to indicate there
is normally no conducting channel between these electrodes.
MOS Technology – Basic MOSFET Switch

• An N-channel MOSFET is the basic element in


a family of devices known as N-MOS.

• Drain is always biased positive relative to the


source.
MOS Technology – Basic MOSFET Switch
• Gate-to-source voltage VGS is the input voltage.
• Where, VGS = VG - VS
• ON/OFF Condition of N-MOS:
a) When VGS > 0 then N – MOS is ON
b) When VGS ≤ 0 then N – MOS is OFF
MOS Technology – Basic MOSFET Switch

• The P-channel MOSFET—P-MOS—operates in


the same manner as the N-channel.
– Except that it uses voltages of opposite polarity.
• The drain is connected to the lower side of the
circuit so it is biased with a more negative
voltage relative to the source.
MOS Technology – Basic MOSFET Switch
• Gate-to-source voltage VGS is the input voltage.
• Where, VGS = VG - VS
• ON/OFF Condition of P-MOS:
a) When VGS < 0 then P – MOS is ON
b) When VGS ≥ 0 then P – MOS is OFF
Summery of N-MOS and P-MOS
Characteristics N – MOS P - MOS

Turning ON If Gate Input = 1 (HIGH) If Gate Input = 0 (LOW)

Condition

Turning OFF If Gate Input = 0 (LOW) If Gate Input = 1 (HIGH)

Condition

INPUT & 1. If Input = 0, then Output = 1 1. If Input = 0, then Output = 1

OUTPUT 2. If Input = 1, then Output = 0 2. If Input = 1, then Output = 0

Application Used in Pulldown Network Used in Pullup Network


Complementary MOS Logic – CMOS Inverter
• P-MOS & N-MOS circuits began to dominate
the LSI and VLSI markets in the 1970s and
1980s.
– Use fewer components & are much simpler to
manufacture than TTL circuits.
• During this era, technology emerged that used
P-MOS & N-MOS transistors in the same
circuit.
– Complementary MOS, or CMOS, technology.
CMOS Inverter
• Pullup Network: Connect the output to VDD
when f (x1, x2 …. xn) = 1

• Pulldown Network: Connect the output to


GND when f (x1, x2 …. xn) = 1
CMOS Inverter
CMOS Inverter
1. Implementing NOT gate

• Not Gate: f = Ā
• Pulldown: f = A
• Pullup: f = Ā
Complementary MOS Logic – CMOS Inverter
• The CMOS INVERTER has two MOSFETs in
series.
– The P-channel device source is connected to VDD .
– The N-channel device has its source connected to
ground—usually labeled VSS.

Basic CMOS INVERTER.


Complementary MOS Logic – CMOS Inverter
• The CMOS INVERTER has two MOSFETs in
series.
– Gates of the two devices are connected together
as a common input.
– Drains are connected together as common output.

Basic CMOS INVERTER.


Complementary MOS Logic
2. Implementing NAND gate
Complementary MOS Logic
• A NAND gate is formed by modifying the basic
INVERTER.
Adding parallel P-channel &
series N-channel MOSFETs
to the basic INVERTER.
Complementary MOS Logic
3. Implementing NOR gate
Complementary MOS Logic
• A CMOS NOR gate.
Formed by adding a series
P-MOS and a parallel N-MOS
to the basic INVERTER.
Some Questions/Home Works
1.How can you implement AND gate using
CMOS Logic?

2. How can you implement OR gate using CMOS


Logic?

3. How can you implement Boolean function


using CMOS (f = A + BC)?
EVERY ENDING
IS REALLY JUST A
NEW BEGINNING

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