(An Autonomous Institution approved by UGC and affiliated to JNTUH))

(Accredited by NAAC with ‘A” Grade, Accredited by NBA of AICTE and

Recipient of World Bank under TEQIP-I and II )
Yamnampet, Ghatkesar Mandal, Hyderabad - 501 301

VLSI Technology and Design LAB MANUAL

For

B. Tech.
III Year - II Semester

ECE Branch

Department of Electronics and Communication Engineering

January 2025
 SREENIDHI INSTITUTE OF SCIENCE AND TECHNOLOGY
(An Autonomous Institution approved by UGC and ‘A’ Grade Awarded by NAAC)

Syllabus for B. Tech (E.C.E.) – A22 regulation

Year/ Sub. Code Subject Name L T P C
Sem
III – II 9C677 VLSI Technology and Design Lab 0 0 3 1.5
Prerequisites: EDC, STLD, LDICA

Course Outcomes: After studying this course, the students will be able to

CO1. Demonstrate the front-end design for various combinational and sequential circuits using Xilinx
Vivado. (L2)
CO2. Implement combinatorial and sequential designs on FPGA boards using Xilinx tools. (L5)
CO3. Develop the back-end EDA tools for the design, simulation and layout for analog circuits. (L3)

VLSI
CO
Technology and PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO
Design Lab 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3

(9C677)
Demonstrate the
front-end design for
various
CO1 combinational and
sequential circuits
using Xilinx
Vivado. (L2)
Implement
combinatorial and
sequential designs
CO2
on FPGA boards
using Xilinx tools.
(L5)
Develop the back-
end EDA tools for
the design,
CO3
simulation and
layout for analog
circuits. (L3)
CO Overall
Syllabus Content
PART A
The following designs are to be simulatedin Xilinx Vivado2017.1 using Verilog HDL (Front-end) and
implement it on 7 series FPGA.
Write HDL program and simulate using testbench program for the following digital circuits
1. Logic Gates.
2. Adders(Half Adder, FullAdder, Parallel Adder).
3. 3-8 Decoder &8-3 Encoder.
4. 8*1Multiplexer & 1*8 Demultiplexer.
5. Flip-flops:D,SR, JK and T.
6. 4-bit Comparator.
PART B
Design, simulate and verify the following circuits using EDA tool (Back-end)
1. CMOS Inverter
2. 2-input CMOS AND/NAND Gate.
3. 2-input CMOS OR/NOR Gate.
4. 2-input CMOS Ex-OR/Ex-NOR Gate.
5. Design and Simulate the Layout diagram for CMOS Inverter using 180nm Technology.
 PROCEDURE FOR FPGA DESIGN FLOW

Introduction
This lab guides you through the process of using Vivado Design Suite to create a simple HDL
design targeting the Nexys4 board. You will simulate, synthesize, and implement the design with
default settings. Finally, you will generate the bitstream and download it in to the hardware to
verify the design functionality

Objectives

After completing this lab, participant can be able to:

□ Create a Vivado project sourcing HDL model(s) and targeting a specific FPGA
device located on the Nexys4 board

□ Use the provided Xilinx Design Constraint (XDC) file to constrain the pin locations
□ Simulate the design using the Vivado simulator
□ Synthesize and implement the design
□ Generate the bitstream
□ Configure the FPGA using the generated bitstream and verify the functionality

Design Example
MASTER SLAVE JK FLIPFLOP(PROCEDURAL FLOW)

Design Objectives:
● To design the Master Slave JK flipflop in structural model using Verilog HDL.
● To write test bench and simulate the design in vivado 16.2 for verifying its
functionality
● To synthesize and implement the design using Artix7 FPGA Board.

Tools used:
PC
Xilinx Vivado Design Suite 2016.2 Tool
Artix 7 FPGA Board

37
PROCEDURE:
Step:1 Create a New Project
1. Open Vivado 16.2, click on create new project and click on Next as illustrated
in following figures.

Fig.1Vivado start window

Fig.2 New project

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2. Specify the project name and location, click on Next as illustrated in Fig.3.

Fig.3 Project name

3. Select RTL project at project type window. The source files can be added after project creation
then new project window will open as illustrated in Fig.4 and tick on Do not specify sources at
this time option and click on Next.

Fig.4 Project Type

39
4. At this window, define the device and project properties as illustrated in Fig.5 click on Next.

Fig.5 Default Part

Step : 2 Add Design sources to created project

5. Then the project navigator will create a new project with following specification as illustrated in
Fig.6, click on Finish

Fig.6 Project summary

40
6. Now go to project manager click on Add source the following window (Fig.7) will appear
select. Add or create design sources option and click on Next

Fig.7 Add Sources

Fig.8 Create Design source

7. Click on create file as illustrated in Fig.8, then create source file window will open as illustrated
in Fig.9.

41
8. Specify file name as msjk and location as illustrated in Fig.9 then click on OK and Finish then
define module window will open.

Fig.9 Create source file

9. Define the I/O ports or you can declare afterwards as illustrated in Fig.10 then click on OK.
Here, all I/O ports are scalar ports.

Fig.10 Module definition

42
 10. Write the program and save it. Again click on Add source to create another file to
write program for MASTER SLAVE JK FLIPFLOP.
11. Specify file type, file name and location as illustrated in Fig.11 then click on OK.

Fig.11 Create source file

⮚ Click on Finish as shown in following Fig.12.

Fig.12 Create file

43
⮚ Define the Module name and Specify the input and output later on ports as illustrated in
Fig.13 and click on OK

Fig.13 Port declaration

Step : 3 Write the program

⮚ Write the program in Program Editor as illustrated in Fig.14

Fig.14 Program Editor

⮚ Save the MSJK program and make MSJK file as top model for that right click on the file and
select set as top model option on doing this the file appears to be as shown in Fig.15.
44
 Fig.15 Program editor

⮚ Save the program and write the test bench. To write test bench go to add source then select add
or simulation sources click on Next as illustrated in Fig.16.

Fig.16 Add Source

45
 ⮚ Click on create file and specify file name, file location and click on OK as illustrated in Fig.17.

Fig.17 Create Source

⮚ Click on Finish and click on OK without defining the i/o ports and write the test bench
as illustrated in Fig.18.

Fig.18 Program Editor

46
Verilog HDL Program:
>>SR LATCH

`timescale 1ns / 1ps

module sr_latch(

input g,

input s,

input r,

output q,

output qn

);

wire s1,r1;

and(s1,g,s);

and (r1,g,r);

nor (qn,s1,q);

nor(q,r1,qn);

endmodule

>>MASTER SLAVE JK

`timescale 1ns / 1ps

module msjk( input c, input j, input k, input rst, output q, output qn);

wire mq,mqn,cn,j1,j2,k1,k2;

assign j2=!rst?0:j1;

assign k2=!rst?1:k1;

and(j1,j,qn);

and(k1,k,q);

not(cn,c);

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sr_latch master(mq,mqn,c,j2,k2);

sr_latch slave(q,qn,cn,mq,mqn);

endmodule

TEST BENCH

`timescale 1ns / 1ps

module mstb( );

reg c,j,k,rst;

wire q,qn;

msjk tb(c,j,k,rst,q,qn);

initial

begin

clk=1'b1;

forever #50 clk=~clk;

end

initial

begin

j=1;k=0;rst=0;

#100 j=1;k=0;rst=1;

#100 j=0;k=1;rst=0;

#100 j=1;k=1;rst=0;

end

endmodule

48
 Step : 4 Simulation
⮚ Save the test bench program and click on run simulation under simulation column in project
manager as illustrated Fig.19

Fig.19 project manager

SIMULATION RESULTS OF MASTER SLAVE JK

⮚ Simulation graphs are illustrated in Fig.20 and Fig.21

Fig.20 Simulation window

49
 Step: 5 RTL Analysis
Before synthesis the RTL schematic can be obtained by clicking on schematic option under RTL
Analysis as illustrated in Fig.21

Fig.21 RTL Analysis

⮚ By clicking the schematic option, RTL schematic can be appeared as illustrated in Fig.22 the
schematic is before synthesis
What is RTL schematic:-
 This is a schematic representation of the pre-optimized design shown at the Register
Transfer Level (RTL). This representation(.ngr file) is in terms of generic symbols, such
as adders, multipliers, counters, AND gates, and OR gates, and is generated after the
HDL synthesis phase of the synthesis process.

Fig.22 RTL Schematic

50
 Step : 6 SYNTHESIS:-
Synthesis is a transformation of high level Verilog/VHDL constructs, which don't have real
physical hardware that can be wired up to do a logic, into low level logical constructs which can
be literally modeled in the form of transistor logic or look - up tables or other FPGA or ASIC
hardware components.

 To perform synthesis click on synthesis option on successful completion of synthesis click

on schematic under open synthesized design option.
 Schematic after synthesis is shown in Fig.23 it is also called Technology schematic
 This is a schematic representation of an NGC file shown in terms of logic elements
optimized to the target architecture or "Technology," for example, in terms of LUTs, carry
logic, I/O buffers, and other technology-specific components. It is generated after the
optimization and technology targeting phase of the synthesis process. Viewing this
schematic allows you to see a technology-level representation of HDL optimized for a
specific Xilinx architecture, which may help to discover design issues

Fig.23 Synthesized Schematic

⮚ Utilization report is illustrated in Fig.24 i.e. in terms of no of LUTs and IOB used in FPGA
Board. .
⮚ Generate the reports such as utilization report and power report

51
 Fig.24Utilisation report
⮚ Power report is indicates the power that our design consumed which is shown in following
Fig.25

Fig.25 Power Report

⮚ After completion of synthesis click on Run implementation under implementation as shown in

Fig.26.

Fig.26 Implementation

52
 IMPLEMENTATION

The Vivado Design Suite implementation process includes logical and physical
transformations of the design. The implementation process consists of the following
sub-processes:
• Optimize Design
Optimizes the logical design to make it easier to fit onto the target Xilinx device.
• Power Optimize Design
Optimizes design elements to reduce the power demands of the target Xilinx device.
Note: This step is optional.
• Place Design
Places the design onto the target Xilinx device.
• Physical Optimize Design
Optimizes design timing by replicating drivers of high-fanout nets to distribute the
loads.
Note: This step is optional.
• Route Design
Routes the design onto the target Xilinx device.

 Click on implement design then device IO planning will be displayed as illustrated in Fig.27

Fig.6.27 IO Planning
⮚ Click on scalar ports option and define the input and output switches and led‟s on FPGA
Board select the I/O Std as LVCMOS 15 as illustrated in Fig.28 this is also called as Xilinx
Design Contraint file (XDC)file and save it

53
 Fig.28 I/O Ports

⮚ After completion of implementation click on Generate Bit stream in order to program the FPGA
as illustrated in Fig.29

Fig.29 Program Debug

⮚ After generation of bit stream the following window will be displayed and click on open
hardware manager as illustrated in Fig.30.

Fig.30 Bit Stream generation

⮚ Connect the FPGA Board i.e NEX YS 4 artix7 shown in Fig.31

54
 Fig.31 NEXYS4 FPGA Board

⮚ Go to program debug and click on open target and select the board and click on program device
as illustrated in Fig.32 and verify the results.

Fig.32 Program Debug

⮚ Observe the final report as illustrated in Fig.33.

55
 Fig.33 Final Project Summary

Result: The design of Master Slave JK

flipflop is simulated, synthesized,
implemented using Verilog HDL in
Vivado 16.2. on Artix7 FPGA kit
and its functionality is verified.
 PART-A

Expt. 1: LOGIC GATES

Aim:
● To design all logic gates.
● To write the Verilog HDL code for the realization of logic gates circuits.
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:

AND GATE : TRUTH TABLE

OR GATE: TRUTH TABLE

NOT GATE : TRUTH TABLE

NAND GATE : TRUTH TABLE

NOR GATE: TRUTH TABLE

24
EXOR GATE: TRUTH TABLE

EXNOR GATE: TRUTH TABLE

Verilog Source Code:

module logicgates (x,y,A,B,C,D,E,F,G); // Starting of module //
Input x,y; // Input variables //
Output A,B,C,D,E,F,G; // Output variables //
assign A= ~x;
assign B= x&y;
assign C= x|y;
assign D= ~(x&y);
assign E= ~(x|y);
assign F= x^y;
assign G= ~(x^y);
endmodule // End of module //

Verilog Testbench Code:

module logicgates_tb;
// Inputs
reg x;reg y;
// Outputs
wire A;wire B;wire C;wire D;wire E;wire F;wire G;
// Instantiate the Unit Under Test (UUT)
logicgates uut (.x(x), .y(y), .A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G));
initial begin
// Initialize Inputs
#100 x = 0; y = 0;
#100 x = 0; y = 1;
#100 x = 1; y = 0;

25
#100 x = 1; y = 1;
end
endmodule

RTL Schematic:

Technology Schematic:

26
Simulated Waveforms:

Synthesis Reports:
Final Report

27
Device utilization summary:

Result:
The design of a Logic gates circuit is obtained and simulated using Verilog HDL in Xilinx
Vivado environment. The design is then synthesized, implemented in Nexys FPGA kit and its
functionality is verified.

28
 Expt. 2: ADDER’S

Aim:
● To design Half adder, Full adder and parallel adder.
● To write the Verilog HDL code for the realization of Half adder, Full adder and parallel
adder.
● To write the test bench and simulate the design in Xilinx vivado environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:
HALF ADDER TRUTH TABLE
A B SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER TRUTH TABLE

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

PARALLEL ADDER

29
Verilog Source Code:
>>HALF ADDER
module hadder(A,B,S,C); // Starting of module //
input A,B; // Declaring Input Variables //
output S,C; // Declaring Output Variables //
assign S=(A^B); // Assigning the vales of logical
operations //
assign C=(A&B);
endmodule // End of module //

>>FULL ADDER
module fadder(A,B,C,S,C0); // Starting of module //
input A,B,C; // Declaring Input Variables //
output S,C0; // Declaring Output Variables //
assign C0=(A&B)|(B&C)|(C&A); // Assigning Values to Logical
expression //
assign S=(A^B^C);
endmodule // End of module //

30
>>PARALLEL ADDER
module pa(
input[3:0]a,
input[3:0]b,
input[3:0]c,
output s,
output c0
);
wire c0,c1,c2;
FA f1(a[0],b[0],c,s[0],c0);
FA f2(a[1],b[1],c,s[1],c1);
FA f3(a[2],b[2],c,s[2],c2);
FA f4(a[3],b[3],c,s[3],c3);
endmodule

Verilog Testbench Code:

>>HALF ADDER
module hadder_tb;
// Inputs
reg A;
reg B;
// Outputs
wire S;
wire C;
// instantiate the unit under test (uut)
ha uut (.a(a), .b(b), .s(s), .c(c));
initial
begin
// initialize inputs
#100 A=0; B=0;

31
#100 A=0; B=1;
#100 A=1; B=0;
#100 A=1; B=1;
End
End module
>>FULL ADDER
module fadder_tb;
//Inputs
reg A;
reg B;
reg C;
//Outputs
Wire S;
Wire C0;
//instantiate the unit under test
fa uut (.a(a), .b(b), .s(s), .c0(c0));
initial
begin
// initialize inputs
#100 A=0;B=0;C=0;
#100 A=0;B=0;C=1;
#100 A=0;B=1;C=0;
#100 A=0;B=1;C=1;
#100 A=1;B=0;C=0;
#100 A=1;B=0;C=1;
#100 A=1;B=1;C=0;
#100 A=1;B=1;C=1;
end
endmodule

>>PARALLEL ADDER
module pa_tb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire cout;
wire [3:0] s;
padder uut (.a(a), .b(b), .cin(cin), .cout(cout), .s(s)); // Instantiate the Unit Under Test
(UUT)
initial
begin
a [3:0]=4’b0000;b [3:0] = 4’b0000;cin = 1’b0;
#100 a[3:0]=4'b1011;b[3:0]=4'b1000;cin=1'b0;

32
 end
endmodule

RTL Schematic:
HALF ADDER

Technology Schematic:

33
Simulated Waveforms:

Synthesis Reports:

Final Report

Device utilization summary

RTL Schematic:
FULL ADDER

34
Technology Schematic:

Simulated Waveforms:

35
Synthesis Report:

Final Report

Device utilization summary

RTL Schematic:
PARALLEL ADDER

36
Technology Schematic:

Simulated Waveforms:

37
Synthesis Report:

Final Report

Device utilization summary

Result:
● The design of half adder, full adder and parallel adder is obtained and simulated using
Verilog HDL in Xilinx Vivado environment. The design is then synthesized,
implemented in Nexys FPGA kit and its functionality is verified.

38
Expt. 3 : 3-8 ENCODER and 8-3 DECODER

Aim:
● To design a 8*3 encoder and 3*8 decoder circuit.
● To write the Verilog HDL code for the realization of 8*3 encoder and 3*8 decoder
circuits.
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:
ENCODER

8 to3
encoder

DECODER

39
ENCODER TRUTH TABLE:
INPUTS OUTPUTS
A B C D E F G H X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

DECODER TRUTH TABLE

INPUTS OUTPUTS
X Y Z A B C D E F G H
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Verilog Source Code:

>> ENCODER
module encoder(a,b,c,d,e,f,g,h,x,y,z); // Starting of module //
input a,b,c,d,e,f,g,h; // Declaring Input
Variables //
output x,y,z; // Declaring Output Variables //
assign x=(e|f|g|h);
assign y=(c|d|g|h); // assigning Values to logical expression //
assign z=(b|d|f|h);
endmodule // End of module //

40
>> DECODER
module decoder(a,b,c,d,e,f,g,h,x,y,z); // Starting of module //
input x,y,z; // Declaring Input Variables //
output a,b,c,d,e,f,g,h; // Declaring Output
Variables //
assign a=(~x)&(~y)&(~z);
assign b=(~x)&(~y)&(z);
assign c=(~x)&(y)&(~z); //Assigning values to logical
Expression//
assign d=(~x)&(y)&(z);
assign e=(x)&(~y)&(~z);
assign f=(x)&(~y)&(z);
assign g=(x)&(y)&(~z);
assign h=(x)&(y)&(z);
endmodule // End of module //

Verilog Testbench:
>> ENCODER
module encoder_tb;
// Inputs
reg a;reg b;reg c;reg d;reg e;reg f;reg g;reg h;
// Outputs
wire x;wire y;wire z;
// Instantiate the Unit Under Test (UUT)
encoder uut
(.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .x(x), .y(y), .z(z));

41
 initial
begin
// Initialize Inputs
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0; // Wait 100 ns for
global reset //to finish
#100 a = 1;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 1;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 1;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 1;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 1;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 1;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 1;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 1;
end
endmodule

>>DECODER
module decoder_tb;
// Inputs
reg x; reg y; reg z;
// Outputs
wire a; wire b; wire c; wire d; wire e; wire f; wire g; wire h;
// Instantiate the Unit Under Test (UUT)
decoder uut
(.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .x(x), .y(y), .z(z));
initial begin

42
 // Initialize Inputs
#100 x=0;y=0;z=0; // Wait 100 ns for global reset to finish
#100 x=0;y=0;z=1;
#100 x=0;y=1;z=0;
#100 x=0;y=1;z=1;
#100 x=1;y=0;z=0;
#100 x=1;y=0;z=1;
#100 x=1;y=1;z=0;
#100 x=1;y=1;z=1;
end
endmodule

RTL Schematic:
ENCODER

43
Technology Schematic:

Simulated Waveforms:

44
Synthesis Reports:

Final Report

Device utilization summary

RTL Schematic:

DECODER

Technology Schematic:

45
Simulated Waveforms:

Synthesis Reports:

46
Final Report

Device utilization summary

Result:
The design of a encoder and decoder circuit is obtained and simulated using Verilog HDL in
Xilinx Vivado environment. The design is then synthesized, implemented in Nexys FPGA kit
and its functionality is verified.

Expt. 4: 8*1 MULTIPLEXER and 1*8 DEMULTIPLEXER

47
Aim:
● To design a 8X1 multiplexer and 1X8 demultiplexer circuit.
● To write the Verilog HDL code for the realization of 8X1 multiplexer and 1X8
demultiplexer circuit .
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board

Logic Diagram and Truth table:

Verilog Source Code:

8x1 Multiplexer:

48
module M8X1(input a, b, c, d, e, f, g, h, x, y,z,
output out );
assign out=((~x)&(~y)&(~z)&a)|((~x)&(~y)&(z)&b)|((~x)&(y)&(~z)&c)|((~x)&(y)&(z)&d)|
((x)&(~y)&(~z)&e)|((~x)&(y)&(~z)&f)|((x)&(y)&(~z))&g|((x)&(y)&(z)&h);
endmodule

1X8 Demultiplexer:

module demux18( // Starting of module //

input i, x, y, z, // Declaring Input Variables //
output a, b, c, d, e, f, g, h); // Declaring Output Variables //
assign a=(~x)&(~y)&(~z)&i;
assign b=(~x)&(~y)&(z)&i;
assign c=(~x)&(y)&(~z)&i;
assign d=(~x)&(y)&(z)&i; // Assigning values to logical expression //
assign e=(x)&(~y)&(~z)&i;
assign f=(x)&(~y)&(z)&i;
assign g=(x)&(y)&(~z)&i;
assign h=(x)&(y)&(z)&i;
endmodule // End of module //

Verilog Test bench Code:

8x1 Multiplexer:

module MUX8X1_TB;
reg a; reg b; reg c; reg d; reg e; reg f; reg g; reg h; reg x; reg y; reg z;
wire out;
M8X1 uut (.a(a), .b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.x(x),.y(y),.z(z),.out(out));
initial begin
a = 1; b = 0; c = 1; d = 0; e = 1; f = 0; g = 1; h = 0;x = 0; y = 0; z = 0;
#100; x = 0; y = 0; z = 1;
#100; x = 0; y = 1; z = 0;
#100; x = 0; y = 1; z = 1;
#100; x = 1; y = 0; z = 0;
#100; x = 1; y = 0; z = 1;
#100; x = 1; y = 1; z = 0;
#100; x = 1; y = 1; z = 1;
end

49
 endmodule

1X8 Demultiplexer:

module demux18_tb;
reg i; reg x; reg y; reg z;
wire a; wire b; wire c; wire d; wire e; wire f; wire g; wire h;
demux18 uut (.i(i),.x(x),.y(y),.z(z),.a(a),.b(b),.c(c), .d(d),.e(e),.f(f),.g(g),.h(h));
initial begin
i = 1;
x = 0; y = 0; z = 0;
#100; x = 0; y = 0; z = 1;
#100; x = 0; y = 1; z = 0;
#100; x = 0; y = 1; z = 1;
#100; x = 1; y = 0; z = 0;
#100; x = 1; y = 0; z = 1;
#100; x = 1; y = 1; z = 0;
#100; x = 1; y = 1; z = 1;
end
endmodule

RTL Schematic:

Multiplexer:

Technology Schematic:

50
Simulated Waveform:

Multiplexer:

Synthesis Reports:

Final Report

51
Device utilization summary

RTL Schematic:
Demultiplexer:

Technology Schematic:

52
Simulated Waveform:

Synthesis Reports:

53
Final Report

Device utilization summary

Result:

● The design of a 8X1 multiplexer and 1X8 demultiplexer circuit is obtained and simulated
using Verilog HDL in Xilinx Vivado environment. The design is then synthesized,
implemented in Nexys FPGA kit and its functionality is verified.

54
 Expt. #5 a) D flip-flop

Aim:
● To design a D flip-flop circuit.
● To write the Verilog HDL code for the realization of D flip-flop circuit .
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:

Truth table:

CLK D Q
0 X LAST STATE
1 0 0

1 1 1

Verilog Source Code:

Verilog Testbench Code:

55
RTL Schematic:

Technology Schematic:

56
Simulation:

Synthesis Reports:
Final Report

Device utilization summary

57
Result:
The design of a D flip-flop circuit is obtained and simulated using Verilog HDL in Xilinx
Vivado environment. The design is then synthesized, implemented in Nexys FPGA kit and its
functionality is verified.

58
Expt. 5b)T flip-flop

Aim:
● To design a T flip-flop circuit.
● To write the Verilog HDL code for the realization of T flip-flop circuit .
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:

Truth table:

Verilog Source Code:

Verilog Testbench Code:

59
RTL Schematic:

Technology Schematic:

60
Simulation:

Synthesis Reports:
Final Report

Device utilization summary

61
Result:
The design of a T flip-flop circuit is obtained and simulated using Verilog HDL in Xilinx Vivado
environment. The design is then synthesized, implemented in Nexys FPGA kit and its
functionality is verified.

62
Expt. # 5c) JK flip-flop

Aim:
● To design a JK flip-flop circuit.
● To write the Verilog HDL code for the realization of JK flip-flop circuit .
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:

Truth table:

63
Verilog Source Code:

Verilog Testbench Code:

RTL Schematic:

64
Technology Schematic:

Simulation:

Synthesis Reports:

65
Final Report

Device utilization summary

Result:
The design of a JK flip-flop circuit is obtained and simulated using Verilog HDL in Vivado
environment. The design is then synthesized, implemented in Nexys FPGA kit and its
functionality is verified.

66
Expt. 5d) RS flip-flop

Aim:
● To design a RS flip-flop circuit.
● To write the Verilog HDL code for the realization of RS flip-flop circuit .
● To write the test bench and simulate the design in Xilinx Vivado design environment for
verifying its functionality.
● To synthesize the design, implement it on Nexys 4 Artix-7 FPGA Trainer Board and
verify its functionality.
Apparatus:
● Computer System
● Xilinx Vivado 2017.1
● Nexys 4 Artix-7 FPGA Trainer Board
Logic Diagram:

Truth table:

Verilog Source Code:

67
Verilog Testbench Code:

RTL Schematic:

68
Technology Schematic:

Simulation:

Synthesis Reports:

69
Final Report

Device utilization summary

Result:
The design of a RS flip-flop circuit is obtained and simulated using Verilog HDL in Xilinx
Vivado environment. The design is then synthesized, implemented in Nexys FPGA kit and its
functionality is verified.

70
 PART-B

PROCEDURE FOR ANALOG DESIGN USING CADENCE TOOL

Start up the procedure by giving right click and opening terminal, a terminal window will be
opened as shown in below figure.

Type the command“virtuoso &”in the terminal window and press enter,following windows will
be displayed.what’s new window is not required,close that window.

Creation of new library:

Select File -> New -> Library. A new window appears.
a) Enter a library name
b) Choose Attach to an existing technology library.
c) Choose your technology whether gpdk 180nm or gpdk 45nm.

71
Now a new library is created which will be displayed in CIW window.

Creation of cell view:

Go to file->new->cell view
A dialog box opens where we need to select the library which was created by us so that the
schematic gets saved in that particular library.Give name of the circuit which has to be
implemented and click ok.

After clicking ok,a blank schematic window will be displayed as shown in below figure.

Adding components,pins and wires to schematic:

In the schematic window,press “i” and browse and select gpdk045,then add the pmos and nmos
transistors. Press “p” and add input and output pins.press “w” and complete the wiring.

72
After creating schematic,save and check it,check for errors in CIW window,if there are no
errors,proceed for next step.
Symbol creation:
In the schematic window, select create-cell view-from cell view.

73
Click on ok,following window will be displayed,modify the pin specifications and click ok.

Now a symbol window will be opened as

shown in below figure.

Now create symbol using lines,arcs etc.. which is shown in below figure.

After creating the symbol,check and save the symbol,if there are no errors,proceed for next step.

Creating test design:

74
In CIW or library manager,select file-new-cell view,give a cell name for test design,following
window will be displayed,click ok,a blank test design window will be opened.

Now,create a test design by using created symbol and analog library which is shown in below
figure.

75
After creating the test design,check and save the design,if there are no errors in the
design,proceed to next step.

Simulation:
To verify the functionality:
● Go to launch->ADEL(analog design environment)
● Go for analysis
● Choose trans
● Select stop time
● Press ok

76
 Go to set up->design->choose design and click ok.

Go to set up->module library->select technology and click ok.

Go to output->to be plotted->select on design,click on input and output lines,then click on run

button in ADE window,following simulation waveform window will be displayed.

Thus the implementation of nand gate is done and its functionality is verified using cadence
tool.

77
 PART-B
Expt.#1 a) CMOS INVERTER

Aim:
● To design inverter using CMOS logic .

Apparatus:
● PC with REDHAT linux operating system
● Cadence tool

Schematic diagram:

Symbol:

Circuit diagram:

78
Experimental Procedure:
1. Right click and open terminal,then create a new library with gpdk045 technology.
2. Create a new cell view,a new schematic window will be opened,draw the schematic and
save it by clicking on check and save.
3. If there are 0 errors and 0 warnings in schematic go to next step to create a symbol.
4. Using the created symbol,draw the circuit and give power supply connections using
analog library.
5. If there are 0 errors and 0 warnings in the circuit,simulate the circuit and observe the
output waveforms for different input combinations.
Simulated Waveforms:

Result:
The design of inverter is done using cadence tool. Its operation is observed and waveforms are
obtained.

79
Expt.#2 a) 2-input CMOS AND GATE

Aim:
● To design AND GATE using CMOS logic .
Apparatus:
● PC withREDHAT linux operating system
● Cadence tool
Schematic diagram:

Symbol:

Circuit diagram:

80
Experimental Procedure:
6. Right click and open terminal,then create a new library with gpdk045 technology.
7. Create a new cell view,a new schematic window will be opened,draw the schematic and
save it by clicking on check and save.
8. If there are 0 errors and 0 warnings in schematic go to next step to create a symbol.
9. Using the created symbol,draw the circuit and give power supply connections using
analog library.
10. If there are 0 errors and 0 warnings in the circuit,simulate the circuit and observe the
output waveforms according to the simulation steps.
Simulated Waveforms:

Result:
The design of AND GATE is done using cadence tool. Its operation is observed and waveforms
are obtained.

81
Expt.#2 b) CMOS NAND GATE

Aim:
● To design NAND GATE using CMOS logic .

Apparatus:
● PC withREDHAT linux operating system.
● Cadence tool
Schematic diagram:

Symbol:

Circuit diagram:

82
Experimental Procedure:
11. Right click and open terminal,then create a new library with gpdk045 technology.
12. Create a new cell view,a new schematic window will be opened,draw the schematic and
save it by clicking on check and save.
13. If there are 0 errors and 0 warnings in schematic go to next step to create a symbol.
14. Using the created symbol,draw the circuit and give power supply connections using
analog library.
15. If there are 0 errors and 0 warnings in the circuit,simulate the circuit and observe the
output waveforms according to the simulation steps.
Simulated Waveforms:

Result:
The design of NAND GATE is done using cadence tool. Its operation is observed and
waveforms are obtained.

83
Expt.#3 a) CMOS OR GATE

Aim:
● To design OR gate using CMOS logic .
Apparatus:
● PC with REDHAT linux operating system
● Cadence tool
Schematic diagram:

Symbol:

Circuit diagram:

84
Experimental Procedure:
16. Right click and open terminal,then create a new library with gpdk045 technology.
17. Create a new cell view,a new schematic window will be opened,draw the schematic and
save it by clicking on check and save.
18. If there are 0 errors and 0 warnings in schematic go to next step to create a symbol.
19. Using the created symbol,draw the circuit and give power supply connections using
analog library.
20. If there are 0 errors and 0 warnings in the circuit,simulate the circuit and observe the
output waveforms according to the simulation steps.
Simulated Waveforms:

Result:
The design of OR gate is done using cadence tool. Its operation is observed and waveforms are
obtained.

85
Expt.#3 b) CMOS NOR GATE

Aim:
● To design NOR GATE using CMOS logic .
Apparatus:
● PC with REDHAT linux operating system
● Cadence software
Schematic diagram:

Symbol:

Circuit diagram:

86
Experimental Procedure:
21. Right click and open terminal,then create a new library with gpdk045 technology.
22. Create a new cell view,a new schematic window will be opened,draw the schematic and
save it by clicking on check and save.
23. If there are 0 errors and 0 warnings in schematic go to next step to create a symbol.
24. Using the created symbol,draw the circuit and give power supply connections using
analog library.
25. If there are 0 errors and 0 warnings in the circuit,simulate the circuit and observe the
output waveforms according to the simulation steps.
Simulated Waveforms:

Result:
The design of NOR GATE is done using cadence tool. Its operation is observed and waveforms
are obtained.

87
88