Module 2: Digital VLSI Circuits

Lecture 14: Advanced CMOS Logic (Dynamic CMOS, Domino CMOS, NORA CMOS etc.)
14.1 Dynamic CMOS Logic
It was noted earlier that static CMOS logic with a fan-in of N requires 2N devices. A variety of approaches
were presented to reduce the number of transistors required to implement a given logic function including
pseudo-NMOS, pass transistor logic, etc. The pseudo-NMOS logic style requires only N + 1 transistors to
implement an N input logic gate, but unfortunately it has static power dissipation. In this section, an alternate
logic style called dynamic logic is presented that obtains a similar result, while avoiding static power
consumption. With the addition of a clock input, it uses a sequence of precharge and conditional evaluation
phases.

Basic Principles
The basic construction of an (n-type) dynamic logic gate is shown in the following figure. The PDN (pull-
down network) is constructed exactly as in complementary CMOS. The operation of this circuit is divided
into two major phases: precharge and evaluation, with the mode of operation determined by the clock signal
CLK ().
Precharge
When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor Mp. During that time,
the evaluate NMOS transistor Me is off, so that the pull-down path is disabled. The evaluation FET
eliminates any static power that would be consumed during the precharge period (this is, static current
would flow between the supplies if both the pull down and the precharge device were turned on
simultaneously).
Evaluate
For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned on. The output
is conditionally discharged based on the input values and the pull-down topology. If the inputs are such that
the PDN conducts, then a low resistance path exists between Out and GND and the output is discharged to
GND. If the PDN is turned off, the precharged value remains stored on the output capacitance CL, which is
a combination of junction capacitances, the wiring capacitance, and the input capacitance of the fan-out
gates. During the evaluation phase, the only possible path between the output node and a supply rail is to
GND. Consequently, once Out is discharged, it cannot be charged again till then next precharge operation.
The inputs to the gate can therefore make at most one transition during evaluation.
14.2 A number of important properties can be derived for the dynamic logic gate:
• The logic function is implemented by the NMOS pull-down network. The construction of the PDN
proceeds just as it does for static CMOS.
• The number of transistors (for complex gates) is substantially lower than in the static case: N + 2 versus
2N.
• It is non-ratioed. The sizing of the PMOS precharge device is not important for realizing proper
functionality of the gate. The size of the precharge device can be made large to improve the low-to-high
transition time (of course, at a cost to the high-to low transition time). There is however, a trade-off with
power dissipation since a larger precharge device directly increases clock-power dissipation.
• It only consumes dynamic power. Ideally, no static current path ever exists between VDD and GND. The
overall power dissipation, however, can be significantly higher compared to a static logic gate.
• The logic gates have faster switching speeds. There are two main reasons for this. The first (obvious)
reason is due to the reduced load capacitance attributed to the lower number of transistors per gate and the
single-transistor load per fan-in. Second, the dynamic gate does not have short circuit current, and all the
current provided by the pull-down devices goes towards discharging the load capacitance.

The dynamic logic circuits offer following advantages over standard CMOS logic circuits.
 Low power dissipation
 Small area due to less number of transistors
 Large noise margin.

14.3 Cascading Problem in Dynamic Logic

However, the dynamic CMOS logic circuit has a serious problem when they are cascaded. The problem is
best illustrated with the two cascaded n-type dynamic inverters, shown in Figure a. During the precharge
phase (i.e., CLK =0), the outputs of both inverters are precharged to VDD. Assume that the primary input In
makes a 0 to 1 transition (Figure b). On the rising edge of the clock, output Out1 starts to discharge. The
second output should remain in the precharged state of VDD as its expected value is 1 (Out1 transitions to 0
during evaluation). However, there is a finite propagation delay for the input to discharge Out1 to GND.
Therefore, the second output also starts to discharge. As long as Out1 exceeds the switching threshold of
the second gate, which approximately equals VTn, a conducting path exists between Out2 and GND, and
precious charge is lost at Out2. The conducting path is only disabled once Out1 reaches VTn, and turns off
the NMOS pull-down transistor. This leaves Out2 at an intermediate voltage level. The correct level will
not be recovered, as dynamic gates rely on capacitive storage in contrast to static gates, which have dc
restoration. The charge loss leads to reduced noise margins and potential malfunctioning.
A number of design styles complying with this rule have been conceived.

14.4 Domino CMOS logic

Domino CMOS logic is s slightly modified version of the dynamic CMOS logic circuit. In this case, a static
inverter is connected at the output of each dynamic CMOS logic blocks. The addition of the inverter solves
the problem of cascading of dynamic CMOS logic circuits.

Figure: Cascaded domino CMOS logic circuit.

In the pre-charge phase ( = 0), the outputs of the dynamic CMOS logic circuits are pre-charged to logic
high and the output the static inverter is logic low. In the evaluation phase ( = 1), outputs of the dynamic
CMOS logic circuits can either go to logic low and or remain at logic high. Consequently, output of the
static inverter can make only a 0-1 transition. So irrespective of the input logic output of the static inverter
cannot make a 1-0 transition.
Summary:
Domino CMOS helps in reducing the number of transistors as compared to the static CMOS logic. In static
CMOS logic we require 2N transistors to implement an N-input logic function. However, in dynamic CMOS
logic we require only N +2 transistors and for Domino CMOS logic two additional transistors are required.
It also solves the cascading problem of dynamic CMOS logic. But it is suitable only for non-inverting logic
(the expressions having no complement over whole expression). For inverting logic the expression must be
reorganized (to remove the complement over whole expression) before it can be realized using domino
CMOS logic.
14.5 NORA CMOS logic (np-CMOS)
The Domino logic presented in the previous section has the disadvantage that each dynamic gate requires an extra
static inverter in the critical path to make the circuit functional.np-CMOS, provides an alternate approach to cascading
dynamic logic by using two flavors (n-tree and p-tree) of dynamic logic. In a p-tree logic gate, PMOS devices are used
to build a pull-up logic network, including a PMOS evaluation transistor (Figure). The NMOS predischarge transistor
drives the output low during precharge. The output conditionally makes a 0 ® 1 transition during evaluation depending
on its inputs.

np-CMOS logic exploits the duality between n-tree and p-tree logic gates to eliminate the cascading
problem. If the n-tree gates are controlled by CLK, and p-tree gates are controlled using CLK, n-tree gates
can directly drive p-tree gates, and vice-versa. Similar to Domino, n-tree outputs must go through an
inverter when connecting to another n-tree gate. During the precharge phase (CLK = 0), the output of the
n-tree gate, Out1, is charged to VDD, while the output of the p-tree gate, Out2, is pre-discharged to 0V.
Since the n-tree gate connects PMOS pull-up devices, the PUN of the p-tree is turned off at that time.
During evaluation, the output of the n-tree gate can only make a 1®0 transition, conditionally turning on
some transistors in the p-tree. This ensures that no accidental discharge of Out2 can occur. Similarly, n-tree
blocks can follow p-tree gates without any problems, as the inputs to the n-gate are precharged to 0. A
disadvantage of the np-CMOS logic style is that the p-tree blocks are slower than the n-tree modules, due
to the lower current drive of the PMOS transistors in the logic network. Equalizing the propagation delays
requires extra area.

14.6 Zipper CMOS logic

The basic circuit architecture of Zipper CMOS is essentially identical to NORA CMOS or np-CMOS with
the exception of the clock signals. The Zipper CMOS clock scheme requires the generation of slightly
different clock signals for the precharge (discharge) transistors and for the pull-down (pull-up) transistors.
In particular, the clock signals which drive the pMOS precharge and nMOS discharge transistors allow
these transistors to remain in weak conduction or near cut-off during the evaluation phase, thus
compensating for the charge leakage and charge-sharing problems. The generalized circuit diagram and the
clock signals of the Zipper CMOS architecture are shown in figure.
 Zipper CMOS Logic

Clock scheme of zipper CMOS logic

----------------------------------------------------END OF LECTURE---------------------------------------
Reference:
1. CMOS Digital Integrated Circuit, S.M.Kang & Y.Leblebici, TMH.
2. VLSI Design, Debaprasad Das, OUP
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Prepared By
Tapas Tewary and Subham Pramanik, ECE Department, Academy of Technology